include/configs/MPC8308RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15
  16 #ifdef CONFIG_MMC
  17 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  18 #define CONFIG_SYS_FSL_ESDHC_USE_PIO
  19 #endif
  20
  21 /*
  22  * On-board devices
  23  *
  24  * TSEC1 is SoC TSEC
  25  * TSEC2 is VSC switch
  26  */
  27 #define CONFIG_TSEC1
  28 #define CONFIG_VSC7385_ENET
  29
  30 /*
  31  * System Clock Setup
  32  */
  33 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
  34 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  35
  36 /*
  37  * Hardware Reset Configuration Word
  38  * if CLKIN is 66.66MHz, then
  39  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  40  * We choose the A type silicon as default, so the core is 400Mhz.
  41  */
  42 #define CONFIG_SYS_HRCW_LOW (\
  43         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  44         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  45         HRCWL_SVCOD_DIV_2 |\
  46         HRCWL_CSB_TO_CLKIN_4X1 |\
  47         HRCWL_CORE_TO_CSB_3X1)
  48 /*
  49  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  50  * in 8308's HRCWH according to the manual, but original Freescale's
  51  * code has them and I've expirienced some problems using the board
  52  * with BDI3000 attached when I've tried to set these bits to zero
  53  * (UART doesn't work after the 'reset run' command).
  54  */
  55 #define CONFIG_SYS_HRCW_HIGH (\
  56         HRCWH_PCI_HOST |\
  57         HRCWH_PCI1_ARBITER_ENABLE |\
  58         HRCWH_CORE_ENABLE |\
  59         HRCWH_FROM_0X00000100 |\
  60         HRCWH_BOOTSEQ_DISABLE |\
  61         HRCWH_SW_WATCHDOG_DISABLE |\
  62         HRCWH_ROM_LOC_LOCAL_16BIT |\
  63         HRCWH_RL_EXT_LEGACY |\
  64         HRCWH_TSEC1M_IN_RGMII |\
  65         HRCWH_TSEC2M_IN_RGMII |\
  66         HRCWH_BIG_ENDIAN)
  67
  68 /*
  69  * System IO Config
  70  */
  71 #define CONFIG_SYS_SICRH (\
  72         SICRH_ESDHC_A_SD |\
  73         SICRH_ESDHC_B_SD |\
  74         SICRH_ESDHC_C_SD |\
  75         SICRH_GPIO_A_TSEC2 |\
  76         SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
  77         SICRH_IEEE1588_A_GPIO |\
  78         SICRH_USB |\
  79         SICRH_GTM_GPIO |\
  80         SICRH_IEEE1588_B_GPIO |\
  81         SICRH_ETSEC2_CRS |\
  82         SICRH_GPIOSEL_1 |\
  83         SICRH_TMROBI_V3P3 |\
  84         SICRH_TSOBI1_V2P5 |\
  85         SICRH_TSOBI2_V2P5)      /* 0x01b7d103 */
  86 #define CONFIG_SYS_SICRL (\
  87         SICRL_SPI_PF0 |\
  88         SICRL_UART_PF0 |\
  89         SICRL_IRQ_PF0 |\
  90         SICRL_I2C2_PF0 |\
  91         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000040 */
  92
  93 /*
  94  * IMMR new address
  95  */
  96 #define CONFIG_SYS_IMMR         0xE0000000
  97
  98 /*
  99  * SERDES
 100  */
 101 #define CONFIG_FSL_SERDES
 102 #define CONFIG_FSL_SERDES1      0xe3000
 103
 104 /*
 105  * Arbiter Setup
 106  */
 107 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
 108 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
 109 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
 110
 111 /*
 112  * DDR Setup
 113  */
 114 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 115 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 116 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 117 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 118 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 119                                 | DDRCDR_PZ_LOZ \
 120                                 | DDRCDR_NZ_LOZ \
 121                                 | DDRCDR_ODT \
 122                                 | DDRCDR_Q_DRN)
 123                                 /* 0x7b880001 */
 124 /*
 125  * Manually set up DDR parameters
 126  * consist of two chips HY5PS12621BFP-C4 from HYNIX
 127  */
 128
 129 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 130
 131 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 132 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 133                                 | CSCONFIG_ODT_RD_NEVER \
 134                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 135                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 136                                 /* 0x80010102 */
 137 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 138 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 139                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 140                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 141                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 142                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 143                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 144                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 145                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 146                                 /* 0x00220802 */
 147 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 148                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 149                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 150                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 151                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
 152                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 153                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 154                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 155                                 /* 0x27256222 */
 156 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 157                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 158                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 159                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 160                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 161                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 162                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 163                                 /* 0x121048c5 */
 164 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 165                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 166                                 /* 0x03600100 */
 167 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 168                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 169                                 | SDRAM_CFG_DBW_32)
 170                                 /* 0x43080000 */
 171
 172 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 173 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 174                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 175                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 176 #define CONFIG_SYS_DDR_MODE2            0x00000000
 177
 178 /*
 179  * Memory test
 180  */
 181 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 182 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 183
 184 /*
 185  * The reserved memory
 186  */
 187 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 188
 189 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 190 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 191
 192 /*
 193  * Initial RAM Base Address Setup
 194  */
 195 #define CONFIG_SYS_INIT_RAM_LOCK        1
 196 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 197 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 198 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 199         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 200
 201 /*
 202  * Local Bus Configuration & Clock Setup
 203  */
 204 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 205 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 206 #define CONFIG_SYS_LBC_LBCR             0x00040000
 207
 208 /*
 209  * FLASH on the Local Bus
 210  */
 211 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 212
 213 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 214 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is 8M */
 215
 216 /* Window base at flash base */
 217 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 218 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 219
 220 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 221                                 | BR_PS_16      /* 16 bit port */ \
 222                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 223                                 | BR_V)         /* valid */
 224 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 225                                 | OR_UPM_XAM \
 226                                 | OR_GPCM_CSNT \
 227                                 | OR_GPCM_ACS_DIV2 \
 228                                 | OR_GPCM_XACS \
 229                                 | OR_GPCM_SCY_15 \
 230                                 | OR_GPCM_TRLX_SET \
 231                                 | OR_GPCM_EHTR_SET)
 232
 233 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 234 /* 127 64KB sectors and 8 8KB top sectors per device */
 235 #define CONFIG_SYS_MAX_FLASH_SECT       135
 236
 237 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 238 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 239
 240 /*
 241  * NAND Flash on the Local Bus
 242  */
 243 #define CONFIG_SYS_NAND_BASE    0xE0600000              /* 0xE0600000 */
 244 #define CONFIG_SYS_NAND_WINDOW_SIZE     (32 * 1024)     /* 0x00008000 */
 245 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
 246                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 247                                 | BR_PS_8               /* 8 bit Port */ \
 248                                 | BR_MS_FCM             /* MSEL = FCM */ \
 249                                 | BR_V)                 /* valid */
 250 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 251                                 | OR_FCM_CSCT \
 252                                 | OR_FCM_CST \
 253                                 | OR_FCM_CHT \
 254                                 | OR_FCM_SCY_1 \
 255                                 | OR_FCM_TRLX \
 256                                 | OR_FCM_EHTR)
 257                                 /* 0xFFFF8396 */
 258
 259 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 260 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 261
 262 #ifdef CONFIG_VSC7385_ENET
 263 #define CONFIG_TSEC2
 264                                         /* VSC7385 Base address on CS2 */
 265 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 266 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024) /* 0x00020000 */
 267 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 268                                         | BR_PS_8       /* 8-bit port */ \
 269                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 270                                         | BR_V)         /* valid */
 271                                         /* 0xF0000801 */
 272 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
 273                                         | OR_GPCM_CSNT \
 274                                         | OR_GPCM_XACS \
 275                                         | OR_GPCM_SCY_15 \
 276                                         | OR_GPCM_SETA \
 277                                         | OR_GPCM_TRLX_SET \
 278                                         | OR_GPCM_EHTR_SET)
 279                                         /* 0xFFFE09FF */
 280 /* Access window base at VSC7385 base */
 281 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 282 /* Access window size 128K */
 283 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 284 /* The flash address and size of the VSC7385 firmware image */
 285 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 286 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 287 #endif
 288 /*
 289  * Serial Port
 290  */
 291 #define CONFIG_SYS_NS16550_SERIAL
 292 #define CONFIG_SYS_NS16550_REG_SIZE     1
 293 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 294
 295 #define CONFIG_SYS_BAUDRATE_TABLE  \
 296         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 297
 298 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 299 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 300
 301 /* I2C */
 302 #define CONFIG_SYS_I2C
 303 #define CONFIG_SYS_I2C_FSL
 304 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 305 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 306 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 307 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 308 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 309 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 310 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 311
 312 /*
 313  * SPI on header J8
 314  *
 315  * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
 316  * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
 317  */
 318 #ifdef CONFIG_MPC8XXX_SPI
 319 #define CONFIG_USE_SPIFLASH
 320 #endif
 321
 322 /*
 323  * Board info - revision and where boot from
 324  */
 325 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 326
 327 /*
 328  * Config on-board RTC
 329  */
 330 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 331 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 332
 333 /*
 334  * General PCI
 335  * Addresses are mapped 1-1.
 336  */
 337 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 338 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 339 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 340 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 341 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 342 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 343 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 344 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 345 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 346
 347 /* enable PCIE clock */
 348 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 349
 350 #define CONFIG_PCI_INDIRECT_BRIDGE
 351 #define CONFIG_PCIE
 352
 353 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 354 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 355
 356 /*
 357  * TSEC
 358  */
 359 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 360 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 361 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 362 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 363
 364 /*
 365  * TSEC ethernet configuration
 366  */
 367 #define CONFIG_TSEC1_NAME       "eTSEC0"
 368 #define CONFIG_TSEC2_NAME       "eTSEC1"
 369 #define TSEC1_PHY_ADDR          2
 370 #define TSEC2_PHY_ADDR          1
 371 #define TSEC1_PHYIDX            0
 372 #define TSEC2_PHYIDX            0
 373 #define TSEC1_FLAGS             TSEC_GIGABIT
 374 #define TSEC2_FLAGS             TSEC_GIGABIT
 375
 376 /* Options are: eTSEC[0-1] */
 377 #define CONFIG_ETHPRIME         "eTSEC0"
 378
 379 /*
 380  * Environment
 381  */
 382 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 383                                  CONFIG_SYS_MONITOR_LEN)
 384 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 385 #define CONFIG_ENV_SIZE         0x2000
 386 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 387 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 388
 389 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 390 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 391
 392 /*
 393  * BOOTP options
 394  */
 395 #define CONFIG_BOOTP_BOOTFILESIZE
 396
 397 /*
 398  * Command line configuration.
 399  */
 400
 401 /*
 402  * Miscellaneous configurable options
 403  */
 404 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 405
 406 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 407
 408 /* Boot Argument Buffer Size */
 409 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 410
 411 /*
 412  * For booting Linux, the board info and command line data
 413  * have to be in the first 256 MB of memory, since this is
 414  * the maximum mapped by the Linux kernel during initialization.
 415  */
 416 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 417 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 418
 419 /*
 420  * Core HID Setup
 421  */
 422 #define CONFIG_SYS_HID0_INIT    0x000000000
 423 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 424                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 425                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 426 #define CONFIG_SYS_HID2         HID2_HBE
 427
 428 /*
 429  * MMU Setup
 430  */
 431
 432 /* DDR: cache cacheable */
 433 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 434                                         BATL_MEMCOHERENCE)
 435 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
 436                                         BATU_VS | BATU_VP)
 437 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 438 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 439
 440 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 441 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 442                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 443 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
 444                                         BATU_VP)
 445 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 446 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 447
 448 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 449 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 450                                         BATL_MEMCOHERENCE)
 451 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
 452                                         BATU_VS | BATU_VP)
 453 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 454                                         BATL_CACHEINHIBIT | \
 455                                         BATL_GUARDEDSTORAGE)
 456 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 457
 458 /* Stack in dcache: cacheable, no memory coherence */
 459 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 460 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 461                                         BATU_VS | BATU_VP)
 462 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 463 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 464
 465 /*
 466  * Environment Configuration
 467  */
 468
 469 #define CONFIG_ENV_OVERWRITE
 470
 471 #if defined(CONFIG_TSEC_ENET)
 472 #define CONFIG_HAS_ETH0
 473 #define CONFIG_HAS_ETH1
 474 #endif
 475
 476 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 477
 478
 479 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 480         "netdev=eth0\0"                                                 \
 481         "consoledev=ttyS0\0"                                            \
 482         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 483                 "nfsroot=${serverip}:${rootpath}\0"                     \
 484         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 485         "addip=setenv bootargs ${bootargs} "                            \
 486                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 487                 ":${hostname}:${netdev}:off panic=1\0"                  \
 488         "addtty=setenv bootargs ${bootargs}"                            \
 489                 " console=${consoledev},${baudrate}\0"                  \
 490         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 491         "addmisc=setenv bootargs ${bootargs}\0"                         \
 492         "kernel_addr=FE080000\0"                                        \
 493         "fdt_addr=FE280000\0"                                           \
 494         "ramdisk_addr=FE290000\0"                                       \
 495         "u-boot=mpc8308rdb/u-boot.bin\0"                                \
 496         "kernel_addr_r=1000000\0"                                       \
 497         "fdt_addr_r=C00000\0"                                           \
 498         "hostname=mpc8308rdb\0"                                         \
 499         "bootfile=mpc8308rdb/uImage\0"                                  \
 500         "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0"                           \
 501         "rootpath=/opt/eldk-4.2/ppc_6xx\0"                              \
 502         "flash_self=run ramargs addip addtty addmtd addmisc;"           \
 503                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 504         "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
 505                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 506         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 507                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 508                 "run nfsargs addip addtty addmtd addmisc;"              \
 509                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 510         "bootcmd=run flash_self\0"                                      \
 511         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 512         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 513                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 514                 " +${filesize};cp.b ${fileaddr} "                       \
 515                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 516         "upd=run load update\0"                                         \
 517
 518 #endif  /* __CONFIG_H */