include/configs/M54455EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF54455 EVB board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M54455EVB_H
  15 #define _M54455EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M54455EVB        /* M54455EVB board */
  22
  23 #define CONFIG_DISPLAY_BOARDINFO
  24
  25 #define CONFIG_MCFUART
  26 #define CONFIG_SYS_UART_PORT            (0)
  27 #define CONFIG_BAUDRATE         115200
  28
  29 #undef CONFIG_WATCHDOG
  30
  31 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  32
  33 /*
  34  * BOOTP options
  35  */
  36 #define CONFIG_BOOTP_BOOTFILESIZE
  37 #define CONFIG_BOOTP_BOOTPATH
  38 #define CONFIG_BOOTP_GATEWAY
  39 #define CONFIG_BOOTP_HOSTNAME
  40
  41 /* Command line configuration */
  42 #define CONFIG_CMD_CACHE
  43 #define CONFIG_CMD_DATE
  44 #define CONFIG_CMD_DHCP
  45 #define CONFIG_CMD_EXT2
  46 #define CONFIG_CMD_FAT
  47 #define CONFIG_CMD_I2C
  48 #define CONFIG_CMD_IDE
  49 #define CONFIG_CMD_JFFS2
  50 #define CONFIG_CMD_MII
  51 #undef CONFIG_CMD_PCI
  52 #define CONFIG_CMD_PING
  53 #define CONFIG_CMD_REGINFO
  54 #define CONFIG_CMD_SPI
  55 #define CONFIG_CMD_SF
  56
  57
  58 /* Network configuration */
  59 #define CONFIG_MCFFEC
  60 #ifdef CONFIG_MCFFEC
  61 #       define CONFIG_MII               1
  62 #       define CONFIG_MII_INIT          1
  63 #       define CONFIG_SYS_DISCOVER_PHY
  64 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  65 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  66
  67 #       define CONFIG_SYS_FEC0_PINMUX   0
  68 #       define CONFIG_SYS_FEC1_PINMUX   0
  69 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  70 #       define CONFIG_SYS_FEC1_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  71 #       define MCFFEC_TOUT_LOOP 50000
  72 #       define CONFIG_HAS_ETH1
  73
  74 #       define CONFIG_BOOTDELAY 1       /* autoboot after 5 seconds */
  75 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
  76 #       define CONFIG_ETHPRIME          "FEC0"
  77 #       define CONFIG_IPADDR            192.162.1.2
  78 #       define CONFIG_NETMASK           255.255.255.0
  79 #       define CONFIG_SERVERIP          192.162.1.1
  80 #       define CONFIG_GATEWAYIP         192.162.1.1
  81
  82 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  83 #       ifndef CONFIG_SYS_DISCOVER_PHY
  84 #               define FECDUPLEX        FULL
  85 #               define FECSPEED         _100BASET
  86 #       else
  87 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  88 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  89 #               endif
  90 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  91 #endif
  92
  93 #define CONFIG_HOSTNAME         M54455EVB
  94 #ifdef CONFIG_SYS_STMICRO_BOOT
  95 /* ST Micro serial flash */
  96 #define CONFIG_SYS_LOAD_ADDR2           0x40010013
  97 #define CONFIG_EXTRA_ENV_SETTINGS               \
  98         "netdev=eth0\0"                         \
  99         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 100         "loadaddr=0x40010000\0"                 \
 101         "sbfhdr=sbfhdr.bin\0"                   \
 102         "uboot=u-boot.bin\0"                    \
 103         "load=tftp ${loadaddr} ${sbfhdr};"      \
 104         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
 105         "upd=run load; run prog\0"              \
 106         "prog=sf probe 0:1 1000000 3;"          \
 107         "sf erase 0 30000;"                     \
 108         "sf write ${loadaddr} 0 0x30000;"       \
 109         "save\0"                                \
 110         ""
 111 #else
 112 /* Atmel and Intel */
 113 #ifdef CONFIG_SYS_ATMEL_BOOT
 114 #       define CONFIG_SYS_UBOOT_END     0x0403FFFF
 115 #elif defined(CONFIG_SYS_INTEL_BOOT)
 116 #       define CONFIG_SYS_UBOOT_END     0x3FFFF
 117 #endif
 118 #define CONFIG_EXTRA_ENV_SETTINGS               \
 119         "netdev=eth0\0"                         \
 120         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 121         "loadaddr=0x40010000\0"                 \
 122         "uboot=u-boot.bin\0"                    \
 123         "load=tftp ${loadaddr} ${uboot}\0"      \
 124         "upd=run load; run prog\0"              \
 125         "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)     \
 126         " " __stringify(CONFIG_SYS_UBOOT_END) ";"               \
 127         "era " __stringify(CONFIG_SYS_FLASH_BASE) " "           \
 128         __stringify(CONFIG_SYS_UBOOT_END) ";"                   \
 129         "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)  \
 130         " ${filesize}; save\0"                  \
 131         ""
 132 #endif
 133
 134 /* ATA configuration */
 135 #define CONFIG_ISO_PARTITION
 136 #define CONFIG_DOS_PARTITION
 137 #define CONFIG_IDE_RESET        1
 138 #define CONFIG_IDE_PREINIT      1
 139 #define CONFIG_ATAPI
 140 #undef CONFIG_LBA48
 141
 142 #define CONFIG_SYS_IDE_MAXBUS           1
 143 #define CONFIG_SYS_IDE_MAXDEVICE        2
 144
 145 #define CONFIG_SYS_ATA_BASE_ADDR        0x90000000
 146 #define CONFIG_SYS_ATA_IDE0_OFFSET      0
 147
 148 #define CONFIG_SYS_ATA_DATA_OFFSET      0xA0    /* Offset for data I/O                            */
 149 #define CONFIG_SYS_ATA_REG_OFFSET       0xA0    /* Offset for normal register accesses */
 150 #define CONFIG_SYS_ATA_ALT_OFFSET       0xC0    /* Offset for alternate registers           */
 151 #define CONFIG_SYS_ATA_STRIDE           4       /* Interval between registers                 */
 152
 153 /* Realtime clock */
 154 #define CONFIG_MCFRTC
 155 #undef RTC_DEBUG
 156 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
 157
 158 /* Timer */
 159 #define CONFIG_MCFTMR
 160 #undef CONFIG_MCFPIT
 161
 162 /* I2c */
 163 #define CONFIG_SYS_I2C
 164 #define CONFIG_SYS_I2C_FSL
 165 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 166 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 167 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
 168 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 169
 170 /* DSPI and Serial Flash */
 171 #define CONFIG_CF_SPI
 172 #define CONFIG_CF_DSPI
 173 #define CONFIG_HARD_SPI
 174 #define CONFIG_SYS_SBFHDR_SIZE          0x13
 175 #ifdef CONFIG_CMD_SPI
 176
 177 #       define CONFIG_SYS_DSPI_CTAR0            (DSPI_CTAR_TRSZ(7) | \
 178                                          DSPI_CTAR_PCSSCK_1CLK | \
 179                                          DSPI_CTAR_PASC(0) | \
 180                                          DSPI_CTAR_PDT(0) | \
 181                                          DSPI_CTAR_CSSCK(0) | \
 182                                          DSPI_CTAR_ASC(0) | \
 183                                          DSPI_CTAR_DT(1))
 184 #endif
 185
 186 /* PCI */
 187 #ifdef CONFIG_CMD_PCI
 188 #define CONFIG_PCI              1
 189 #define CONFIG_PCI_PNP          1
 190 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
 191
 192 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  4
 193
 194 #define CONFIG_SYS_PCI_MEM_BUS          0xA0000000
 195 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
 196 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
 197
 198 #define CONFIG_SYS_PCI_IO_BUS           0xB1000000
 199 #define CONFIG_SYS_PCI_IO_PHYS          CONFIG_SYS_PCI_IO_BUS
 200 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000
 201
 202 #define CONFIG_SYS_PCI_CFG_BUS          0xB0000000
 203 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
 204 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
 205 #endif
 206
 207 /* FPGA - Spartan 2 */
 208 /* experiment
 209 #define CONFIG_FPGA
 210 #define CONFIG_FPGA_COUNT       1
 211 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 212 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 213 */
 214
 215 /* Input, PCI, Flexbus, and VCO */
 216 #define CONFIG_EXTRA_CLOCK
 217
 218 #define CONFIG_PRAM             2048    /* 2048 KB */
 219
 220 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 221
 222 #if defined(CONFIG_CMD_KGDB)
 223 #define CONFIG_SYS_CBSIZE                       1024    /* Console I/O Buffer Size */
 224 #else
 225 #define CONFIG_SYS_CBSIZE                       256     /* Console I/O Buffer Size */
 226 #endif
 227 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 228 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 229 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 230
 231 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 232
 233 #define CONFIG_SYS_MBAR         0xFC000000
 234
 235 /*
 236  * Low Level Configuration Settings
 237  * (address mappings, register initial values, etc.)
 238  * You should know what you are doing if you make changes here.
 239  */
 240
 241 /*-----------------------------------------------------------------------
 242  * Definitions for initial stack pointer and data area (in DPRAM)
 243  */
 244 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 245 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000  /* Size of used area in internal SRAM */
 246 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 247 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 248 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 249 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 250
 251 /*-----------------------------------------------------------------------
 252  * Start addresses for the final memory configuration
 253  * (Set up by the startup code)
 254  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 255  */
 256 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 257 #define CONFIG_SYS_SDRAM_BASE1          0x48000000
 258 #define CONFIG_SYS_SDRAM_SIZE           256     /* SDRAM size in MB */
 259 #define CONFIG_SYS_SDRAM_CFG1           0x65311610
 260 #define CONFIG_SYS_SDRAM_CFG2           0x59670000
 261 #define CONFIG_SYS_SDRAM_CTRL           0xEA0B2000
 262 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
 263 #define CONFIG_SYS_SDRAM_MODE           0x00010033
 264 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0xAA
 265
 266 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 267 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 268
 269 #ifdef CONFIG_CF_SBF
 270 #       define CONFIG_SERIAL_BOOT
 271 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 272 #else
 273 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 274 #endif
 275 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 276 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 277
 278 /* Reserve 256 kB for malloc() */
 279 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 280
 281 /*
 282  * For booting Linux, the board info and command line data
 283  * have to be in the first 8 MB of memory, since this is
 284  * the maximum mapped by the Linux kernel during initialization ??
 285  */
 286 /* Initial Memory map for Linux */
 287 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 288
 289 /*
 290  * Configuration for environment
 291  * Environment is not embedded in u-boot. First time runing may have env
 292  * crc error warning if there is no correct environment on the flash.
 293  */
 294 #ifdef CONFIG_CF_SBF
 295 #       define CONFIG_ENV_IS_IN_SPI_FLASH
 296 #       define CONFIG_ENV_SPI_CS                1
 297 #else
 298 #       define CONFIG_ENV_IS_IN_FLASH   1
 299 #endif
 300 #undef CONFIG_ENV_OVERWRITE
 301
 302 /*-----------------------------------------------------------------------
 303  * FLASH organization
 304  */
 305 #ifdef CONFIG_SYS_STMICRO_BOOT
 306 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 307 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS1_BASE
 308 #       define CONFIG_ENV_OFFSET                0x30000
 309 #       define CONFIG_ENV_SIZE          0x2000
 310 #       define CONFIG_ENV_SECT_SIZE     0x10000
 311 #endif
 312 #ifdef CONFIG_SYS_ATMEL_BOOT
 313 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 314 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 315 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
 316 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 317 #       define CONFIG_ENV_SIZE          0x2000
 318 #       define CONFIG_ENV_SECT_SIZE     0x10000
 319 #endif
 320 #ifdef CONFIG_SYS_INTEL_BOOT
 321 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 322 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 323 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
 324 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 325 #       define CONFIG_ENV_SIZE          0x2000
 326 #       define CONFIG_ENV_SECT_SIZE     0x20000
 327 #endif
 328
 329 #define CONFIG_SYS_FLASH_CFI
 330 #ifdef CONFIG_SYS_FLASH_CFI
 331
 332 #       define CONFIG_FLASH_CFI_DRIVER  1
 333 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 334 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 335 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_8BIT
 336 #       define CONFIG_SYS_MAX_FLASH_BANKS       2       /* max number of memory banks */
 337 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 338 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 339 #       define CONFIG_SYS_FLASH_CHECKSUM
 340 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
 341 #       define CONFIG_FLASH_CFI_LEGACY
 342
 343 #ifdef CONFIG_FLASH_CFI_LEGACY
 344 #       define CONFIG_SYS_ATMEL_REGION          4
 345 #       define CONFIG_SYS_ATMEL_TOTALSECT       11
 346 #       define CONFIG_SYS_ATMEL_SECT            {1, 2, 1, 7}
 347 #       define CONFIG_SYS_ATMEL_SECTSZ          {0x4000, 0x2000, 0x8000, 0x10000}
 348 #endif
 349 #endif
 350
 351 /*
 352  * This is setting for JFFS2 support in u-boot.
 353  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 354  */
 355 #ifdef CONFIG_CMD_JFFS2
 356 #ifdef CF_STMICRO_BOOT
 357 #       define CONFIG_JFFS2_DEV         "nor1"
 358 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 359 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
 360 #endif
 361 #ifdef CONFIG_SYS_ATMEL_BOOT
 362 #       define CONFIG_JFFS2_DEV         "nor1"
 363 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 364 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
 365 #endif
 366 #ifdef CONFIG_SYS_INTEL_BOOT
 367 #       define CONFIG_JFFS2_DEV         "nor0"
 368 #       define CONFIG_JFFS2_PART_SIZE   (0x01000000 - 0x500000)
 369 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
 370 #endif
 371 #endif
 372
 373 /*-----------------------------------------------------------------------
 374  * Cache Configuration
 375  */
 376 #define CONFIG_SYS_CACHELINE_SIZE               16
 377
 378 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 379                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 380 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 381                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 382 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 383 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 384 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 385                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 386                                          CF_ACR_EN | CF_ACR_SM_ALL)
 387 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 388                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 389 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 390                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 391                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 392
 393 /*-----------------------------------------------------------------------
 394  * Memory bank definitions
 395  */
 396 /*
 397  * CS0 - NOR Flash 1, 2, 4, or 8MB
 398  * CS1 - CompactFlash and registers
 399  * CS2 - CPLD
 400  * CS3 - FPGA
 401  * CS4 - Available
 402  * CS5 - Available
 403  */
 404
 405 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
 406  /* Atmel Flash */
 407 #define CONFIG_SYS_CS0_BASE             0x04000000
 408 #define CONFIG_SYS_CS0_MASK             0x00070001
 409 #define CONFIG_SYS_CS0_CTRL             0x00001140
 410 /* Intel Flash */
 411 #define CONFIG_SYS_CS1_BASE             0x00000000
 412 #define CONFIG_SYS_CS1_MASK             0x01FF0001
 413 #define CONFIG_SYS_CS1_CTRL             0x00000D60
 414
 415 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS0_BASE
 416 #else
 417 /* Intel Flash */
 418 #define CONFIG_SYS_CS0_BASE             0x00000000
 419 #define CONFIG_SYS_CS0_MASK             0x01FF0001
 420 #define CONFIG_SYS_CS0_CTRL             0x00000D60
 421  /* Atmel Flash */
 422 #define CONFIG_SYS_CS1_BASE             0x04000000
 423 #define CONFIG_SYS_CS1_MASK             0x00070001
 424 #define CONFIG_SYS_CS1_CTRL             0x00001140
 425
 426 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS1_BASE
 427 #endif
 428
 429 /* CPLD */
 430 #define CONFIG_SYS_CS2_BASE             0x08000000
 431 #define CONFIG_SYS_CS2_MASK             0x00070001
 432 #define CONFIG_SYS_CS2_CTRL             0x003f1140
 433
 434 /* FPGA */
 435 #define CONFIG_SYS_CS3_BASE             0x09000000
 436 #define CONFIG_SYS_CS3_MASK             0x00070001
 437 #define CONFIG_SYS_CS3_CTRL             0x00000020
 438
 439 #endif                          /* _M54455EVB_H */