1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF54451 EVB board.
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
20 #define CONFIG_M54451EVB /* M54451EVB board */
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
25 #define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*)
27 #undef CONFIG_WATCHDOG
29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
34 #define CONFIG_BOOTP_BOOTFILESIZE
36 /* Network configuration */
38 # define CONFIG_MII_INIT 1
39 # define CONFIG_SYS_DISCOVER_PHY
40 # define CONFIG_SYS_RX_ETH_BUFFER 8
41 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
42 # define CONFIG_ETHPRIME "FEC0"
43 # define CONFIG_IPADDR 192.162.1.2
44 # define CONFIG_NETMASK 255.255.255.0
45 # define CONFIG_SERVERIP 192.162.1.1
46 # define CONFIG_GATEWAYIP 192.162.1.1
48 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
49 # ifndef CONFIG_SYS_DISCOVER_PHY
50 # define FECDUPLEX FULL
51 # define FECSPEED _100BASET
53 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
54 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
56 # endif /* CONFIG_SYS_DISCOVER_PHY */
59 #define CONFIG_HOSTNAME "M54451EVB"
60 #ifdef CONFIG_SYS_STMICRO_BOOT
61 /* ST Micro serial flash */
62 #define CONFIG_SYS_LOAD_ADDR2 0x40010007
63 #define CONFIG_EXTRA_ENV_SETTINGS \
65 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
66 "loadaddr=0x40010000\0" \
67 "sbfhdr=sbfhdr.bin\0" \
68 "uboot=u-boot.bin\0" \
69 "load=tftp ${loadaddr} ${sbfhdr};" \
70 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
71 "upd=run load; run prog\0" \
72 "prog=sf probe 0:1 1000000 3;" \
74 "sf write ${loadaddr} 0 30000;" \
78 #define CONFIG_SYS_UBOOT_END 0x3FFFF
79 #define CONFIG_EXTRA_ENV_SETTINGS \
81 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
82 "loadaddr=40010000\0" \
83 "u-boot=u-boot.bin\0" \
84 "load=tftp ${loadaddr) ${u-boot}\0" \
85 "upd=run load; run prog\0" \
86 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
87 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
88 "cp.b ${loadaddr} 0 ${filesize};" \
96 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
103 #define CONFIG_SYS_I2C
104 #define CONFIG_SYS_I2C_FSL
105 #define CONFIG_SYS_FSL_I2C_SPEED 80000
106 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
107 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
108 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
110 /* DSPI and Serial Flash */
111 #define CONFIG_CF_DSPI
112 #define CONFIG_SERIAL_FLASH
113 #define CONFIG_SYS_SBFHDR_SIZE 0x7
115 /* Input, PCI, Flexbus, and VCO */
116 #define CONFIG_EXTRA_CLOCK
118 #define CONFIG_PRAM 2048 /* 2048 KB */
120 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
122 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
124 #define CONFIG_SYS_MBAR 0xFC000000
127 * Low Level Configuration Settings
128 * (address mappings, register initial values, etc.)
129 * You should know what you are doing if you make changes here.
132 /*-----------------------------------------------------------------------
133 * Definitions for initial stack pointer and data area (in DPRAM)
135 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
136 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
137 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
138 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
139 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
140 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
142 /*-----------------------------------------------------------------------
143 * Start addresses for the final memory configuration
144 * (Set up by the startup code)
145 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
147 #define CONFIG_SYS_SDRAM_BASE 0x40000000
148 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
149 #define CONFIG_SYS_SDRAM_CFG1 0x33633F30
150 #define CONFIG_SYS_SDRAM_CFG2 0x57670000
151 #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
152 #define CONFIG_SYS_SDRAM_EMOD 0x80810000
153 #define CONFIG_SYS_SDRAM_MODE 0x008D0000
154 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
156 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
157 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
160 # define CONFIG_SERIAL_BOOT
161 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
163 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
165 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
166 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
168 /* Reserve 256 kB for malloc() */
169 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
171 * For booting Linux, the board info and command line data
172 * have to be in the first 8 MB of memory, since this is
173 * the maximum mapped by the Linux kernel during initialization ??
175 /* Initial Memory map for Linux */
176 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
178 /* Configuration for environment
179 * Environment is not embedded in u-boot. First time runing may have env
180 * crc error warning if there is no correct environment on the flash.
182 #undef CONFIG_ENV_OVERWRITE
184 /* FLASH organization */
185 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
187 #ifdef CONFIG_SYS_FLASH_CFI
189 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
190 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
191 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
192 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
193 # define CONFIG_SYS_FLASH_CHECKSUM
194 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
199 * This is setting for JFFS2 support in u-boot.
200 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
202 #ifdef CONFIG_CMD_JFFS2
203 # define CONFIG_JFFS2_DEV "nor0"
204 # define CONFIG_JFFS2_PART_SIZE 0x01000000
205 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
208 /* Cache Configuration */
209 #define CONFIG_SYS_CACHELINE_SIZE 16
211 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
212 CONFIG_SYS_INIT_RAM_SIZE - 8)
213 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
214 CONFIG_SYS_INIT_RAM_SIZE - 4)
215 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
216 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
217 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
218 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
219 CF_ACR_EN | CF_ACR_SM_ALL)
220 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
221 CF_CACR_ICINVA | CF_CACR_EUSP)
222 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
223 CF_CACR_DEC | CF_CACR_DDCM_P | \
224 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
226 /*-----------------------------------------------------------------------
227 * Memory bank definitions
230 * CS0 - NOR Flash 16MB
239 #define CONFIG_SYS_CS0_BASE 0x00000000
240 #define CONFIG_SYS_CS0_MASK 0x00FF0001
241 #define CONFIG_SYS_CS0_CTRL 0x00004D80
243 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
245 #endif /* _M54451EVB_H */