include/configs/M54451EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF54451 EVB board.
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M54451EVB_H
  15 #define _M54451EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M54451EVB        /* M54451EVB board */
  22
  23 #define CONFIG_DISPLAY_BOARDINFO
  24
  25 #define CONFIG_MCFUART
  26 #define CONFIG_SYS_UART_PORT            (0)
  27 #define CONFIG_BAUDRATE         115200
  28
  29 #undef CONFIG_WATCHDOG
  30
  31 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  32
  33 /*
  34  * BOOTP options
  35  */
  36 #define CONFIG_BOOTP_BOOTFILESIZE
  37 #define CONFIG_BOOTP_BOOTPATH
  38 #define CONFIG_BOOTP_GATEWAY
  39 #define CONFIG_BOOTP_HOSTNAME
  40
  41 /* Command line configuration */
  42 #define CONFIG_CMD_CACHE
  43 #define CONFIG_CMD_DATE
  44 #define CONFIG_CMD_DHCP
  45 #define CONFIG_CMD_I2C
  46 #undef CONFIG_CMD_JFFS2
  47 #define CONFIG_CMD_MII
  48 #define CONFIG_CMD_PING
  49 #define CONFIG_CMD_REGINFO
  50 #define CONFIG_CMD_SPI
  51 #define CONFIG_CMD_SF
  52
  53
  54 /* Network configuration */
  55 #define CONFIG_MCFFEC
  56 #ifdef CONFIG_MCFFEC
  57 #       define CONFIG_MII               1
  58 #       define CONFIG_MII_INIT          1
  59 #       define CONFIG_SYS_DISCOVER_PHY
  60 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  61 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  62
  63 #       define CONFIG_SYS_FEC0_PINMUX   0
  64 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  65 #       define MCFFEC_TOUT_LOOP 50000
  66
  67 #       define CONFIG_BOOTDELAY 1       /* autoboot after 5 seconds */
  68 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
  69 #       define CONFIG_ETHPRIME          "FEC0"
  70 #       define CONFIG_IPADDR            192.162.1.2
  71 #       define CONFIG_NETMASK           255.255.255.0
  72 #       define CONFIG_SERVERIP          192.162.1.1
  73 #       define CONFIG_GATEWAYIP         192.162.1.1
  74
  75 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  76 #       ifndef CONFIG_SYS_DISCOVER_PHY
  77 #               define FECDUPLEX        FULL
  78 #               define FECSPEED         _100BASET
  79 #       else
  80 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  81 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  82 #               endif
  83 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  84 #endif
  85
  86 #define CONFIG_HOSTNAME         M54451EVB
  87 #ifdef CONFIG_SYS_STMICRO_BOOT
  88 /* ST Micro serial flash */
  89 #define CONFIG_SYS_LOAD_ADDR2           0x40010007
  90 #define CONFIG_EXTRA_ENV_SETTINGS               \
  91         "netdev=eth0\0"                         \
  92         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  93         "loadaddr=0x40010000\0"                 \
  94         "sbfhdr=sbfhdr.bin\0"                   \
  95         "uboot=u-boot.bin\0"                    \
  96         "load=tftp ${loadaddr} ${sbfhdr};"      \
  97         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
  98         "upd=run load; run prog\0"              \
  99         "prog=sf probe 0:1 1000000 3;"          \
 100         "sf erase 0 30000;"                     \
 101         "sf write ${loadaddr} 0 30000;"         \
 102         "save\0"                                \
 103         ""
 104 #else
 105 #define CONFIG_SYS_UBOOT_END    0x3FFFF
 106 #define CONFIG_EXTRA_ENV_SETTINGS               \
 107         "netdev=eth0\0"                         \
 108         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 109         "loadaddr=40010000\0"                   \
 110         "u-boot=u-boot.bin\0"                   \
 111         "load=tftp ${loadaddr) ${u-boot}\0"     \
 112         "upd=run load; run prog\0"              \
 113         "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END)    \
 114         "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;"       \
 115         "cp.b ${loadaddr} 0 ${filesize};"       \
 116         "save\0"                                \
 117         ""
 118 #endif
 119
 120 /* Realtime clock */
 121 #define CONFIG_MCFRTC
 122 #undef RTC_DEBUG
 123 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
 124
 125 /* Timer */
 126 #define CONFIG_MCFTMR
 127 #undef CONFIG_MCFPIT
 128
 129 /* I2c */
 130 #define CONFIG_SYS_I2C
 131 #define CONFIG_SYS_I2C_FSL
 132 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 133 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 134 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
 135 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 136
 137 /* DSPI and Serial Flash */
 138 #define CONFIG_CF_SPI
 139 #define CONFIG_CF_DSPI
 140 #define CONFIG_SERIAL_FLASH
 141 #define CONFIG_HARD_SPI
 142 #define CONFIG_SYS_SBFHDR_SIZE          0x7
 143 #ifdef CONFIG_CMD_SPI
 144
 145 #       define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
 146                                          DSPI_CTAR_PCSSCK_1CLK | \
 147                                          DSPI_CTAR_PASC(0) | \
 148                                          DSPI_CTAR_PDT(0) | \
 149                                          DSPI_CTAR_CSSCK(0) | \
 150                                          DSPI_CTAR_ASC(0) | \
 151                                          DSPI_CTAR_DT(1))
 152 #       define CONFIG_SYS_DSPI_CTAR1    (CONFIG_SYS_DSPI_CTAR0)
 153 #       define CONFIG_SYS_DSPI_CTAR2    (CONFIG_SYS_DSPI_CTAR0)
 154 #endif
 155
 156 /* Input, PCI, Flexbus, and VCO */
 157 #define CONFIG_EXTRA_CLOCK
 158
 159 #define CONFIG_PRAM                     2048    /* 2048 KB */
 160
 161 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 162
 163 #if defined(CONFIG_CMD_KGDB)
 164 #define CONFIG_SYS_CBSIZE                       1024    /* Console I/O Buffer Size */
 165 #else
 166 #define CONFIG_SYS_CBSIZE                       256     /* Console I/O Buffer Size */
 167 #endif
 168 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 169 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 170 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 171
 172 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 173
 174 #define CONFIG_SYS_MBAR                 0xFC000000
 175
 176 /*
 177  * Low Level Configuration Settings
 178  * (address mappings, register initial values, etc.)
 179  * You should know what you are doing if you make changes here.
 180  */
 181
 182 /*-----------------------------------------------------------------------
 183  * Definitions for initial stack pointer and data area (in DPRAM)
 184  */
 185 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 186 #define CONFIG_SYS_INIT_RAM_SIZE        0x8000  /* Size of used area in internal SRAM */
 187 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 188 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 189 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 190 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 191
 192 /*-----------------------------------------------------------------------
 193  * Start addresses for the final memory configuration
 194  * (Set up by the startup code)
 195  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 196  */
 197 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 198 #define CONFIG_SYS_SDRAM_SIZE           128     /* SDRAM size in MB */
 199 #define CONFIG_SYS_SDRAM_CFG1           0x33633F30
 200 #define CONFIG_SYS_SDRAM_CFG2           0x57670000
 201 #define CONFIG_SYS_SDRAM_CTRL           0xE20D2C00
 202 #define CONFIG_SYS_SDRAM_EMOD           0x80810000
 203 #define CONFIG_SYS_SDRAM_MODE           0x008D0000
 204 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0x44
 205
 206 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 207 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 208
 209 #ifdef CONFIG_CF_SBF
 210 #       define CONFIG_SERIAL_BOOT
 211 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 212 #else
 213 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 214 #endif
 215 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 216 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 217
 218 /* Reserve 256 kB for malloc() */
 219 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 220 /*
 221  * For booting Linux, the board info and command line data
 222  * have to be in the first 8 MB of memory, since this is
 223  * the maximum mapped by the Linux kernel during initialization ??
 224  */
 225 /* Initial Memory map for Linux */
 226 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 227
 228 /* Configuration for environment
 229  * Environment is not embedded in u-boot. First time runing may have env
 230  * crc error warning if there is no correct environment on the flash.
 231  */
 232 #if defined(CONFIG_SYS_STMICRO_BOOT)
 233 #       define CONFIG_ENV_IS_IN_SPI_FLASH       1
 234 #       define CONFIG_ENV_SPI_CS                1
 235 #       define CONFIG_ENV_OFFSET                0x20000
 236 #       define CONFIG_ENV_SIZE          0x2000
 237 #       define CONFIG_ENV_SECT_SIZE     0x10000
 238 #else
 239 #       define CONFIG_ENV_IS_IN_FLASH   1
 240 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 241 #       define CONFIG_ENV_SIZE          0x2000
 242 #       define CONFIG_ENV_SECT_SIZE     0x20000
 243 #endif
 244 #undef CONFIG_ENV_OVERWRITE
 245
 246 /* FLASH organization */
 247 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 248
 249 #define CONFIG_SYS_FLASH_CFI
 250 #ifdef CONFIG_SYS_FLASH_CFI
 251
 252 #       define CONFIG_FLASH_CFI_DRIVER  1
 253 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 254 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 255 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 256 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 257 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 258 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 259 #       define CONFIG_SYS_FLASH_CHECKSUM
 260 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE }
 261
 262 #endif
 263
 264 /*
 265  * This is setting for JFFS2 support in u-boot.
 266  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 267  */
 268 #ifdef CONFIG_CMD_JFFS2
 269 #       define CONFIG_JFFS2_DEV         "nor0"
 270 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 271 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
 272 #endif
 273
 274 /* Cache Configuration */
 275 #define CONFIG_SYS_CACHELINE_SIZE               16
 276
 277 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 278                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 279 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 280                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 281 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 282 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 283 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 284                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 285                                          CF_ACR_EN | CF_ACR_SM_ALL)
 286 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 287                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 288 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 289                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 290                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 291
 292 /*-----------------------------------------------------------------------
 293  * Memory bank definitions
 294  */
 295 /*
 296  * CS0 - NOR Flash 16MB
 297  * CS1 - Available
 298  * CS2 - Available
 299  * CS3 - Available
 300  * CS4 - Available
 301  * CS5 - Available
 302  */
 303
 304  /* Flash */
 305 #define CONFIG_SYS_CS0_BASE             0x00000000
 306 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 307 #define CONFIG_SYS_CS0_CTRL             0x00004D80
 308
 309 #define CONFIG_SYS_SPANSION_BASE        CONFIG_SYS_CS0_BASE
 310
 311 #endif                          /* _M54451EVB_H */