include/configs/M5373EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Freescale MCF5373 FireEngine board.
   4  *
   5  * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _M5373EVB_H
  14 #define _M5373EVB_H
  15
  16 #include <linux/stringify.h>
  17
  18 /*
  19  * High Level Configuration Options
  20  * (easy to change)
  21  */
  22
  23 #define CFG_SYS_UART_PORT               (0)
  24
  25 /* I2C */
  26
  27 #define CFG_EXTRA_ENV_SETTINGS                                  \
  28         "netdev=eth0\0"                 \
  29         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0"      \
  30         "u-boot=u-boot.bin\0"   \
  31         "load=tftp ${loadaddr) ${u-boot}\0"     \
  32         "upd=run load; run prog\0"      \
  33         "prog=prot off 0 3ffff;"        \
  34         "era 0 3ffff;"  \
  35         "cp.b ${loadaddr} 0 ${filesize};"       \
  36         "save\0"        \
  37         ""
  38
  39 #define CFG_PRAM                512     /* 512 KB */
  40
  41 #define CFG_SYS_CLK                     80000000
  42 #define CFG_SYS_CPU_CLK         CFG_SYS_CLK * 3
  43
  44 #define CFG_SYS_MBAR            0xFC000000
  45
  46 #define CFG_SYS_LATCH_ADDR              (CFG_SYS_CS1_BASE + 0x80000)
  47
  48 /*
  49  * Low Level Configuration Settings
  50  * (address mappings, register initial values, etc.)
  51  * You should know what you are doing if you make changes here.
  52  */
  53 /*-----------------------------------------------------------------------
  54  * Definitions for initial stack pointer and data area (in DPRAM)
  55  */
  56 #define CFG_SYS_INIT_RAM_ADDR   0x80000000
  57 #define CFG_SYS_INIT_RAM_SIZE   0x8000  /* Size of used area in internal SRAM */
  58 #define CFG_SYS_INIT_RAM_CTRL   0x221
  59
  60 /*-----------------------------------------------------------------------
  61  * Start addresses for the final memory configuration
  62  * (Set up by the startup code)
  63  * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  64  */
  65 #define CFG_SYS_SDRAM_BASE              0x40000000
  66 #define CFG_SYS_SDRAM_SIZE              32      /* SDRAM size in MB */
  67 #define CFG_SYS_SDRAM_CFG1              0x53722730
  68 #define CFG_SYS_SDRAM_CFG2              0x56670000
  69 #define CFG_SYS_SDRAM_CTRL              0xE1092000
  70 #define CFG_SYS_SDRAM_EMOD              0x40010000
  71 #define CFG_SYS_SDRAM_MODE              0x018D0000
  72
  73 /*
  74  * For booting Linux, the board info and command line data
  75  * have to be in the first 8 MB of memory, since this is
  76  * the maximum mapped by the Linux kernel during initialization ??
  77  */
  78 #define CFG_SYS_BOOTMAPSZ               (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
  79
  80 /*-----------------------------------------------------------------------
  81  * FLASH organization
  82  */
  83 #ifdef CONFIG_SYS_FLASH_CFI
  84 #       define CFG_SYS_FLASH_SIZE               0x800000        /* Max size that the board might have */
  85 #endif
  86
  87 #       define CFG_SYS_NAND_BASE                CFG_SYS_CS2_BASE
  88 #       define CFG_SYS_NAND_BASE_LIST   { CFG_SYS_NAND_BASE }
  89 #       define NAND_ALLOW_ERASE_ALL     1
  90
  91 #define CFG_SYS_FLASH_BASE              CFG_SYS_CS0_BASE
  92
  93 /* Configuration for environment
  94  * Environment is embedded in u-boot in the second sector of the flash
  95  */
  96
  97 #define LDS_BOARD_TEXT \
  98         . = DEFINED(env_offset) ? env_offset : .; \
  99         env/embedded.o(.text*);
 100
 101 /*-----------------------------------------------------------------------
 102  * Cache Configuration
 103  */
 104
 105 #define ICACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
 106                                          CFG_SYS_INIT_RAM_SIZE - 8)
 107 #define DCACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
 108                                          CFG_SYS_INIT_RAM_SIZE - 4)
 109 #define CFG_SYS_ICACHE_INV              (CF_CACR_CINVA)
 110 #define CFG_SYS_CACHE_ACR0              (CFG_SYS_SDRAM_BASE | \
 111                                          CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 112                                          CF_ACR_EN | CF_ACR_SM_ALL)
 113 #define CFG_SYS_CACHE_ICACR             (CF_CACR_EC | CF_CACR_CINVA | \
 114                                          CF_CACR_DCM_P)
 115
 116 /*-----------------------------------------------------------------------
 117  * Chipselect bank definitions
 118  */
 119 /*
 120  * CS0 - NOR Flash 1, 2, 4, or 8MB
 121  * CS1 - CompactFlash and registers
 122  * CS2 - NAND Flash 16, 32, or 64MB
 123  * CS3 - Available
 124  * CS4 - Available
 125  * CS5 - Available
 126  */
 127 #define CFG_SYS_CS0_BASE                0
 128 #define CFG_SYS_CS0_MASK                0x007f0001
 129 #define CFG_SYS_CS0_CTRL                0x00001fa0
 130
 131 #define CFG_SYS_CS1_BASE                0x10000000
 132 #define CFG_SYS_CS1_MASK                0x001f0001
 133 #define CFG_SYS_CS1_CTRL                0x002A3780
 134
 135 #define CFG_SYS_CS2_BASE                0x20000000
 136 #define CFG_SYS_CS2_MASK                (16 << 20)
 137 #define CFG_SYS_CS2_CTRL                0x00001f60
 138
 139 #define CFG_MCFTMR
 140
 141 #endif                          /* _M5373EVB_H */