include/configs/M5373EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Freescale MCF5373 FireEngine board.
   4  *
   5  * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _M5373EVB_H
  14 #define _M5373EVB_H
  15
  16 #include <linux/stringify.h>
  17
  18 /*
  19  * High Level Configuration Options
  20  * (easy to change)
  21  */
  22
  23 #define CONFIG_SYS_UART_PORT            (0)
  24
  25 #define CONFIG_WATCHDOG_TIMEOUT 3360    /* timeout in ms, max is 3.36 sec */
  26
  27 /* I2C */
  28
  29 #ifdef CONFIG_MCFFEC
  30 #       define CONFIG_IPADDR    192.162.1.2
  31 #       define CONFIG_NETMASK   255.255.255.0
  32 #       define CONFIG_SERVERIP  192.162.1.1
  33 #       define CONFIG_GATEWAYIP 192.162.1.1
  34 #endif                          /* FEC_ENET */
  35
  36 #define CONFIG_HOSTNAME         "M5373EVB"
  37 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  38         "netdev=eth0\0"                 \
  39         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0"      \
  40         "u-boot=u-boot.bin\0"   \
  41         "load=tftp ${loadaddr) ${u-boot}\0"     \
  42         "upd=run load; run prog\0"      \
  43         "prog=prot off 0 3ffff;"        \
  44         "era 0 3ffff;"  \
  45         "cp.b ${loadaddr} 0 ${filesize};"       \
  46         "save\0"        \
  47         ""
  48
  49 #define CONFIG_PRAM             512     /* 512 KB */
  50
  51 #define CONFIG_SYS_CLK                  80000000
  52 #define CONFIG_SYS_CPU_CLK              CONFIG_SYS_CLK * 3
  53
  54 #define CONFIG_SYS_MBAR         0xFC000000
  55
  56 #define CONFIG_SYS_LATCH_ADDR           (CONFIG_SYS_CS1_BASE + 0x80000)
  57
  58 /*
  59  * Low Level Configuration Settings
  60  * (address mappings, register initial values, etc.)
  61  * You should know what you are doing if you make changes here.
  62  */
  63 /*-----------------------------------------------------------------------
  64  * Definitions for initial stack pointer and data area (in DPRAM)
  65  */
  66 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
  67 #define CONFIG_SYS_INIT_RAM_SIZE        0x8000  /* Size of used area in internal SRAM */
  68 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
  69
  70 /*-----------------------------------------------------------------------
  71  * Start addresses for the final memory configuration
  72  * (Set up by the startup code)
  73  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  74  */
  75 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  76 #define CONFIG_SYS_SDRAM_SIZE           32      /* SDRAM size in MB */
  77 #define CONFIG_SYS_SDRAM_CFG1           0x53722730
  78 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
  79 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
  80 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
  81 #define CONFIG_SYS_SDRAM_MODE           0x018D0000
  82
  83 /*
  84  * For booting Linux, the board info and command line data
  85  * have to be in the first 8 MB of memory, since this is
  86  * the maximum mapped by the Linux kernel during initialization ??
  87  */
  88 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  89
  90 /*-----------------------------------------------------------------------
  91  * FLASH organization
  92  */
  93 #ifdef CONFIG_SYS_FLASH_CFI
  94 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
  95 #endif
  96
  97 #       define CONFIG_SYS_NAND_BASE             CONFIG_SYS_CS2_BASE
  98 #       define CONFIG_SYS_NAND_BASE_LIST        { CONFIG_SYS_NAND_BASE }
  99 #       define NAND_ALLOW_ERASE_ALL     1
 100
 101 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 102
 103 /* Configuration for environment
 104  * Environment is embedded in u-boot in the second sector of the flash
 105  */
 106
 107 #define LDS_BOARD_TEXT \
 108         . = DEFINED(env_offset) ? env_offset : .; \
 109         env/embedded.o(.text*);
 110
 111 /*-----------------------------------------------------------------------
 112  * Cache Configuration
 113  */
 114
 115 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 116                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 117 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 118                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 119 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 120 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 121                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 122                                          CF_ACR_EN | CF_ACR_SM_ALL)
 123 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 124                                          CF_CACR_DCM_P)
 125
 126 /*-----------------------------------------------------------------------
 127  * Chipselect bank definitions
 128  */
 129 /*
 130  * CS0 - NOR Flash 1, 2, 4, or 8MB
 131  * CS1 - CompactFlash and registers
 132  * CS2 - NAND Flash 16, 32, or 64MB
 133  * CS3 - Available
 134  * CS4 - Available
 135  * CS5 - Available
 136  */
 137 #define CONFIG_SYS_CS0_BASE             0
 138 #define CONFIG_SYS_CS0_MASK             0x007f0001
 139 #define CONFIG_SYS_CS0_CTRL             0x00001fa0
 140
 141 #define CONFIG_SYS_CS1_BASE             0x10000000
 142 #define CONFIG_SYS_CS1_MASK             0x001f0001
 143 #define CONFIG_SYS_CS1_CTRL             0x002A3780
 144
 145 #define CONFIG_SYS_CS2_BASE             0x20000000
 146 #define CONFIG_SYS_CS2_MASK             (16 << 20)
 147 #define CONFIG_SYS_CS2_CTRL             0x00001f60
 148
 149 #endif                          /* _M5373EVB_H */