1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5373 FireEngine board.
5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
16 #include <linux/stringify.h>
19 * High Level Configuration Options
23 #define CFG_SYS_UART_PORT (0)
28 # define CONFIG_IPADDR 192.162.1.2
29 # define CONFIG_NETMASK 255.255.255.0
30 # define CONFIG_SERVERIP 192.162.1.1
31 # define CONFIG_GATEWAYIP 192.162.1.1
34 #define CONFIG_HOSTNAME "M5373EVB"
35 #define CONFIG_EXTRA_ENV_SETTINGS \
37 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
38 "u-boot=u-boot.bin\0" \
39 "load=tftp ${loadaddr) ${u-boot}\0" \
40 "upd=run load; run prog\0" \
41 "prog=prot off 0 3ffff;" \
43 "cp.b ${loadaddr} 0 ${filesize};" \
47 #define CONFIG_PRAM 512 /* 512 KB */
49 #define CFG_SYS_CLK 80000000
50 #define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3
52 #define CFG_SYS_MBAR 0xFC000000
54 #define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000)
57 * Low Level Configuration Settings
58 * (address mappings, register initial values, etc.)
59 * You should know what you are doing if you make changes here.
61 /*-----------------------------------------------------------------------
62 * Definitions for initial stack pointer and data area (in DPRAM)
64 #define CFG_SYS_INIT_RAM_ADDR 0x80000000
65 #define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
66 #define CFG_SYS_INIT_RAM_CTRL 0x221
68 /*-----------------------------------------------------------------------
69 * Start addresses for the final memory configuration
70 * (Set up by the startup code)
71 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
73 #define CFG_SYS_SDRAM_BASE 0x40000000
74 #define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
75 #define CFG_SYS_SDRAM_CFG1 0x53722730
76 #define CFG_SYS_SDRAM_CFG2 0x56670000
77 #define CFG_SYS_SDRAM_CTRL 0xE1092000
78 #define CFG_SYS_SDRAM_EMOD 0x40010000
79 #define CFG_SYS_SDRAM_MODE 0x018D0000
82 * For booting Linux, the board info and command line data
83 * have to be in the first 8 MB of memory, since this is
84 * the maximum mapped by the Linux kernel during initialization ??
86 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
88 /*-----------------------------------------------------------------------
91 #ifdef CONFIG_SYS_FLASH_CFI
92 # define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
95 # define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE
96 # define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
97 # define NAND_ALLOW_ERASE_ALL 1
99 #define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
101 /* Configuration for environment
102 * Environment is embedded in u-boot in the second sector of the flash
105 #define LDS_BOARD_TEXT \
106 . = DEFINED(env_offset) ? env_offset : .; \
107 env/embedded.o(.text*);
109 /*-----------------------------------------------------------------------
110 * Cache Configuration
113 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
114 CFG_SYS_INIT_RAM_SIZE - 8)
115 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
116 CFG_SYS_INIT_RAM_SIZE - 4)
117 #define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
118 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
119 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
120 CF_ACR_EN | CF_ACR_SM_ALL)
121 #define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
124 /*-----------------------------------------------------------------------
125 * Chipselect bank definitions
128 * CS0 - NOR Flash 1, 2, 4, or 8MB
129 * CS1 - CompactFlash and registers
130 * CS2 - NAND Flash 16, 32, or 64MB
135 #define CFG_SYS_CS0_BASE 0
136 #define CFG_SYS_CS0_MASK 0x007f0001
137 #define CFG_SYS_CS0_CTRL 0x00001fa0
139 #define CFG_SYS_CS1_BASE 0x10000000
140 #define CFG_SYS_CS1_MASK 0x001f0001
141 #define CFG_SYS_CS1_CTRL 0x002A3780
143 #define CFG_SYS_CS2_BASE 0x20000000
144 #define CFG_SYS_CS2_MASK (16 << 20)
145 #define CFG_SYS_CS2_CTRL 0x00001f60
147 #endif /* _M5373EVB_H */