include/configs/M5329EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Freescale MCF5329 FireEngine board.
   4  *
   5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _M5329EVB_H
  14 #define _M5329EVB_H
  15
  16 /*
  17  * High Level Configuration Options
  18  * (easy to change)
  19  */
  20
  21 #define CFG_SYS_UART_PORT               (0)
  22
  23 /* I2C */
  24
  25 #ifdef CONFIG_MCFFEC
  26 #       define CONFIG_IPADDR    192.162.1.2
  27 #       define CONFIG_NETMASK   255.255.255.0
  28 #       define CONFIG_SERVERIP  192.162.1.1
  29 #       define CONFIG_GATEWAYIP 192.162.1.1
  30 #endif                          /* FEC_ENET */
  31
  32 #define CONFIG_HOSTNAME         "M5329EVB"
  33 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  34         "netdev=eth0\0"                 \
  35         "loadaddr=40010000\0"   \
  36         "u-boot=u-boot.bin\0"   \
  37         "load=tftp ${loadaddr) ${u-boot}\0"     \
  38         "upd=run load; run prog\0"      \
  39         "prog=prot off 0 3ffff;"        \
  40         "era 0 3ffff;"  \
  41         "cp.b ${loadaddr} 0 ${filesize};"       \
  42         "save\0"        \
  43         ""
  44
  45 #define CONFIG_PRAM             512     /* 512 KB */
  46
  47 #define CFG_SYS_CLK                     80000000
  48 #define CFG_SYS_CPU_CLK         CFG_SYS_CLK * 3
  49
  50 #define CFG_SYS_MBAR            0xFC000000
  51
  52 #define CFG_SYS_LATCH_ADDR              (CFG_SYS_CS1_BASE + 0x80000)
  53
  54 /*
  55  * Low Level Configuration Settings
  56  * (address mappings, register initial values, etc.)
  57  * You should know what you are doing if you make changes here.
  58  */
  59 /*-----------------------------------------------------------------------
  60  * Definitions for initial stack pointer and data area (in DPRAM)
  61  */
  62 #define CFG_SYS_INIT_RAM_ADDR   0x80000000
  63 #define CFG_SYS_INIT_RAM_SIZE   0x8000  /* Size of used area in internal SRAM */
  64 #define CFG_SYS_INIT_RAM_CTRL   0x221
  65
  66 /*-----------------------------------------------------------------------
  67  * Start addresses for the final memory configuration
  68  * (Set up by the startup code)
  69  * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  70  */
  71 #define CFG_SYS_SDRAM_BASE              0x40000000
  72 #define CFG_SYS_SDRAM_SIZE              32      /* SDRAM size in MB */
  73 #define CFG_SYS_SDRAM_CFG1              0x53722730
  74 #define CFG_SYS_SDRAM_CFG2              0x56670000
  75 #define CFG_SYS_SDRAM_CTRL              0xE1092000
  76 #define CFG_SYS_SDRAM_EMOD              0x40010000
  77 #define CFG_SYS_SDRAM_MODE              0x018D0000
  78
  79 /*
  80  * For booting Linux, the board info and command line data
  81  * have to be in the first 8 MB of memory, since this is
  82  * the maximum mapped by the Linux kernel during initialization ??
  83  */
  84 #define CFG_SYS_BOOTMAPSZ               (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
  85
  86 /*-----------------------------------------------------------------------
  87  * FLASH organization
  88  */
  89 #ifdef CONFIG_SYS_FLASH_CFI
  90 #       define CFG_SYS_FLASH_SIZE               0x800000        /* Max size that the board might have */
  91 #endif
  92
  93 #ifdef CONFIG_CMD_NAND
  94 #       define CFG_SYS_NAND_BASE                CFG_SYS_CS2_BASE
  95 #       define CFG_SYS_NAND_BASE_LIST   { CFG_SYS_NAND_BASE }
  96 #       define NAND_ALLOW_ERASE_ALL     1
  97 #endif
  98
  99 #define CFG_SYS_FLASH_BASE              CFG_SYS_CS0_BASE
 100
 101 /* Configuration for environment
 102  * Environment is embedded in u-boot in the second sector of the flash
 103  */
 104
 105 #define LDS_BOARD_TEXT \
 106         . = DEFINED(env_offset) ? env_offset : .; \
 107         env/embedded.o(.text*);
 108
 109 /*-----------------------------------------------------------------------
 110  * Cache Configuration
 111  */
 112
 113 #define ICACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
 114                                          CFG_SYS_INIT_RAM_SIZE - 8)
 115 #define DCACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
 116                                          CFG_SYS_INIT_RAM_SIZE - 4)
 117 #define CFG_SYS_ICACHE_INV              (CF_CACR_CINVA)
 118 #define CFG_SYS_CACHE_ACR0              (CFG_SYS_SDRAM_BASE | \
 119                                          CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 120                                          CF_ACR_EN | CF_ACR_SM_ALL)
 121 #define CFG_SYS_CACHE_ICACR             (CF_CACR_EC | CF_CACR_CINVA | \
 122                                          CF_CACR_DCM_P)
 123
 124 /*-----------------------------------------------------------------------
 125  * Chipselect bank definitions
 126  */
 127 /*
 128  * CS0 - NOR Flash 1, 2, 4, or 8MB
 129  * CS1 - CompactFlash and registers
 130  * CS2 - NAND Flash 16, 32, or 64MB
 131  * CS3 - Available
 132  * CS4 - Available
 133  * CS5 - Available
 134  */
 135 #define CFG_SYS_CS0_BASE                0
 136 #define CFG_SYS_CS0_MASK                0x007f0001
 137 #define CFG_SYS_CS0_CTRL                0x00001fa0
 138
 139 #define CFG_SYS_CS1_BASE                0x10000000
 140 #define CFG_SYS_CS1_MASK                0x001f0001
 141 #define CFG_SYS_CS1_CTRL                0x002A3780
 142
 143 #ifdef CONFIG_CMD_NAND
 144 #define CFG_SYS_CS2_BASE                0x20000000
 145 #define CFG_SYS_CS2_MASK                (16 << 20)
 146 #define CFG_SYS_CS2_CTRL                0x00001f60
 147 #endif
 148
 149 #endif                          /* _M5329EVB_H */