include/configs/M53017EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Freescale MCF53017EVB.
   4  *
   5  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _M53017EVB_H
  14 #define _M53017EVB_H
  15
  16 /*
  17  * High Level Configuration Options
  18  * (easy to change)
  19  */
  20
  21 #define CONFIG_MCFUART
  22 #define CONFIG_SYS_UART_PORT            (0)
  23
  24 #undef CONFIG_WATCHDOG
  25 #define CONFIG_WATCHDOG_TIMEOUT         5000
  26
  27 #define CONFIG_SYS_UNIFY_CACHE
  28
  29 #ifdef CONFIG_MCFFEC
  30 #       define CONFIG_MII_INIT          1
  31 #       define CONFIG_SYS_DISCOVER_PHY
  32 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  33 #       define CONFIG_SYS_TX_ETH_BUFFER 8
  34 #       define CONFIG_SYS_FEC_BUF_USE_SRAM
  35 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  36 #       define CONFIG_HAS_ETH1
  37
  38 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  39 #       ifndef CONFIG_SYS_DISCOVER_PHY
  40 #               define FECDUPLEX        FULL
  41 #               define FECSPEED         _100BASET
  42 #       else
  43 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  44 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  45 #               endif
  46 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  47 #endif
  48
  49 #define CONFIG_MCFRTC
  50 #undef RTC_DEBUG
  51 #define CONFIG_SYS_RTC_CNT              (0x8000)
  52 #define CONFIG_SYS_RTC_SETUP            (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
  53
  54 /* Timer */
  55 #define CONFIG_MCFTMR
  56
  57 /* I2C */
  58 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
  59
  60 #define CONFIG_UDP_CHECKSUM
  61
  62 #ifdef CONFIG_MCFFEC
  63 #       define CONFIG_IPADDR    192.162.1.2
  64 #       define CONFIG_NETMASK   255.255.255.0
  65 #       define CONFIG_SERVERIP  192.162.1.1
  66 #       define CONFIG_GATEWAYIP 192.162.1.1
  67 #endif                          /* FEC_ENET */
  68
  69 #define CONFIG_HOSTNAME         "M53017"
  70 #define CONFIG_EXTRA_ENV_SETTINGS               \
  71         "netdev=eth0\0"                         \
  72         "loadaddr=40010000\0"                   \
  73         "u-boot=u-boot.bin\0"                   \
  74         "load=tftp ${loadaddr) ${u-boot}\0"     \
  75         "upd=run load; run prog\0"              \
  76         "prog=prot off 0 3ffff;"                \
  77         "era 0 3ffff;"                          \
  78         "cp.b ${loadaddr} 0 ${filesize};"       \
  79         "save\0"                                \
  80         ""
  81
  82 #define CONFIG_PRAM             512     /* 512 KB */
  83
  84 #define CONFIG_SYS_CLK          80000000
  85 #define CONFIG_SYS_CPU_CLK      CONFIG_SYS_CLK * 3
  86
  87 #define CONFIG_SYS_MBAR         0xFC000000
  88
  89 /*
  90  * Low Level Configuration Settings
  91  * (address mappings, register initial values, etc.)
  92  * You should know what you are doing if you make changes here.
  93  */
  94 /*
  95  * Definitions for initial stack pointer and data area (in DPRAM)
  96  */
  97 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
  98 #define CONFIG_SYS_INIT_RAM_SIZE                0x20000 /* Size of used area in internal SRAM */
  99 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 100 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 101 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 102
 103 /*
 104  * Start addresses for the final memory configuration
 105  * (Set up by the startup code)
 106  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 107  */
 108 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 109 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
 110 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 111 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 112 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 113 #define CONFIG_SYS_SDRAM_EMOD           0x80010000
 114 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 115
 116 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
 117 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 118
 119 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 120
 121 /*
 122  * For booting Linux, the board info and command line data
 123  * have to be in the first 8 MB of memory, since this is
 124  * the maximum mapped by the Linux kernel during initialization ??
 125  */
 126 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 127 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 128
 129 /*-----------------------------------------------------------------------
 130  * FLASH organization
 131  */
 132 #ifdef CONFIG_SYS_FLASH_CFI
 133 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
 134 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 135 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 136 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 137 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 138 #endif
 139
 140 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 141
 142 /* Configuration for environment
 143  * Environment is embedded in u-boot in the second sector of the flash
 144  */
 145
 146 #define LDS_BOARD_TEXT \
 147         . = DEFINED(env_offset) ? env_offset : .; \
 148         env/embedded.o(.text*)
 149
 150 /*-----------------------------------------------------------------------
 151  * Cache Configuration
 152  */
 153
 154 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 155                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 156 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 157                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 158 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 159 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 160                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 161                                          CF_ACR_EN | CF_ACR_SM_ALL)
 162 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 163                                          CF_CACR_DCM_P)
 164
 165 /*-----------------------------------------------------------------------
 166  * Chipselect bank definitions
 167  */
 168 /*
 169  * CS0 - NOR Flash
 170  * CS1 - Ext SRAM
 171  * CS2 - Available
 172  * CS3 - Available
 173  * CS4 - Available
 174  * CS5 - Available
 175  */
 176 #define CONFIG_SYS_CS0_BASE             0
 177 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 178 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 179
 180 #define CONFIG_SYS_CS1_BASE             0xC0000000
 181 #define CONFIG_SYS_CS1_MASK             0x00070001
 182 #define CONFIG_SYS_CS1_CTRL             0x00001FA0
 183
 184 #endif                          /* _M53017EVB_H */