include/configs/M53017EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Freescale MCF53017EVB.
   4  *
   5  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _M53017EVB_H
  14 #define _M53017EVB_H
  15
  16 /*
  17  * High Level Configuration Options
  18  * (easy to change)
  19  */
  20
  21 #define CONFIG_SYS_UART_PORT            (0)
  22
  23 #define CONFIG_WATCHDOG_TIMEOUT         5000
  24
  25 #define CONFIG_SYS_UNIFY_CACHE
  26
  27 #ifdef CONFIG_MCFFEC
  28 #       define CONFIG_SYS_DISCOVER_PHY
  29 #       define CONFIG_SYS_TX_ETH_BUFFER 8
  30 #       define CONFIG_SYS_FEC_BUF_USE_SRAM
  31
  32 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  33 #       ifndef CONFIG_SYS_DISCOVER_PHY
  34 #               define FECDUPLEX        FULL
  35 #               define FECSPEED         _100BASET
  36 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  37 #endif
  38
  39 #define CONFIG_MCFRTC
  40 #undef RTC_DEBUG
  41 #define CONFIG_SYS_RTC_CNT              (0x8000)
  42 #define CONFIG_SYS_RTC_SETUP            (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
  43
  44 /* Timer */
  45 #define CONFIG_MCFTMR
  46
  47 /* I2C */
  48
  49 #ifdef CONFIG_MCFFEC
  50 #       define CONFIG_IPADDR    192.162.1.2
  51 #       define CONFIG_NETMASK   255.255.255.0
  52 #       define CONFIG_SERVERIP  192.162.1.1
  53 #       define CONFIG_GATEWAYIP 192.162.1.1
  54 #endif                          /* FEC_ENET */
  55
  56 #define CONFIG_HOSTNAME         "M53017"
  57 #define CONFIG_EXTRA_ENV_SETTINGS               \
  58         "netdev=eth0\0"                         \
  59         "loadaddr=40010000\0"                   \
  60         "u-boot=u-boot.bin\0"                   \
  61         "load=tftp ${loadaddr) ${u-boot}\0"     \
  62         "upd=run load; run prog\0"              \
  63         "prog=prot off 0 3ffff;"                \
  64         "era 0 3ffff;"                          \
  65         "cp.b ${loadaddr} 0 ${filesize};"       \
  66         "save\0"                                \
  67         ""
  68
  69 #define CONFIG_PRAM             512     /* 512 KB */
  70
  71 #define CONFIG_SYS_CLK          80000000
  72 #define CONFIG_SYS_CPU_CLK      CONFIG_SYS_CLK * 3
  73
  74 #define CONFIG_SYS_MBAR         0xFC000000
  75
  76 /*
  77  * Low Level Configuration Settings
  78  * (address mappings, register initial values, etc.)
  79  * You should know what you are doing if you make changes here.
  80  */
  81 /*
  82  * Definitions for initial stack pointer and data area (in DPRAM)
  83  */
  84 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
  85 #define CONFIG_SYS_INIT_RAM_SIZE                0x20000 /* Size of used area in internal SRAM */
  86 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
  87 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
  88 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  89
  90 /*
  91  * Start addresses for the final memory configuration
  92  * (Set up by the startup code)
  93  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  94  */
  95 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  96 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
  97 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
  98 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
  99 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 100 #define CONFIG_SYS_SDRAM_EMOD           0x80010000
 101 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 102
 103 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
 104 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 105
 106 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 107
 108 /*
 109  * For booting Linux, the board info and command line data
 110  * have to be in the first 8 MB of memory, since this is
 111  * the maximum mapped by the Linux kernel during initialization ??
 112  */
 113 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 114 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 115
 116 /*-----------------------------------------------------------------------
 117  * FLASH organization
 118  */
 119 #ifdef CONFIG_SYS_FLASH_CFI
 120 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
 121 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 122 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 123 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 124 #endif
 125
 126 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 127
 128 /* Configuration for environment
 129  * Environment is embedded in u-boot in the second sector of the flash
 130  */
 131
 132 #define LDS_BOARD_TEXT \
 133         . = DEFINED(env_offset) ? env_offset : .; \
 134         env/embedded.o(.text*)
 135
 136 /*-----------------------------------------------------------------------
 137  * Cache Configuration
 138  */
 139
 140 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 141                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 142 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 143                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 144 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 145 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 146                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 147                                          CF_ACR_EN | CF_ACR_SM_ALL)
 148 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 149                                          CF_CACR_DCM_P)
 150
 151 /*-----------------------------------------------------------------------
 152  * Chipselect bank definitions
 153  */
 154 /*
 155  * CS0 - NOR Flash
 156  * CS1 - Ext SRAM
 157  * CS2 - Available
 158  * CS3 - Available
 159  * CS4 - Available
 160  * CS5 - Available
 161  */
 162 #define CONFIG_SYS_CS0_BASE             0
 163 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 164 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 165
 166 #define CONFIG_SYS_CS1_BASE             0xC0000000
 167 #define CONFIG_SYS_CS1_MASK             0x00070001
 168 #define CONFIG_SYS_CS1_CTRL             0x00001FA0
 169
 170 #endif                          /* _M53017EVB_H */