1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF53017EVB.
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_MCFUART
22 #define CONFIG_SYS_UART_PORT (0)
24 #undef CONFIG_WATCHDOG
25 #define CONFIG_WATCHDOG_TIMEOUT 5000
27 #define CONFIG_SYS_UNIFY_CACHE
30 # define CONFIG_MII_INIT 1
31 # define CONFIG_SYS_DISCOVER_PHY
32 # define CONFIG_SYS_RX_ETH_BUFFER 8
33 # define CONFIG_SYS_TX_ETH_BUFFER 8
34 # define CONFIG_SYS_FEC_BUF_USE_SRAM
35 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
36 # define CONFIG_HAS_ETH1
38 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
39 # ifndef CONFIG_SYS_DISCOVER_PHY
40 # define FECDUPLEX FULL
41 # define FECSPEED _100BASET
43 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
44 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
46 # endif /* CONFIG_SYS_DISCOVER_PHY */
51 #define CONFIG_SYS_RTC_CNT (0x8000)
52 #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
59 #define CONFIG_SYS_I2C
60 #define CONFIG_SYS_I2C_FSL
61 #define CONFIG_SYS_FSL_I2C_SPEED 80000
62 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
63 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
64 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
66 #define CONFIG_UDP_CHECKSUM
69 # define CONFIG_IPADDR 192.162.1.2
70 # define CONFIG_NETMASK 255.255.255.0
71 # define CONFIG_SERVERIP 192.162.1.1
72 # define CONFIG_GATEWAYIP 192.162.1.1
75 #define CONFIG_HOSTNAME "M53017"
76 #define CONFIG_EXTRA_ENV_SETTINGS \
78 "loadaddr=40010000\0" \
79 "u-boot=u-boot.bin\0" \
80 "load=tftp ${loadaddr) ${u-boot}\0" \
81 "upd=run load; run prog\0" \
82 "prog=prot off 0 3ffff;" \
84 "cp.b ${loadaddr} 0 ${filesize};" \
88 #define CONFIG_PRAM 512 /* 512 KB */
90 #define CONFIG_SYS_LOAD_ADDR 0x40010000
92 #define CONFIG_SYS_CLK 80000000
93 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
95 #define CONFIG_SYS_MBAR 0xFC000000
98 * Low Level Configuration Settings
99 * (address mappings, register initial values, etc.)
100 * You should know what you are doing if you make changes here.
103 * Definitions for initial stack pointer and data area (in DPRAM)
105 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
106 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
107 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
108 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
109 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
112 * Start addresses for the final memory configuration
113 * (Set up by the startup code)
114 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
116 #define CONFIG_SYS_SDRAM_BASE 0x40000000
117 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
118 #define CONFIG_SYS_SDRAM_CFG1 0x43711630
119 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
120 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
121 #define CONFIG_SYS_SDRAM_EMOD 0x80010000
122 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
124 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
125 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
127 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
128 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
130 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
131 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
134 * For booting Linux, the board info and command line data
135 * have to be in the first 8 MB of memory, since this is
136 * the maximum mapped by the Linux kernel during initialization ??
138 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
139 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
141 /*-----------------------------------------------------------------------
144 #ifdef CONFIG_SYS_FLASH_CFI
145 # define CONFIG_FLASH_SPANSION_S29WS_N 1
146 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
147 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
148 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
149 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
152 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
154 /* Configuration for environment
155 * Environment is embedded in u-boot in the second sector of the flash
158 #define LDS_BOARD_TEXT \
159 . = DEFINED(env_offset) ? env_offset : .; \
160 env/embedded.o(.text*)
162 /*-----------------------------------------------------------------------
163 * Cache Configuration
165 #define CONFIG_SYS_CACHELINE_SIZE 16
167 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
168 CONFIG_SYS_INIT_RAM_SIZE - 8)
169 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
170 CONFIG_SYS_INIT_RAM_SIZE - 4)
171 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
172 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
173 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
174 CF_ACR_EN | CF_ACR_SM_ALL)
175 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
178 /*-----------------------------------------------------------------------
179 * Chipselect bank definitions
189 #define CONFIG_SYS_CS0_BASE 0
190 #define CONFIG_SYS_CS0_MASK 0x00FF0001
191 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
193 #define CONFIG_SYS_CS1_BASE 0xC0000000
194 #define CONFIG_SYS_CS1_MASK 0x00070001
195 #define CONFIG_SYS_CS1_CTRL 0x00001FA0
197 #endif /* _M53017EVB_H */