include/configs/M5282EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Motorola MC5282EVB board.
   4  *
   5  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef _CONFIG_M5282EVB_H
  13 #define _CONFIG_M5282EVB_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19 #define CONFIG_MCFTMR
  20
  21 #define CONFIG_MCFUART
  22 #define CONFIG_SYS_UART_PORT            (0)
  23
  24 #undef  CONFIG_MONITOR_IS_IN_RAM        /* define if monitor is started from a pre-loader */
  25
  26 /* Configuration for environment
  27  * Environment is embedded in u-boot in the second sector of the flash
  28  */
  29
  30 #define LDS_BOARD_TEXT \
  31         . = DEFINED(env_offset) ? env_offset : .; \
  32         env/embedded.o(.text*);
  33
  34 /*
  35  * BOOTP options
  36  */
  37 #define CONFIG_BOOTP_BOOTFILESIZE
  38
  39 /*
  40  * Command line configuration.
  41  */
  42
  43 #define CONFIG_MCFFEC
  44 #ifdef CONFIG_MCFFEC
  45 #       define CONFIG_MII_INIT          1
  46 #       define CONFIG_SYS_DISCOVER_PHY
  47 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  48 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  49
  50 #       define CONFIG_SYS_FEC0_PINMUX           0
  51 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  52 #       define MCFFEC_TOUT_LOOP         50000
  53 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  54 #       ifndef CONFIG_SYS_DISCOVER_PHY
  55 #               define FECDUPLEX        FULL
  56 #               define FECSPEED         _100BASET
  57 #       else
  58 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  59 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  60 #               endif
  61 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  62 #endif
  63
  64 #ifdef CONFIG_MCFFEC
  65 #       define CONFIG_IPADDR    192.162.1.2
  66 #       define CONFIG_NETMASK   255.255.255.0
  67 #       define CONFIG_SERVERIP  192.162.1.1
  68 #       define CONFIG_GATEWAYIP 192.162.1.1
  69 #endif                          /* CONFIG_MCFFEC */
  70
  71 #define CONFIG_HOSTNAME         "M5282EVB"
  72 #define CONFIG_EXTRA_ENV_SETTINGS               \
  73         "netdev=eth0\0"                         \
  74         "loadaddr=10000\0"                      \
  75         "u-boot=u-boot.bin\0"                   \
  76         "load=tftp ${loadaddr) ${u-boot}\0"     \
  77         "upd=run load; run prog\0"              \
  78         "prog=prot off ffe00000 ffe3ffff;"      \
  79         "era ffe00000 ffe3ffff;"                \
  80         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  81         "save\0"                                \
  82         ""
  83
  84 #define CONFIG_SYS_LOAD_ADDR            0x20000
  85
  86 #define CONFIG_SYS_MEMTEST_START        0x400
  87 #define CONFIG_SYS_MEMTEST_END          0x380000
  88
  89 #define CONFIG_SYS_CLK                  64000000
  90
  91 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
  92
  93 #define CONFIG_SYS_MFD                  0x02    /* PLL Multiplication Factor Devider */
  94 #define CONFIG_SYS_RFD                  0x00    /* PLL Reduce Frecuency Devider */
  95
  96 /*
  97  * Low Level Configuration Settings
  98  * (address mappings, register initial values, etc.)
  99  * You should know what you are doing if you make changes here.
 100  */
 101 #define CONFIG_SYS_MBAR         0x40000000
 102
 103 /*-----------------------------------------------------------------------
 104  * Definitions for initial stack pointer and data area (in DPRAM)
 105  */
 106 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 107 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM    */
 108 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 109 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 110
 111 /*-----------------------------------------------------------------------
 112  * Start addresses for the final memory configuration
 113  * (Set up by the startup code)
 114  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 115  */
 116 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 117 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 118 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 119 #define CONFIG_SYS_INT_FLASH_BASE       0xf0000000
 120 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 121
 122 /* If M5282 port is fully implemented the monitor base will be behind
 123  * the vector table. */
 124 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
 125 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 126 #else
 127 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418)  /* 24 Byte for CFM-Config */
 128 #endif
 129
 130 #define CONFIG_SYS_MONITOR_LEN          0x20000
 131 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 132 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 133
 134 /*
 135  * For booting Linux, the board info and command line data
 136  * have to be in the first 8 MB of memory, since this is
 137  * the maximum mapped by the Linux kernel during initialization ??
 138  */
 139 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 140
 141 /*-----------------------------------------------------------------------
 142  * FLASH organization
 143  */
 144 #ifdef CONFIG_SYS_FLASH_CFI
 145
 146 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 147 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 148 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 149 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 150 #       define CONFIG_SYS_FLASH_CHECKSUM
 151 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_FLASH_BASE }
 152 #endif
 153
 154 /*-----------------------------------------------------------------------
 155  * Cache Configuration
 156  */
 157 #define CONFIG_SYS_CACHELINE_SIZE       16
 158
 159 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 160                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 161 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 162                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 163 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 164 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 165                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 166                                          CF_ACR_EN | CF_ACR_SM_ALL)
 167 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 168                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 169                                          CF_CACR_EUSP)
 170
 171 /*-----------------------------------------------------------------------
 172  * Memory bank definitions
 173  */
 174 #define CONFIG_SYS_CS0_BASE             0xFFE00000
 175 #define CONFIG_SYS_CS0_CTRL             0x00001980
 176 #define CONFIG_SYS_CS0_MASK             0x001F0001
 177
 178 /*-----------------------------------------------------------------------
 179  * Port configuration
 180  */
 181 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 182 #define CONFIG_SYS_PADDR                0x0000000
 183 #define CONFIG_SYS_PADAT                0x0000000
 184
 185 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 186 #define CONFIG_SYS_PBDDR                0x0000000
 187 #define CONFIG_SYS_PBDAT                0x0000000
 188
 189 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 190 #define CONFIG_SYS_PCDDR                0x0000000
 191 #define CONFIG_SYS_PCDAT                0x0000000
 192
 193 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 194 #define CONFIG_SYS_PCDDR                0x0000000
 195 #define CONFIG_SYS_PCDAT                0x0000000
 196
 197 #define CONFIG_SYS_PEHLPAR              0xC0
 198 #define CONFIG_SYS_PUAPAR               0x0F    /* UA0..UA3 = Uart 0 +1 */
 199 #define CONFIG_SYS_DDRUA                0x05
 200 #define CONFIG_SYS_PJPAR                0xFF
 201
 202 #endif                          /* _CONFIG_M5282EVB_H */