include/configs/M5282EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Motorola MC5282EVB board.
   4  *
   5  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef _CONFIG_M5282EVB_H
  13 #define _CONFIG_M5282EVB_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CFG_SYS_UART_PORT               (0)
  21
  22 #undef  CONFIG_MONITOR_IS_IN_RAM        /* define if monitor is started from a pre-loader */
  23
  24 /* Configuration for environment
  25  * Environment is embedded in u-boot in the second sector of the flash
  26  */
  27
  28 #define LDS_BOARD_TEXT \
  29         . = DEFINED(env_offset) ? env_offset : .; \
  30         env/embedded.o(.text*);
  31
  32 #define CONFIG_EXTRA_ENV_SETTINGS               \
  33         "netdev=eth0\0"                         \
  34         "loadaddr=10000\0"                      \
  35         "u-boot=u-boot.bin\0"                   \
  36         "load=tftp ${loadaddr) ${u-boot}\0"     \
  37         "upd=run load; run prog\0"              \
  38         "prog=prot off ffe00000 ffe3ffff;"      \
  39         "era ffe00000 ffe3ffff;"                \
  40         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  41         "save\0"                                \
  42         ""
  43
  44 #define CFG_SYS_CLK                     64000000
  45
  46 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
  47
  48 #define CFG_SYS_MFD                     0x02    /* PLL Multiplication Factor Devider */
  49 #define CFG_SYS_RFD                     0x00    /* PLL Reduce Frecuency Devider */
  50
  51 /*
  52  * Low Level Configuration Settings
  53  * (address mappings, register initial values, etc.)
  54  * You should know what you are doing if you make changes here.
  55  */
  56 #define CFG_SYS_MBAR            0x40000000
  57
  58 /*-----------------------------------------------------------------------
  59  * Definitions for initial stack pointer and data area (in DPRAM)
  60  */
  61 #define CFG_SYS_INIT_RAM_ADDR   0x20000000
  62 #define CFG_SYS_INIT_RAM_SIZE   0x10000 /* Size of used area in internal SRAM    */
  63
  64 /*-----------------------------------------------------------------------
  65  * Start addresses for the final memory configuration
  66  * (Set up by the startup code)
  67  * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  68  */
  69 #define CFG_SYS_SDRAM_BASE              0x00000000
  70 #define CFG_SYS_SDRAM_SIZE              16      /* SDRAM size in MB */
  71 #define CFG_SYS_FLASH_BASE              CFG_SYS_CS0_BASE
  72 #define CFG_SYS_INT_FLASH_BASE  0xf0000000
  73 #define CFG_SYS_INT_FLASH_ENABLE        0x21
  74
  75 /*
  76  * For booting Linux, the board info and command line data
  77  * have to be in the first 8 MB of memory, since this is
  78  * the maximum mapped by the Linux kernel during initialization ??
  79  */
  80 #define CFG_SYS_BOOTMAPSZ               (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
  81
  82 /*-----------------------------------------------------------------------
  83  * FLASH organization
  84  */
  85 #ifdef CONFIG_SYS_FLASH_CFI
  86
  87 #       define CFG_SYS_FLASH_SIZE               0x1000000       /* Max size that the board might have */
  88 #       define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
  89 #endif
  90
  91 /*-----------------------------------------------------------------------
  92  * Cache Configuration
  93  */
  94
  95 #define ICACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
  96                                          CFG_SYS_INIT_RAM_SIZE - 8)
  97 #define DCACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
  98                                          CFG_SYS_INIT_RAM_SIZE - 4)
  99 #define CFG_SYS_ICACHE_INV              (CF_CACR_CINV + CF_CACR_DCM)
 100 #define CFG_SYS_CACHE_ACR0              (CFG_SYS_SDRAM_BASE | \
 101                                          CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 102                                          CF_ACR_EN | CF_ACR_SM_ALL)
 103 #define CFG_SYS_CACHE_ICACR             (CF_CACR_CENB | CF_CACR_DISD | \
 104                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 105                                          CF_CACR_EUSP)
 106
 107 /*-----------------------------------------------------------------------
 108  * Memory bank definitions
 109  */
 110 #define CFG_SYS_CS0_BASE                0xFFE00000
 111 #define CFG_SYS_CS0_CTRL                0x00001980
 112 #define CFG_SYS_CS0_MASK                0x001F0001
 113
 114 /*-----------------------------------------------------------------------
 115  * Port configuration
 116  */
 117 #define CFG_SYS_PACNT           0x0000000       /* Port A D[31:24] */
 118 #define CFG_SYS_PADDR           0x0000000
 119 #define CFG_SYS_PADAT           0x0000000
 120
 121 #define CFG_SYS_PBCNT           0x0000000       /* Port B D[23:16] */
 122 #define CFG_SYS_PBDDR           0x0000000
 123 #define CFG_SYS_PBDAT           0x0000000
 124
 125 #define CFG_SYS_PDCNT           0x0000000       /* Port D D[07:00] */
 126
 127 #define CFG_SYS_PEHLPAR         0xC0
 128 #define CFG_SYS_PUAPAR          0x0F    /* UA0..UA3 = Uart 0 +1 */
 129 #define CFG_SYS_DDRUA           0x05
 130 #define CFG_SYS_PJPAR           0xFF
 131
 132 #endif                          /* _CONFIG_M5282EVB_H */