include/configs/M5282EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Motorola MC5282EVB board.
   4  *
   5  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef _CONFIG_M5282EVB_H
  13 #define _CONFIG_M5282EVB_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19 #define CONFIG_MCFTMR
  20
  21 #define CONFIG_SYS_UART_PORT            (0)
  22
  23 #undef  CONFIG_MONITOR_IS_IN_RAM        /* define if monitor is started from a pre-loader */
  24
  25 /* Configuration for environment
  26  * Environment is embedded in u-boot in the second sector of the flash
  27  */
  28
  29 #define LDS_BOARD_TEXT \
  30         . = DEFINED(env_offset) ? env_offset : .; \
  31         env/embedded.o(.text*);
  32
  33 /*
  34  * BOOTP options
  35  */
  36 #define CONFIG_BOOTP_BOOTFILESIZE
  37
  38 #ifdef CONFIG_MCFFEC
  39 #       define CONFIG_MII_INIT          1
  40 #       define CONFIG_SYS_DISCOVER_PHY
  41 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  42 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  43 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  44 #       ifndef CONFIG_SYS_DISCOVER_PHY
  45 #               define FECDUPLEX        FULL
  46 #               define FECSPEED         _100BASET
  47 #       else
  48 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  49 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  50 #               endif
  51 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  52 #endif
  53
  54 #ifdef CONFIG_MCFFEC
  55 #       define CONFIG_IPADDR    192.162.1.2
  56 #       define CONFIG_NETMASK   255.255.255.0
  57 #       define CONFIG_SERVERIP  192.162.1.1
  58 #       define CONFIG_GATEWAYIP 192.162.1.1
  59 #endif                          /* CONFIG_MCFFEC */
  60
  61 #define CONFIG_HOSTNAME         "M5282EVB"
  62 #define CONFIG_EXTRA_ENV_SETTINGS               \
  63         "netdev=eth0\0"                         \
  64         "loadaddr=10000\0"                      \
  65         "u-boot=u-boot.bin\0"                   \
  66         "load=tftp ${loadaddr) ${u-boot}\0"     \
  67         "upd=run load; run prog\0"              \
  68         "prog=prot off ffe00000 ffe3ffff;"      \
  69         "era ffe00000 ffe3ffff;"                \
  70         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  71         "save\0"                                \
  72         ""
  73
  74 #define CONFIG_SYS_CLK                  64000000
  75
  76 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
  77
  78 #define CONFIG_SYS_MFD                  0x02    /* PLL Multiplication Factor Devider */
  79 #define CONFIG_SYS_RFD                  0x00    /* PLL Reduce Frecuency Devider */
  80
  81 /*
  82  * Low Level Configuration Settings
  83  * (address mappings, register initial values, etc.)
  84  * You should know what you are doing if you make changes here.
  85  */
  86 #define CONFIG_SYS_MBAR         0x40000000
  87
  88 /*-----------------------------------------------------------------------
  89  * Definitions for initial stack pointer and data area (in DPRAM)
  90  */
  91 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  92 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM    */
  93 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  94 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  95
  96 /*-----------------------------------------------------------------------
  97  * Start addresses for the final memory configuration
  98  * (Set up by the startup code)
  99  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 100  */
 101 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 102 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 103 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 104 #define CONFIG_SYS_INT_FLASH_BASE       0xf0000000
 105 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 106
 107 /* If M5282 port is fully implemented the monitor base will be behind
 108  * the vector table. */
 109 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
 110 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 111 #else
 112 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418)  /* 24 Byte for CFM-Config */
 113 #endif
 114
 115 #define CONFIG_SYS_MONITOR_LEN          0x20000
 116 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 117
 118 /*
 119  * For booting Linux, the board info and command line data
 120  * have to be in the first 8 MB of memory, since this is
 121  * the maximum mapped by the Linux kernel during initialization ??
 122  */
 123 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 124
 125 /*-----------------------------------------------------------------------
 126  * FLASH organization
 127  */
 128 #ifdef CONFIG_SYS_FLASH_CFI
 129
 130 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 131 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 132 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 133 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 134 #       define CONFIG_SYS_FLASH_CHECKSUM
 135 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_FLASH_BASE }
 136 #endif
 137
 138 /*-----------------------------------------------------------------------
 139  * Cache Configuration
 140  */
 141
 142 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 143                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 144 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 145                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 146 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 147 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 148                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 149                                          CF_ACR_EN | CF_ACR_SM_ALL)
 150 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 151                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 152                                          CF_CACR_EUSP)
 153
 154 /*-----------------------------------------------------------------------
 155  * Memory bank definitions
 156  */
 157 #define CONFIG_SYS_CS0_BASE             0xFFE00000
 158 #define CONFIG_SYS_CS0_CTRL             0x00001980
 159 #define CONFIG_SYS_CS0_MASK             0x001F0001
 160
 161 /*-----------------------------------------------------------------------
 162  * Port configuration
 163  */
 164 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 165 #define CONFIG_SYS_PADDR                0x0000000
 166 #define CONFIG_SYS_PADAT                0x0000000
 167
 168 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 169 #define CONFIG_SYS_PBDDR                0x0000000
 170 #define CONFIG_SYS_PBDAT                0x0000000
 171
 172 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 173 #define CONFIG_SYS_PCDDR                0x0000000
 174 #define CONFIG_SYS_PCDAT                0x0000000
 175
 176 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 177 #define CONFIG_SYS_PCDDR                0x0000000
 178 #define CONFIG_SYS_PCDAT                0x0000000
 179
 180 #define CONFIG_SYS_PEHLPAR              0xC0
 181 #define CONFIG_SYS_PUAPAR               0x0F    /* UA0..UA3 = Uart 0 +1 */
 182 #define CONFIG_SYS_DDRUA                0x05
 183 #define CONFIG_SYS_PJPAR                0xFF
 184
 185 #endif                          /* _CONFIG_M5282EVB_H */