configs: purge unneeded fec defines
[platform/kernel/u-boot.git] / include / configs / M5282EVB.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Configuation settings for the Motorola MC5282EVB board.
4  *
5  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
6  */
7
8 /*
9  * board/config.h - configuration options, board specific
10  */
11
12 #ifndef _CONFIG_M5282EVB_H
13 #define _CONFIG_M5282EVB_H
14
15 /*
16  * High Level Configuration Options
17  * (easy to change)
18  */
19 #define CONFIG_MCFTMR
20
21 #define CONFIG_MCFUART
22 #define CONFIG_SYS_UART_PORT            (0)
23
24 #undef  CONFIG_MONITOR_IS_IN_RAM        /* define if monitor is started from a pre-loader */
25
26 /* Configuration for environment
27  * Environment is embedded in u-boot in the second sector of the flash
28  */
29
30 #define LDS_BOARD_TEXT \
31         . = DEFINED(env_offset) ? env_offset : .; \
32         env/embedded.o(.text*);
33
34 /*
35  * BOOTP options
36  */
37 #define CONFIG_BOOTP_BOOTFILESIZE
38
39 /*
40  * Command line configuration.
41  */
42 #ifdef CONFIG_MCFFEC
43 #       define CONFIG_MII_INIT          1
44 #       define CONFIG_SYS_DISCOVER_PHY
45 #       define CONFIG_SYS_RX_ETH_BUFFER 8
46 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
47 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
48 #       ifndef CONFIG_SYS_DISCOVER_PHY
49 #               define FECDUPLEX        FULL
50 #               define FECSPEED         _100BASET
51 #       else
52 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
53 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
54 #               endif
55 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
56 #endif
57
58 #ifdef CONFIG_MCFFEC
59 #       define CONFIG_IPADDR    192.162.1.2
60 #       define CONFIG_NETMASK   255.255.255.0
61 #       define CONFIG_SERVERIP  192.162.1.1
62 #       define CONFIG_GATEWAYIP 192.162.1.1
63 #endif                          /* CONFIG_MCFFEC */
64
65 #define CONFIG_HOSTNAME         "M5282EVB"
66 #define CONFIG_EXTRA_ENV_SETTINGS               \
67         "netdev=eth0\0"                         \
68         "loadaddr=10000\0"                      \
69         "u-boot=u-boot.bin\0"                   \
70         "load=tftp ${loadaddr) ${u-boot}\0"     \
71         "upd=run load; run prog\0"              \
72         "prog=prot off ffe00000 ffe3ffff;"      \
73         "era ffe00000 ffe3ffff;"                \
74         "cp.b ${loadaddr} ffe00000 ${filesize};"\
75         "save\0"                                \
76         ""
77
78 #define CONFIG_SYS_LOAD_ADDR            0x20000
79
80 #define CONFIG_SYS_MEMTEST_START        0x400
81 #define CONFIG_SYS_MEMTEST_END          0x380000
82
83 #define CONFIG_SYS_CLK                  64000000
84
85 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
86
87 #define CONFIG_SYS_MFD                  0x02    /* PLL Multiplication Factor Devider */
88 #define CONFIG_SYS_RFD                  0x00    /* PLL Reduce Frecuency Devider */
89
90 /*
91  * Low Level Configuration Settings
92  * (address mappings, register initial values, etc.)
93  * You should know what you are doing if you make changes here.
94  */
95 #define CONFIG_SYS_MBAR         0x40000000
96
97 /*-----------------------------------------------------------------------
98  * Definitions for initial stack pointer and data area (in DPRAM)
99  */
100 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
101 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM    */
102 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
103 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
104
105 /*-----------------------------------------------------------------------
106  * Start addresses for the final memory configuration
107  * (Set up by the startup code)
108  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
109  */
110 #define CONFIG_SYS_SDRAM_BASE           0x00000000
111 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
112 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
113 #define CONFIG_SYS_INT_FLASH_BASE       0xf0000000
114 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
115
116 /* If M5282 port is fully implemented the monitor base will be behind
117  * the vector table. */
118 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
119 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
120 #else
121 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418)  /* 24 Byte for CFM-Config */
122 #endif
123
124 #define CONFIG_SYS_MONITOR_LEN          0x20000
125 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
126 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
127
128 /*
129  * For booting Linux, the board info and command line data
130  * have to be in the first 8 MB of memory, since this is
131  * the maximum mapped by the Linux kernel during initialization ??
132  */
133 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
134
135 /*-----------------------------------------------------------------------
136  * FLASH organization
137  */
138 #ifdef CONFIG_SYS_FLASH_CFI
139
140 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
141 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
142 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
143 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
144 #       define CONFIG_SYS_FLASH_CHECKSUM
145 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_FLASH_BASE }
146 #endif
147
148 /*-----------------------------------------------------------------------
149  * Cache Configuration
150  */
151 #define CONFIG_SYS_CACHELINE_SIZE       16
152
153 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
154                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
155 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
156                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
157 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
158 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
159                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
160                                          CF_ACR_EN | CF_ACR_SM_ALL)
161 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
162                                          CF_CACR_CEIB | CF_CACR_DBWE | \
163                                          CF_CACR_EUSP)
164
165 /*-----------------------------------------------------------------------
166  * Memory bank definitions
167  */
168 #define CONFIG_SYS_CS0_BASE             0xFFE00000
169 #define CONFIG_SYS_CS0_CTRL             0x00001980
170 #define CONFIG_SYS_CS0_MASK             0x001F0001
171
172 /*-----------------------------------------------------------------------
173  * Port configuration
174  */
175 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
176 #define CONFIG_SYS_PADDR                0x0000000
177 #define CONFIG_SYS_PADAT                0x0000000
178
179 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
180 #define CONFIG_SYS_PBDDR                0x0000000
181 #define CONFIG_SYS_PBDAT                0x0000000
182
183 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
184 #define CONFIG_SYS_PCDDR                0x0000000
185 #define CONFIG_SYS_PCDAT                0x0000000
186
187 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
188 #define CONFIG_SYS_PCDDR                0x0000000
189 #define CONFIG_SYS_PCDAT                0x0000000
190
191 #define CONFIG_SYS_PEHLPAR              0xC0
192 #define CONFIG_SYS_PUAPAR               0x0F    /* UA0..UA3 = Uart 0 +1 */
193 #define CONFIG_SYS_DDRUA                0x05
194 #define CONFIG_SYS_PJPAR                0xFF
195
196 #endif                          /* _CONFIG_M5282EVB_H */