1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Motorola MC5275EVB board.
5 * By Arthur Shipkowski <art@videon-central.com>
6 * Copyright (C) 2005 Videon Central, Inc.
8 * Based off of M5272C3 board code by Josef Baumgartner
9 * <josef.baumgartner@telex.de>
13 * board/config.h - configuration options, board specific
20 * High Level Configuration Options
26 #define CONFIG_MCFUART
27 #define CONFIG_SYS_UART_PORT (0)
29 /* Configuration for environment
30 * Environment is embedded in u-boot in the second sector of the flash
33 #define LDS_BOARD_TEXT \
34 . = DEFINED(env_offset) ? env_offset : .; \
35 env/embedded.o(.text);
40 #define CONFIG_BOOTP_BOOTFILESIZE
42 /* Available command configuration */
45 #define CONFIG_MII_INIT 1
46 #define CONFIG_SYS_DISCOVER_PHY
47 #define CONFIG_SYS_RX_ETH_BUFFER 8
48 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
49 #define CONFIG_HAS_ETH1
50 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
51 #ifndef CONFIG_SYS_DISCOVER_PHY
52 #define FECDUPLEX FULL
53 #define FECSPEED _100BASET
55 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
56 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
62 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
63 #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
64 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
65 #define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
67 #define CONFIG_SYS_LOAD_ADDR 0x800000
69 #define CONFIG_BOOTCOMMAND "bootm ffe40000"
72 # define CONFIG_NET_RETRY_COUNT 5
73 # define CONFIG_OVERWRITE_ETHADDR_ONCE
76 #define CONFIG_EXTRA_ENV_SETTINGS \
79 "uboot=u-boot.bin\0" \
80 "load=tftp ${loadaddr} ${uboot}\0" \
81 "upd=run load; run prog\0" \
82 "prog=prot off ffe00000 ffe3ffff;" \
83 "era ffe00000 ffe3ffff;" \
84 "cp.b ${loadaddr} ffe00000 ${filesize};"\
88 #define CONFIG_SYS_CLK 150000000
91 * Low Level Configuration Settings
92 * (address mappings, register initial values, etc.)
93 * You should know what you are doing if you make changes here.
96 #define CONFIG_SYS_MBAR 0x40000000
98 /*-----------------------------------------------------------------------
99 * Definitions for initial stack pointer and data area (in DPRAM)
101 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
102 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
103 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
104 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
106 /*-----------------------------------------------------------------------
107 * Start addresses for the final memory configuration
108 * (Set up by the startup code)
109 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
111 #define CONFIG_SYS_SDRAM_BASE 0x00000000
112 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
113 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
115 #ifdef CONFIG_MONITOR_IS_IN_RAM
116 #define CONFIG_SYS_MONITOR_BASE 0x20000
118 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
121 #define CONFIG_SYS_MONITOR_LEN 0x20000
122 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
123 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
126 * For booting Linux, the board info and command line data
127 * have to be in the first 8 MB of memory, since this is
128 * the maximum mapped by the Linux kernel during initialization ??
130 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
131 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
133 /*-----------------------------------------------------------------------
136 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
137 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
138 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
140 #define CONFIG_SYS_FLASH_SIZE 0x200000
142 /*-----------------------------------------------------------------------
143 * Cache Configuration
145 #define CONFIG_SYS_CACHELINE_SIZE 16
147 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
148 CONFIG_SYS_INIT_RAM_SIZE - 8)
149 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
150 CONFIG_SYS_INIT_RAM_SIZE - 4)
151 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
152 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
153 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
154 CF_ACR_EN | CF_ACR_SM_ALL)
155 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
156 CF_CACR_DISD | CF_CACR_INVI | \
157 CF_CACR_CEIB | CF_CACR_DCM | \
160 /*-----------------------------------------------------------------------
161 * Memory bank definitions
163 #define CONFIG_SYS_CS0_BASE 0xffe00000
164 #define CONFIG_SYS_CS0_CTRL 0x00001980
165 #define CONFIG_SYS_CS0_MASK 0x001F0001
167 #define CONFIG_SYS_CS1_BASE 0x30000000
168 #define CONFIG_SYS_CS1_CTRL 0x00001900
169 #define CONFIG_SYS_CS1_MASK 0x00070001
171 /*-----------------------------------------------------------------------
174 #define CONFIG_SYS_FECI2C 0x0FA0
176 #endif /* _M5275EVB_H */