include/configs/M5272C3.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Motorola MC5272C3 board.
   4  *
   5  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef _M5272C3_H
  13 #define _M5272C3_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CFG_SYS_UART_PORT               (0)
  21
  22 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
  23
  24 /* Configuration for environment
  25  * Environment is embedded in u-boot in the second sector of the flash
  26  */
  27
  28 #define LDS_BOARD_TEXT \
  29         . = DEFINED(env_offset) ? env_offset : .; \
  30         env/embedded.o(.text);
  31
  32 #define CONFIG_EXTRA_ENV_SETTINGS               \
  33         "netdev=eth0\0"                         \
  34         "loadaddr=10000\0"                      \
  35         "u-boot=u-boot.bin\0"                   \
  36         "load=tftp ${loadaddr) ${u-boot}\0"     \
  37         "upd=run load; run prog\0"              \
  38         "prog=prot off ffe00000 ffe3ffff;"      \
  39         "era ffe00000 ffe3ffff;"                \
  40         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  41         "save\0"                                \
  42         ""
  43
  44 #define CFG_SYS_CLK                     66000000
  45
  46 /*
  47  * Low Level Configuration Settings
  48  * (address mappings, register initial values, etc.)
  49  * You should know what you are doing if you make changes here.
  50  */
  51 #define CFG_SYS_MBAR            0x10000000      /* Register Base Addrs */
  52 #define CFG_SYS_SCR                     0x0003
  53 #define CFG_SYS_SPR                     0xffff
  54
  55 /*-----------------------------------------------------------------------
  56  * Definitions for initial stack pointer and data area (in DPRAM)
  57  */
  58 #define CFG_SYS_INIT_RAM_ADDR   0x20000000
  59 #define CFG_SYS_INIT_RAM_SIZE   0x1000  /* Size of used area in internal SRAM    */
  60
  61 /*-----------------------------------------------------------------------
  62  * Start addresses for the final memory configuration
  63  * (Set up by the startup code)
  64  * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  65  */
  66 #define CFG_SYS_SDRAM_BASE              0x00000000
  67 #define CFG_SYS_SDRAM_SIZE              4       /* SDRAM size in MB */
  68 #define CFG_SYS_FLASH_BASE              0xffe00000
  69
  70 /*
  71  * For booting Linux, the board info and command line data
  72  * have to be in the first 8 MB of memory, since this is
  73  * the maximum mapped by the Linux kernel during initialization ??
  74  */
  75 #define CFG_SYS_BOOTMAPSZ               (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
  76
  77 /*
  78  * FLASH organization
  79  */
  80 #ifdef CONFIG_SYS_FLASH_CFI
  81 #       define CFG_SYS_FLASH_SIZE               0x800000        /* Max size that the board might have */
  82 #endif
  83
  84 /*-----------------------------------------------------------------------
  85  * Cache Configuration
  86  */
  87
  88 #define ICACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
  89                                          CFG_SYS_INIT_RAM_SIZE - 8)
  90 #define DCACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
  91                                          CFG_SYS_INIT_RAM_SIZE - 4)
  92 #define CFG_SYS_ICACHE_INV              (CF_CACR_CINV | CF_CACR_INVI)
  93 #define CFG_SYS_CACHE_ACR0              (CFG_SYS_SDRAM_BASE | \
  94                                          CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
  95                                          CF_ACR_EN | CF_ACR_SM_ALL)
  96 #define CFG_SYS_CACHE_ICACR             (CF_CACR_CENB | CF_CACR_CINV | \
  97                                          CF_CACR_DISD | CF_CACR_INVI | \
  98                                          CF_CACR_CEIB | CF_CACR_DCM | \
  99                                          CF_CACR_EUSP)
 100
 101 /*-----------------------------------------------------------------------
 102  * Port configuration
 103  */
 104 #define CFG_SYS_PACNT           0x00000000
 105 #define CFG_SYS_PADDR           0x0000
 106 #define CFG_SYS_PADAT           0x0000
 107 #define CFG_SYS_PBCNT           0x55554155      /* Ethernet/UART configuration */
 108 #define CFG_SYS_PBDDR           0x0000
 109 #define CFG_SYS_PBDAT           0x0000
 110 #define CFG_SYS_PDCNT           0x00000000
 111 #endif                          /* _M5272C3_H */