include/configs/M5272C3.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Motorola MC5272C3 board.
   4  *
   5  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef _M5272C3_H
  13 #define _M5272C3_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19 #define CONFIG_MCFTMR
  20
  21 #define CONFIG_MCFUART
  22 #define CONFIG_SYS_UART_PORT            (0)
  23
  24 #undef CONFIG_WATCHDOG
  25 #define CONFIG_WATCHDOG_TIMEOUT 10000   /* timeout in milliseconds */
  26
  27 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
  28
  29 /* Configuration for environment
  30  * Environment is embedded in u-boot in the second sector of the flash
  31  */
  32 #ifndef CONFIG_MONITOR_IS_IN_RAM
  33 #define CONFIG_ENV_OFFSET               0x4000
  34 #define CONFIG_ENV_SECT_SIZE    0x2000
  35 #else
  36 #define CONFIG_ENV_ADDR         0xffe04000
  37 #define CONFIG_ENV_SECT_SIZE    0x2000
  38 #endif
  39
  40 #define LDS_BOARD_TEXT \
  41         . = DEFINED(env_offset) ? env_offset : .; \
  42         env/embedded.o(.text);
  43
  44 /*
  45  * BOOTP options
  46  */
  47 #define CONFIG_BOOTP_BOOTFILESIZE
  48
  49 /*
  50  * Command line configuration.
  51  */
  52
  53 #define CONFIG_MCFFEC
  54 #ifdef CONFIG_MCFFEC
  55 #       define CONFIG_MII               1
  56 #       define CONFIG_MII_INIT          1
  57 #       define CONFIG_SYS_DISCOVER_PHY
  58 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  59 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  60
  61 #       define CONFIG_SYS_FEC0_PINMUX           0
  62 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  63 #       define MCFFEC_TOUT_LOOP         50000
  64 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  65 #       ifndef CONFIG_SYS_DISCOVER_PHY
  66 #               define FECDUPLEX        FULL
  67 #               define FECSPEED         _100BASET
  68 #       else
  69 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  70 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  71 #               endif
  72 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  73 #endif
  74
  75 #ifdef CONFIG_MCFFEC
  76 #       define CONFIG_IPADDR    192.162.1.2
  77 #       define CONFIG_NETMASK   255.255.255.0
  78 #       define CONFIG_SERVERIP  192.162.1.1
  79 #       define CONFIG_GATEWAYIP 192.162.1.1
  80 #endif                          /* CONFIG_MCFFEC */
  81
  82 #define CONFIG_HOSTNAME         "M5272C3"
  83 #define CONFIG_EXTRA_ENV_SETTINGS               \
  84         "netdev=eth0\0"                         \
  85         "loadaddr=10000\0"                      \
  86         "u-boot=u-boot.bin\0"                   \
  87         "load=tftp ${loadaddr) ${u-boot}\0"     \
  88         "upd=run load; run prog\0"              \
  89         "prog=prot off ffe00000 ffe3ffff;"      \
  90         "era ffe00000 ffe3ffff;"                \
  91         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  92         "save\0"                                \
  93         ""
  94
  95 #define CONFIG_SYS_LOAD_ADDR            0x20000
  96 #define CONFIG_SYS_MEMTEST_START        0x400
  97 #define CONFIG_SYS_MEMTEST_END          0x380000
  98 #define CONFIG_SYS_CLK                  66000000
  99
 100 /*
 101  * Low Level Configuration Settings
 102  * (address mappings, register initial values, etc.)
 103  * You should know what you are doing if you make changes here.
 104  */
 105 #define CONFIG_SYS_MBAR         0x10000000      /* Register Base Addrs */
 106 #define CONFIG_SYS_SCR                  0x0003
 107 #define CONFIG_SYS_SPR                  0xffff
 108
 109 /*-----------------------------------------------------------------------
 110  * Definitions for initial stack pointer and data area (in DPRAM)
 111  */
 112 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 113 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in internal SRAM    */
 114 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 115 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 116
 117 /*-----------------------------------------------------------------------
 118  * Start addresses for the final memory configuration
 119  * (Set up by the startup code)
 120  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 121  */
 122 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 123 #define CONFIG_SYS_SDRAM_SIZE           4       /* SDRAM size in MB */
 124 #define CONFIG_SYS_FLASH_BASE           0xffe00000
 125
 126 #ifdef  CONFIG_MONITOR_IS_IN_RAM
 127 #define CONFIG_SYS_MONITOR_BASE 0x20000
 128 #else
 129 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 130 #endif
 131
 132 #define CONFIG_SYS_MONITOR_LEN          0x20000
 133 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 134 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 135
 136 /*
 137  * For booting Linux, the board info and command line data
 138  * have to be in the first 8 MB of memory, since this is
 139  * the maximum mapped by the Linux kernel during initialization ??
 140  */
 141 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 142
 143 /*
 144  * FLASH organization
 145  */
 146 #define CONFIG_SYS_FLASH_CFI
 147 #ifdef CONFIG_SYS_FLASH_CFI
 148 #       define CONFIG_FLASH_CFI_DRIVER  1
 149 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
 150 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 151 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 152 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 153 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 154 #endif
 155
 156 /*-----------------------------------------------------------------------
 157  * Cache Configuration
 158  */
 159 #define CONFIG_SYS_CACHELINE_SIZE       16
 160
 161 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 162                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 163 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 164                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 165 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 166 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 167                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 168                                          CF_ACR_EN | CF_ACR_SM_ALL)
 169 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 170                                          CF_CACR_DISD | CF_CACR_INVI | \
 171                                          CF_CACR_CEIB | CF_CACR_DCM | \
 172                                          CF_CACR_EUSP)
 173
 174 /*-----------------------------------------------------------------------
 175  * Memory bank definitions
 176  */
 177 #define CONFIG_SYS_BR0_PRELIM           0xFFE00201
 178 #define CONFIG_SYS_OR0_PRELIM           0xFFE00014
 179 #define CONFIG_SYS_BR1_PRELIM           0
 180 #define CONFIG_SYS_OR1_PRELIM           0
 181 #define CONFIG_SYS_BR2_PRELIM           0x30000001
 182 #define CONFIG_SYS_OR2_PRELIM           0xFFF80000
 183 #define CONFIG_SYS_BR3_PRELIM           0
 184 #define CONFIG_SYS_OR3_PRELIM           0
 185 #define CONFIG_SYS_BR4_PRELIM           0
 186 #define CONFIG_SYS_OR4_PRELIM           0
 187 #define CONFIG_SYS_BR5_PRELIM           0
 188 #define CONFIG_SYS_OR5_PRELIM           0
 189 #define CONFIG_SYS_BR6_PRELIM           0
 190 #define CONFIG_SYS_OR6_PRELIM           0
 191 #define CONFIG_SYS_BR7_PRELIM           0x00000701
 192 #define CONFIG_SYS_OR7_PRELIM           0xFFC0007C
 193
 194 /*-----------------------------------------------------------------------
 195  * Port configuration
 196  */
 197 #define CONFIG_SYS_PACNT                0x00000000
 198 #define CONFIG_SYS_PADDR                0x0000
 199 #define CONFIG_SYS_PADAT                0x0000
 200 #define CONFIG_SYS_PBCNT                0x55554155      /* Ethernet/UART configuration */
 201 #define CONFIG_SYS_PBDDR                0x0000
 202 #define CONFIG_SYS_PBDAT                0x0000
 203 #define CONFIG_SYS_PDCNT                0x00000000
 204 #endif                          /* _M5272C3_H */