2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * Hayden Fraser (Hayden.Fraser@freescale.com)
5 * SPDX-License-Identifier: GPL-2.0+
11 #define CONFIG_MCF52x2 /* define processor family */
12 #define CONFIG_M5253 /* define processor type */
13 #define CONFIG_M5253EVBE /* define board type */
17 #define CONFIG_MCFUART
18 #define CONFIG_SYS_UART_PORT (0)
19 #define CONFIG_BAUDRATE 115200
21 #undef CONFIG_WATCHDOG /* disable watchdog */
23 #define CONFIG_BOOTDELAY 5
25 /* Configuration for environment
26 * Environment is embedded in u-boot in the second sector of the flash
28 #ifndef CONFIG_MONITOR_IS_IN_RAM
29 #define CONFIG_ENV_OFFSET 0x4000
30 #define CONFIG_ENV_SECT_SIZE 0x2000
31 #define CONFIG_ENV_IS_IN_FLASH 1
33 #define CONFIG_ENV_ADDR 0xffe04000
34 #define CONFIG_ENV_SECT_SIZE 0x2000
35 #define CONFIG_ENV_IS_IN_FLASH 1
41 #undef CONFIG_BOOTP_BOOTFILESIZE
42 #undef CONFIG_BOOTP_BOOTPATH
43 #undef CONFIG_BOOTP_GATEWAY
44 #undef CONFIG_BOOTP_HOSTNAME
47 * Command line configuration.
49 #include <config_cmd_default.h>
50 #define CONFIG_CMD_CACHE
52 #define CONFIG_CMD_LOADB
53 #define CONFIG_CMD_LOADS
54 #define CONFIG_CMD_EXT2
55 #define CONFIG_CMD_FAT
56 #define CONFIG_CMD_IDE
57 #define CONFIG_CMD_MEMORY
58 #define CONFIG_CMD_MISC
61 #define CONFIG_DOS_PARTITION
62 #define CONFIG_MAC_PARTITION
63 #define CONFIG_IDE_RESET 1
64 #define CONFIG_IDE_PREINIT 1
68 #define CONFIG_SYS_IDE_MAXBUS 1
69 #define CONFIG_SYS_IDE_MAXDEVICE 2
71 #define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
72 #define CONFIG_SYS_ATA_IDE0_OFFSET 0
74 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
75 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
76 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
77 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
79 #define CONFIG_SYS_LONGHELP /* undef to save memory */
81 #if defined(CONFIG_CMD_KGDB)
82 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
84 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
86 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
87 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
88 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
90 #define CONFIG_SYS_LOAD_ADDR 0x00100000
92 #define CONFIG_SYS_MEMTEST_START 0x400
93 #define CONFIG_SYS_MEMTEST_END 0x380000
95 #define CONFIG_SYS_HZ 1000
97 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
98 #define CONFIG_SYS_FAST_CLK
99 #ifdef CONFIG_SYS_FAST_CLK
100 # define CONFIG_SYS_PLLCR 0x1243E054
101 # define CONFIG_SYS_CLK 140000000
103 # define CONFIG_SYS_PLLCR 0x135a4140
104 # define CONFIG_SYS_CLK 70000000
108 * Low Level Configuration Settings
109 * (address mappings, register initial values, etc.)
110 * You should know what you are doing if you make changes here.
113 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
114 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
117 * Definitions for initial stack pointer and data area (in DPRAM)
119 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
120 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
121 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
122 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
125 * Start addresses for the final memory configuration
126 * (Set up by the startup code)
127 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
129 #define CONFIG_SYS_SDRAM_BASE 0x00000000
130 #define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */
132 #ifdef CONFIG_MONITOR_IS_IN_RAM
133 #define CONFIG_SYS_MONITOR_BASE 0x20000
135 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
138 #define CONFIG_SYS_MONITOR_LEN 0x40000
139 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
140 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
143 * For booting Linux, the board info and command line data
144 * have to be in the first 8 MB of memory, since this is
145 * the maximum mapped by the Linux kernel during initialization ??
147 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
148 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
150 /* FLASH organization */
151 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
152 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
153 #define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
154 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
156 #define CONFIG_SYS_FLASH_CFI 1
157 #define CONFIG_FLASH_CFI_DRIVER 1
158 #define CONFIG_SYS_FLASH_SIZE 0x200000
159 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
161 /* Cache Configuration */
162 #define CONFIG_SYS_CACHELINE_SIZE 16
164 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
165 CONFIG_SYS_INIT_RAM_SIZE - 8)
166 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
167 CONFIG_SYS_INIT_RAM_SIZE - 4)
168 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
169 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
171 CF_ACR_EN | CF_ACR_SM_ALL)
172 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
173 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
174 CF_ACR_EN | CF_ACR_SM_ALL)
175 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
178 /* Port configuration */
179 #define CONFIG_SYS_FECI2C 0xF0
181 #define CONFIG_SYS_CS0_BASE 0xFFE00000
182 #define CONFIG_SYS_CS0_MASK 0x001F0021
183 #define CONFIG_SYS_CS0_CTRL 0x00001D80
185 /*-----------------------------------------------------------------------
188 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
189 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
190 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
191 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
192 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
193 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
194 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
196 #endif /* _M5253EVB_H */