1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * Hayden Fraser (Hayden.Fraser@freescale.com)
9 #include <linux/stringify.h>
11 #define CONFIG_SYS_UART_PORT (0)
14 /* Configuration for environment
15 * Environment is embedded in u-boot in the second sector of the flash
18 #define LDS_BOARD_TEXT \
19 . = DEFINED(env_offset) ? env_offset : .; \
20 env/embedded.o(.text*);
24 # define CONFIG_IDE_PREINIT 1
27 #ifdef CONFIG_DRIVER_DM9000
28 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
29 # define DM9000_IO CONFIG_DM9000_BASE
30 # define DM9000_DATA (CONFIG_DM9000_BASE + 4)
31 # undef CONFIG_DM9000_DEBUG
32 # define CONFIG_DM9000_BYTE_SWAPPED
34 # define CONFIG_OVERWRITE_ETHADDR_ONCE
36 # define CONFIG_EXTRA_ENV_SETTINGS \
38 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
40 "u-boot=u-boot.bin\0" \
41 "load=tftp ${loadaddr) ${u-boot}\0" \
42 "upd=run load; run prog\0" \
43 "prog=prot off 0xff800000 0xff82ffff;" \
44 "era 0xff800000 0xff82ffff;" \
45 "cp.b ${loadaddr} 0xff800000 ${filesize};" \
50 #define CONFIG_HOSTNAME "M5253DEMO"
53 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
54 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
55 #define CONFIG_SYS_I2C_PINMUX_SET (0)
57 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
58 #define CONFIG_SYS_FAST_CLK
59 #ifdef CONFIG_SYS_FAST_CLK
60 # define CONFIG_SYS_PLLCR 0x1243E054
61 # define CONFIG_SYS_CLK 140000000
63 # define CONFIG_SYS_PLLCR 0x135a4140
64 # define CONFIG_SYS_CLK 70000000
68 * Low Level Configuration Settings
69 * (address mappings, register initial values, etc.)
70 * You should know what you are doing if you make changes here.
73 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
74 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
77 * Definitions for initial stack pointer and data area (in DPRAM)
79 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
80 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
83 * Start addresses for the final memory configuration
84 * (Set up by the startup code)
85 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
87 #define CONFIG_SYS_SDRAM_BASE 0x00000000
88 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
90 #define CONFIG_SYS_MONITOR_LEN 0x40000
93 * For booting Linux, the board info and command line data
94 * have to be in the first 8 MB of memory, since this is
95 * the maximum mapped by the Linux kernel during initialization ??
97 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
98 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
100 /* FLASH organization */
101 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
102 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
103 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
105 #define FLASH_SST6401B 0x200
106 #define SST_ID_xF6401B 0x236D236D
108 #ifdef CONFIG_SYS_FLASH_CFI
110 * Unable to use CFI driver, due to incompatible sector erase command by SST.
111 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
112 * 0x30 is block erase in SST
114 # define CONFIG_SYS_FLASH_SIZE 0x800000
115 # define CONFIG_FLASH_CFI_LEGACY
117 # define CONFIG_SYS_SST_SECT 2048
118 # define CONFIG_SYS_SST_SECTSZ 0x1000
119 # define CONFIG_SYS_FLASH_WRITE_TOUT 500
122 /* Cache Configuration */
124 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
125 CONFIG_SYS_INIT_RAM_SIZE - 8)
126 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
127 CONFIG_SYS_INIT_RAM_SIZE - 4)
128 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
129 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
131 CF_ACR_EN | CF_ACR_SM_ALL)
132 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
133 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
134 CF_ACR_EN | CF_ACR_SM_ALL)
135 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
138 /* Port configuration */
139 #define CONFIG_SYS_FECI2C 0xF0
141 #define CONFIG_SYS_CS0_BASE 0xFF800000
142 #define CONFIG_SYS_CS0_MASK 0x007F0021
143 #define CONFIG_SYS_CS0_CTRL 0x00001D80
145 #define CONFIG_SYS_CS1_BASE 0xE0000000
146 #define CONFIG_SYS_CS1_MASK 0x00000001
147 #define CONFIG_SYS_CS1_CTRL 0x00003DD8
149 /*-----------------------------------------------------------------------
152 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
153 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
154 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
155 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
156 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
157 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
158 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
160 #endif /* _M5253DEMO_H */