include/configs/M5253DEMO.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  * Hayden Fraser (Hayden.Fraser@freescale.com)
   4  */
   5
   6 #ifndef _M5253DEMO_H
   7 #define _M5253DEMO_H
   8
   9 #include <linux/stringify.h>
  10
  11 #define CONFIG_SYS_UART_PORT            (0)
  12
  13
  14 /* Configuration for environment
  15  * Environment is embedded in u-boot in the second sector of the flash
  16  */
  17
  18 #define LDS_BOARD_TEXT \
  19         . = DEFINED(env_offset) ? env_offset : .; \
  20         env/embedded.o(.text*);
  21
  22 #ifdef CONFIG_DRIVER_DM9000
  23 #       define CONFIG_DM9000_BASE       (CONFIG_SYS_CS1_BASE | 0x300)
  24 #       define DM9000_IO                CONFIG_DM9000_BASE
  25 #       define DM9000_DATA              (CONFIG_DM9000_BASE + 4)
  26 #       undef CONFIG_DM9000_DEBUG
  27 #       define CONFIG_DM9000_BYTE_SWAPPED
  28
  29 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
  30
  31 #       define CONFIG_EXTRA_ENV_SETTINGS                \
  32                 "netdev=eth0\0"                         \
  33                 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  34                 "loadaddr=10000\0"                      \
  35                 "u-boot=u-boot.bin\0"                   \
  36                 "load=tftp ${loadaddr) ${u-boot}\0"     \
  37                 "upd=run load; run prog\0"              \
  38                 "prog=prot off 0xff800000 0xff82ffff;"  \
  39                 "era 0xff800000 0xff82ffff;"            \
  40                 "cp.b ${loadaddr} 0xff800000 ${filesize};"      \
  41                 "save\0"                                \
  42                 ""
  43 #endif
  44
  45 #define CONFIG_HOSTNAME         "M5253DEMO"
  46
  47 /* I2C */
  48 #define CONFIG_SYS_I2C_PINMUX_REG       (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
  49 #define CONFIG_SYS_I2C_PINMUX_CLR       (0xFFFFE7FF)
  50 #define CONFIG_SYS_I2C_PINMUX_SET       (0)
  51
  52 #undef CONFIG_SYS_PLL_BYPASS            /* bypass PLL for test purpose */
  53 #define CONFIG_SYS_FAST_CLK
  54 #ifdef CONFIG_SYS_FAST_CLK
  55 #       define CONFIG_SYS_PLLCR 0x1243E054
  56 #       define CONFIG_SYS_CLK           140000000
  57 #else
  58 #       define CONFIG_SYS_PLLCR 0x135a4140
  59 #       define CONFIG_SYS_CLK           70000000
  60 #endif
  61
  62 /*
  63  * Low Level Configuration Settings
  64  * (address mappings, register initial values, etc.)
  65  * You should know what you are doing if you make changes here.
  66  */
  67
  68 #define CONFIG_SYS_MBAR         0x10000000      /* Register Base Addrs */
  69 #define CONFIG_SYS_MBAR2                0x80000000      /* Module Base Addrs 2 */
  70
  71 /*
  72  * Definitions for initial stack pointer and data area (in DPRAM)
  73  */
  74 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  75 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
  76
  77 /*
  78  * Start addresses for the final memory configuration
  79  * (Set up by the startup code)
  80  * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  81  */
  82 #define CFG_SYS_SDRAM_BASE              0x00000000
  83 #define CFG_SYS_SDRAM_SIZE              16      /* SDRAM size in MB */
  84
  85 /*
  86  * For booting Linux, the board info and command line data
  87  * have to be in the first 8 MB of memory, since this is
  88  * the maximum mapped by the Linux kernel during initialization ??
  89  */
  90 #define CONFIG_SYS_BOOTMAPSZ            (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
  91
  92 /* FLASH organization */
  93 #define CONFIG_SYS_FLASH_BASE           (CONFIG_SYS_CS0_BASE)
  94
  95 #define FLASH_SST6401B          0x200
  96 #define SST_ID_xF6401B          0x236D236D
  97
  98 #ifdef CONFIG_SYS_FLASH_CFI
  99 /*
 100  * Unable to use CFI driver, due to incompatible sector erase command by SST.
 101  * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
 102  * 0x30 is block erase in SST
 103  */
 104 #       define CONFIG_SYS_FLASH_SIZE            0x800000
 105 #else
 106 #       define CONFIG_SYS_SST_SECT              2048
 107 #       define CONFIG_SYS_SST_SECTSZ            0x1000
 108 #endif
 109
 110 /* Cache Configuration */
 111
 112 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 113                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 114 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 115                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 116 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_DCM)
 117 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_FLASH_BASE | \
 118                                          CF_ADDRMASK(8) | \
 119                                          CF_ACR_EN | CF_ACR_SM_ALL)
 120 #define CONFIG_SYS_CACHE_ACR1           (CFG_SYS_SDRAM_BASE | \
 121                                          CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 122                                          CF_ACR_EN | CF_ACR_SM_ALL)
 123 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CEIB | \
 124                                          CF_CACR_DBWE)
 125
 126 #define CONFIG_SYS_CS0_BASE             0xFF800000
 127 #define CONFIG_SYS_CS0_MASK             0x007F0021
 128 #define CONFIG_SYS_CS0_CTRL             0x00001D80
 129
 130 #define CONFIG_SYS_CS1_BASE             0xE0000000
 131 #define CONFIG_SYS_CS1_MASK             0x00000001
 132 #define CONFIG_SYS_CS1_CTRL             0x00003DD8
 133
 134 /*-----------------------------------------------------------------------
 135  * Port configuration
 136  */
 137 #define CONFIG_SYS_GPIO_FUNC            0x00000008      /* Set gpio pins: none */
 138 #define CONFIG_SYS_GPIO1_FUNC           0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54 */
 139 #define CONFIG_SYS_GPIO_EN              0x00000008      /* Set gpio output enable */
 140 #define CONFIG_SYS_GPIO1_EN             0x00c70000      /* Set gpio output enable */
 141 #define CONFIG_SYS_GPIO_OUT             0x00000008      /* Set outputs to default state */
 142 #define CONFIG_SYS_GPIO1_OUT            0x00c70000      /* Set outputs to default state */
 143 #define CONFIG_SYS_GPIO1_LED            0x00400000      /* user led */
 144
 145 #endif                          /* _M5253DEMO_H */