include/configs/M5253DEMO.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  * Hayden Fraser (Hayden.Fraser@freescale.com)
   4  */
   5
   6 #ifndef _M5253DEMO_H
   7 #define _M5253DEMO_H
   8
   9 #include <linux/stringify.h>
  10
  11 #define CFG_SYS_UART_PORT               (0)
  12
  13
  14 /* Configuration for environment
  15  * Environment is embedded in u-boot in the second sector of the flash
  16  */
  17
  18 #define LDS_BOARD_TEXT \
  19         . = DEFINED(env_offset) ? env_offset : .; \
  20         env/embedded.o(.text*);
  21
  22 #ifdef CONFIG_DRIVER_DM9000
  23 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
  24
  25 #       define CONFIG_EXTRA_ENV_SETTINGS                \
  26                 "netdev=eth0\0"                         \
  27                 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  28                 "loadaddr=10000\0"                      \
  29                 "u-boot=u-boot.bin\0"                   \
  30                 "load=tftp ${loadaddr) ${u-boot}\0"     \
  31                 "upd=run load; run prog\0"              \
  32                 "prog=prot off 0xff800000 0xff82ffff;"  \
  33                 "era 0xff800000 0xff82ffff;"            \
  34                 "cp.b ${loadaddr} 0xff800000 ${filesize};"      \
  35                 "save\0"                                \
  36                 ""
  37 #endif
  38
  39 /* I2C */
  40 #define CFG_SYS_I2C_PINMUX_REG  (*(u32 *) (CFG_SYS_MBAR+0x19C))
  41 #define CFG_SYS_I2C_PINMUX_CLR  (0xFFFFE7FF)
  42 #define CFG_SYS_I2C_PINMUX_SET  (0)
  43
  44 #undef CFG_SYS_PLL_BYPASS               /* bypass PLL for test purpose */
  45 #define CFG_SYS_FAST_CLK
  46 #ifdef CFG_SYS_FAST_CLK
  47 #       define CFG_SYS_PLLCR    0x1243E054
  48 #       define CFG_SYS_CLK              140000000
  49 #else
  50 #       define CFG_SYS_PLLCR    0x135a4140
  51 #       define CFG_SYS_CLK              70000000
  52 #endif
  53
  54 /*
  55  * Low Level Configuration Settings
  56  * (address mappings, register initial values, etc.)
  57  * You should know what you are doing if you make changes here.
  58  */
  59
  60 #define CFG_SYS_MBAR            0x10000000      /* Register Base Addrs */
  61 #define CFG_SYS_MBAR2           0x80000000      /* Module Base Addrs 2 */
  62
  63 /*
  64  * Definitions for initial stack pointer and data area (in DPRAM)
  65  */
  66 #define CFG_SYS_INIT_RAM_ADDR   0x20000000
  67 #define CFG_SYS_INIT_RAM_SIZE   0x10000 /* Size of used area in internal SRAM */
  68
  69 /*
  70  * Start addresses for the final memory configuration
  71  * (Set up by the startup code)
  72  * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  73  */
  74 #define CFG_SYS_SDRAM_BASE              0x00000000
  75 #define CFG_SYS_SDRAM_SIZE              16      /* SDRAM size in MB */
  76
  77 /*
  78  * For booting Linux, the board info and command line data
  79  * have to be in the first 8 MB of memory, since this is
  80  * the maximum mapped by the Linux kernel during initialization ??
  81  */
  82 #define CFG_SYS_BOOTMAPSZ               (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
  83
  84 /* FLASH organization */
  85 #define CFG_SYS_FLASH_BASE              (CFG_SYS_CS0_BASE)
  86
  87 #define FLASH_SST6401B          0x200
  88 #define SST_ID_xF6401B          0x236D236D
  89
  90 #ifdef CONFIG_SYS_FLASH_CFI
  91 /*
  92  * Unable to use CFI driver, due to incompatible sector erase command by SST.
  93  * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
  94  * 0x30 is block erase in SST
  95  */
  96 #       define CFG_SYS_FLASH_SIZE               0x800000
  97 #else
  98 #       define CFG_SYS_SST_SECT         2048
  99 #       define CFG_SYS_SST_SECTSZ               0x1000
 100 #endif
 101
 102 /* Cache Configuration */
 103
 104 #define ICACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
 105                                          CFG_SYS_INIT_RAM_SIZE - 8)
 106 #define DCACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
 107                                          CFG_SYS_INIT_RAM_SIZE - 4)
 108 #define CFG_SYS_ICACHE_INV              (CF_CACR_DCM)
 109 #define CFG_SYS_CACHE_ACR0              (CFG_SYS_FLASH_BASE | \
 110                                          CF_ADDRMASK(8) | \
 111                                          CF_ACR_EN | CF_ACR_SM_ALL)
 112 #define CFG_SYS_CACHE_ACR1              (CFG_SYS_SDRAM_BASE | \
 113                                          CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 114                                          CF_ACR_EN | CF_ACR_SM_ALL)
 115 #define CFG_SYS_CACHE_ICACR             (CF_CACR_CENB | CF_CACR_CEIB | \
 116                                          CF_CACR_DBWE)
 117
 118 #define CFG_SYS_CS0_BASE                0xFF800000
 119 #define CFG_SYS_CS0_MASK                0x007F0021
 120 #define CFG_SYS_CS0_CTRL                0x00001D80
 121
 122 #define CFG_SYS_CS1_BASE                0xE0000000
 123 #define CFG_SYS_CS1_MASK                0x00000001
 124 #define CFG_SYS_CS1_CTRL                0x00003DD8
 125
 126 /*-----------------------------------------------------------------------
 127  * Port configuration
 128  */
 129 #define CFG_SYS_GPIO_FUNC               0x00000008      /* Set gpio pins: none */
 130 #define CFG_SYS_GPIO1_FUNC              0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54 */
 131 #define CFG_SYS_GPIO_EN         0x00000008      /* Set gpio output enable */
 132 #define CFG_SYS_GPIO1_EN                0x00c70000      /* Set gpio output enable */
 133 #define CFG_SYS_GPIO_OUT                0x00000008      /* Set outputs to default state */
 134 #define CFG_SYS_GPIO1_OUT               0x00c70000      /* Set outputs to default state */
 135 #define CFG_SYS_GPIO1_LED               0x00400000      /* user led */
 136
 137 #endif                          /* _M5253DEMO_H */