include/configs/M5253DEMO.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  * Hayden Fraser (Hayden.Fraser@freescale.com)
   4  */
   5
   6 #ifndef _M5253DEMO_H
   7 #define _M5253DEMO_H
   8
   9 #include <linux/stringify.h>
  10
  11 #define CONFIG_SYS_UART_PORT            (0)
  12
  13
  14 /* Configuration for environment
  15  * Environment is embedded in u-boot in the second sector of the flash
  16  */
  17
  18 #define LDS_BOARD_TEXT \
  19         . = DEFINED(env_offset) ? env_offset : .; \
  20         env/embedded.o(.text*);
  21
  22 #ifdef CONFIG_IDE
  23 /* ATA */
  24 #       define CONFIG_IDE_PREINIT       1
  25 #       undef CONFIG_LBA48
  26 #endif
  27
  28 #define CONFIG_DRIVER_DM9000
  29 #ifdef CONFIG_DRIVER_DM9000
  30 #       define CONFIG_DM9000_BASE       (CONFIG_SYS_CS1_BASE | 0x300)
  31 #       define DM9000_IO                CONFIG_DM9000_BASE
  32 #       define DM9000_DATA              (CONFIG_DM9000_BASE + 4)
  33 #       undef CONFIG_DM9000_DEBUG
  34 #       define CONFIG_DM9000_BYTE_SWAPPED
  35
  36 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
  37
  38 #       define CONFIG_EXTRA_ENV_SETTINGS                \
  39                 "netdev=eth0\0"                         \
  40                 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  41                 "loadaddr=10000\0"                      \
  42                 "u-boot=u-boot.bin\0"                   \
  43                 "load=tftp ${loadaddr) ${u-boot}\0"     \
  44                 "upd=run load; run prog\0"              \
  45                 "prog=prot off 0xff800000 0xff82ffff;"  \
  46                 "era 0xff800000 0xff82ffff;"            \
  47                 "cp.b ${loadaddr} 0xff800000 ${filesize};"      \
  48                 "save\0"                                \
  49                 ""
  50 #endif
  51
  52 #define CONFIG_HOSTNAME         "M5253DEMO"
  53
  54 /* I2C */
  55 #define CONFIG_SYS_I2C_PINMUX_REG       (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
  56 #define CONFIG_SYS_I2C_PINMUX_CLR       (0xFFFFE7FF)
  57 #define CONFIG_SYS_I2C_PINMUX_SET       (0)
  58
  59 #undef CONFIG_SYS_PLL_BYPASS            /* bypass PLL for test purpose */
  60 #define CONFIG_SYS_FAST_CLK
  61 #ifdef CONFIG_SYS_FAST_CLK
  62 #       define CONFIG_SYS_PLLCR 0x1243E054
  63 #       define CONFIG_SYS_CLK           140000000
  64 #else
  65 #       define CONFIG_SYS_PLLCR 0x135a4140
  66 #       define CONFIG_SYS_CLK           70000000
  67 #endif
  68
  69 /*
  70  * Low Level Configuration Settings
  71  * (address mappings, register initial values, etc.)
  72  * You should know what you are doing if you make changes here.
  73  */
  74
  75 #define CONFIG_SYS_MBAR         0x10000000      /* Register Base Addrs */
  76 #define CONFIG_SYS_MBAR2                0x80000000      /* Module Base Addrs 2 */
  77
  78 /*
  79  * Definitions for initial stack pointer and data area (in DPRAM)
  80  */
  81 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  82 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
  83 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  84 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  85
  86 /*
  87  * Start addresses for the final memory configuration
  88  * (Set up by the startup code)
  89  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  90  */
  91 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  92 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
  93
  94 #define CONFIG_SYS_MONITOR_LEN          0x40000
  95 #define CONFIG_SYS_BOOTPARAMS_LEN       (64*1024)
  96
  97 /*
  98  * For booting Linux, the board info and command line data
  99  * have to be in the first 8 MB of memory, since this is
 100  * the maximum mapped by the Linux kernel during initialization ??
 101  */
 102 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 103 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 104
 105 /* FLASH organization */
 106 #define CONFIG_SYS_FLASH_BASE           (CONFIG_SYS_CS0_BASE)
 107 #define CONFIG_SYS_MAX_FLASH_SECT       2048    /* max number of sectors on one chip */
 108 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
 109
 110 #define FLASH_SST6401B          0x200
 111 #define SST_ID_xF6401B          0x236D236D
 112
 113 #ifdef CONFIG_SYS_FLASH_CFI
 114 /*
 115  * Unable to use CFI driver, due to incompatible sector erase command by SST.
 116  * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
 117  * 0x30 is block erase in SST
 118  */
 119 #       define CONFIG_SYS_FLASH_SIZE            0x800000
 120 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 121 #       define CONFIG_FLASH_CFI_LEGACY
 122 #else
 123 #       define CONFIG_SYS_SST_SECT              2048
 124 #       define CONFIG_SYS_SST_SECTSZ            0x1000
 125 #       define CONFIG_SYS_FLASH_WRITE_TOUT      500
 126 #endif
 127
 128 /* Cache Configuration */
 129
 130 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 131                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 132 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 133                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 134 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_DCM)
 135 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_FLASH_BASE | \
 136                                          CF_ADDRMASK(8) | \
 137                                          CF_ACR_EN | CF_ACR_SM_ALL)
 138 #define CONFIG_SYS_CACHE_ACR1           (CONFIG_SYS_SDRAM_BASE | \
 139                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 140                                          CF_ACR_EN | CF_ACR_SM_ALL)
 141 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CEIB | \
 142                                          CF_CACR_DBWE)
 143
 144 /* Port configuration */
 145 #define CONFIG_SYS_FECI2C               0xF0
 146
 147 #define CONFIG_SYS_CS0_BASE             0xFF800000
 148 #define CONFIG_SYS_CS0_MASK             0x007F0021
 149 #define CONFIG_SYS_CS0_CTRL             0x00001D80
 150
 151 #define CONFIG_SYS_CS1_BASE             0xE0000000
 152 #define CONFIG_SYS_CS1_MASK             0x00000001
 153 #define CONFIG_SYS_CS1_CTRL             0x00003DD8
 154
 155 /*-----------------------------------------------------------------------
 156  * Port configuration
 157  */
 158 #define CONFIG_SYS_GPIO_FUNC            0x00000008      /* Set gpio pins: none */
 159 #define CONFIG_SYS_GPIO1_FUNC           0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54 */
 160 #define CONFIG_SYS_GPIO_EN              0x00000008      /* Set gpio output enable */
 161 #define CONFIG_SYS_GPIO1_EN             0x00c70000      /* Set gpio output enable */
 162 #define CONFIG_SYS_GPIO_OUT             0x00000008      /* Set outputs to default state */
 163 #define CONFIG_SYS_GPIO1_OUT            0x00c70000      /* Set outputs to default state */
 164 #define CONFIG_SYS_GPIO1_LED            0x00400000      /* user led */
 165
 166 #endif                          /* _M5253DEMO_H */