1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_SYS_UART_PORT (0)
23 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
26 # define CONFIG_MII_INIT 1
27 # define CONFIG_SYS_DISCOVER_PHY
28 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
29 # ifndef CONFIG_SYS_DISCOVER_PHY
30 # define FECDUPLEX FULL
31 # define FECSPEED _100BASET
32 # endif /* CONFIG_SYS_DISCOVER_PHY */
39 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
40 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
41 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
43 /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */
45 # define CONFIG_IPADDR 192.162.1.2
46 # define CONFIG_NETMASK 255.255.255.0
47 # define CONFIG_SERVERIP 192.162.1.1
48 # define CONFIG_GATEWAYIP 192.162.1.1
51 #define CONFIG_HOSTNAME "M5235EVB"
52 #define CONFIG_EXTRA_ENV_SETTINGS \
55 "u-boot=u-boot.bin\0" \
56 "load=tftp ${loadaddr) ${u-boot}\0" \
57 "upd=run load; run prog\0" \
58 "prog=prot off ffe00000 ffe3ffff;" \
59 "era ffe00000 ffe3ffff;" \
60 "cp.b ${loadaddr} ffe00000 ${filesize};"\
64 #define CONFIG_PRAM 512 /* 512 KB */
66 #define CONFIG_SYS_CLK 75000000
67 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
69 #define CONFIG_SYS_MBAR 0x40000000
72 * Low Level Configuration Settings
73 * (address mappings, register initial values, etc.)
74 * You should know what you are doing if you make changes here.
76 /*-----------------------------------------------------------------------
77 * Definitions for initial stack pointer and data area (in DPRAM)
79 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
80 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
81 #define CONFIG_SYS_INIT_RAM_CTRL 0x21
82 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
83 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
85 /*-----------------------------------------------------------------------
86 * Start addresses for the final memory configuration
87 * (Set up by the startup code)
88 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
90 #define CONFIG_SYS_SDRAM_BASE 0x00000000
91 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
93 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
94 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
96 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
99 * For booting Linux, the board info and command line data
100 * have to be in the first 8 MB of memory, since this is
101 * the maximum mapped by the Linux kernel during initialization ??
103 /* Initial Memory map for Linux */
104 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
105 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
107 /*-----------------------------------------------------------------------
110 #ifdef CONFIG_SYS_FLASH_CFI
111 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
112 #ifdef NORFLASH_PS32BIT
113 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
115 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
117 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
120 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
122 /* Configuration for environment
123 * Environment is embedded in u-boot in the second sector of the flash
126 #define LDS_BOARD_TEXT \
127 . = DEFINED(env_offset) ? env_offset : .; \
128 env/embedded.o(.text);
130 /*-----------------------------------------------------------------------
131 * Cache Configuration
134 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
135 CONFIG_SYS_INIT_RAM_SIZE - 8)
136 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
137 CONFIG_SYS_INIT_RAM_SIZE - 4)
138 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
139 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
140 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
141 CF_ACR_EN | CF_ACR_SM_ALL)
142 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
143 CF_CACR_CEIB | CF_CACR_DCM | \
146 /*-----------------------------------------------------------------------
147 * Chipselect bank definitions
150 * CS0 - NOR Flash 1, 2, 4, or 8MB
159 #ifdef NORFLASH_PS32BIT
160 # define CONFIG_SYS_CS0_BASE 0xFFC00000
161 # define CONFIG_SYS_CS0_MASK 0x003f0001
162 # define CONFIG_SYS_CS0_CTRL 0x00001D00
164 # define CONFIG_SYS_CS0_BASE 0xFFE00000
165 # define CONFIG_SYS_CS0_MASK 0x001f0001
166 # define CONFIG_SYS_CS0_CTRL 0x00001D80
169 #endif /* _M5329EVB_H */