1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_MCFUART
22 #define CONFIG_SYS_UART_PORT (0)
24 #undef CONFIG_WATCHDOG
25 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
30 #define CONFIG_BOOTP_BOOTFILESIZE
33 # define CONFIG_MII_INIT 1
34 # define CONFIG_SYS_DISCOVER_PHY
35 # define CONFIG_SYS_RX_ETH_BUFFER 8
36 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
37 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
38 # ifndef CONFIG_SYS_DISCOVER_PHY
39 # define FECDUPLEX FULL
40 # define FECSPEED _100BASET
42 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
43 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
45 # endif /* CONFIG_SYS_DISCOVER_PHY */
52 #define CONFIG_SYS_i2C_FSL
53 #define CONFIG_SYS_FSL_I2C_SPEED 80000
54 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
55 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
56 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
57 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
58 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
59 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
61 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
62 #define CONFIG_BOOTFILE "u-boot.bin"
64 # define CONFIG_IPADDR 192.162.1.2
65 # define CONFIG_NETMASK 255.255.255.0
66 # define CONFIG_SERVERIP 192.162.1.1
67 # define CONFIG_GATEWAYIP 192.162.1.1
70 #define CONFIG_HOSTNAME "M5235EVB"
71 #define CONFIG_EXTRA_ENV_SETTINGS \
74 "u-boot=u-boot.bin\0" \
75 "load=tftp ${loadaddr) ${u-boot}\0" \
76 "upd=run load; run prog\0" \
77 "prog=prot off ffe00000 ffe3ffff;" \
78 "era ffe00000 ffe3ffff;" \
79 "cp.b ${loadaddr} ffe00000 ${filesize};"\
83 #define CONFIG_PRAM 512 /* 512 KB */
85 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
87 #define CONFIG_SYS_CLK 75000000
88 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
90 #define CONFIG_SYS_MBAR 0x40000000
93 * Low Level Configuration Settings
94 * (address mappings, register initial values, etc.)
95 * You should know what you are doing if you make changes here.
97 /*-----------------------------------------------------------------------
98 * Definitions for initial stack pointer and data area (in DPRAM)
100 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
101 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
102 #define CONFIG_SYS_INIT_RAM_CTRL 0x21
103 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
104 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
106 /*-----------------------------------------------------------------------
107 * Start addresses for the final memory configuration
108 * (Set up by the startup code)
109 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
111 #define CONFIG_SYS_SDRAM_BASE 0x00000000
112 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
114 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
115 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
117 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
118 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
121 * For booting Linux, the board info and command line data
122 * have to be in the first 8 MB of memory, since this is
123 * the maximum mapped by the Linux kernel during initialization ??
125 /* Initial Memory map for Linux */
126 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
127 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
129 /*-----------------------------------------------------------------------
132 #ifdef CONFIG_SYS_FLASH_CFI
133 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
134 #ifdef NORFLASH_PS32BIT
135 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
137 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
139 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
140 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
143 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
145 /* Configuration for environment
146 * Environment is embedded in u-boot in the second sector of the flash
149 #define LDS_BOARD_TEXT \
150 . = DEFINED(env_offset) ? env_offset : .; \
151 env/embedded.o(.text);
153 /*-----------------------------------------------------------------------
154 * Cache Configuration
156 #define CONFIG_SYS_CACHELINE_SIZE 16
158 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
159 CONFIG_SYS_INIT_RAM_SIZE - 8)
160 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
161 CONFIG_SYS_INIT_RAM_SIZE - 4)
162 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
163 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
164 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
165 CF_ACR_EN | CF_ACR_SM_ALL)
166 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
167 CF_CACR_CEIB | CF_CACR_DCM | \
170 /*-----------------------------------------------------------------------
171 * Chipselect bank definitions
174 * CS0 - NOR Flash 1, 2, 4, or 8MB
183 #ifdef NORFLASH_PS32BIT
184 # define CONFIG_SYS_CS0_BASE 0xFFC00000
185 # define CONFIG_SYS_CS0_MASK 0x003f0001
186 # define CONFIG_SYS_CS0_CTRL 0x00001D00
188 # define CONFIG_SYS_CS0_BASE 0xFFE00000
189 # define CONFIG_SYS_CS0_MASK 0x001f0001
190 # define CONFIG_SYS_CS0_CTRL 0x00001D80
193 #endif /* _M5329EVB_H */