include/configs/M52277EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF52277 EVB board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M52277EVB_H
  15 #define _M52277EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M52277EVB        /* M52277EVB board */
  22
  23 #define CONFIG_MCFUART
  24 #define CONFIG_SYS_UART_PORT            (0)
  25 #define CONFIG_BAUDRATE                 115200
  26
  27 #undef CONFIG_WATCHDOG
  28
  29 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  30
  31 /*
  32  * BOOTP options
  33  */
  34 #define CONFIG_BOOTP_BOOTFILESIZE
  35 #define CONFIG_BOOTP_BOOTPATH
  36 #define CONFIG_BOOTP_GATEWAY
  37 #define CONFIG_BOOTP_HOSTNAME
  38
  39 /* Command line configuration */
  40 #define CONFIG_CMD_DATE
  41 #define CONFIG_CMD_JFFS2
  42 #define CONFIG_CMD_REGINFO
  43 #undef CONFIG_CMD_BMP
  44
  45 #define CONFIG_HOSTNAME                 M52277EVB
  46 #define CONFIG_SYS_UBOOT_END            0x3FFFF
  47 #define CONFIG_SYS_LOAD_ADDR2           0x40010007
  48 #ifdef CONFIG_SYS_STMICRO_BOOT
  49 /* ST Micro serial flash */
  50 #define CONFIG_EXTRA_ENV_SETTINGS               \
  51         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  52         "loadaddr=0x40010000\0"                 \
  53         "uboot=u-boot.bin\0"                    \
  54         "load=loadb ${loadaddr} ${baudrate};"   \
  55         "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"   \
  56         "upd=run load; run prog\0"              \
  57         "prog=sf probe 0:2 10000 1;"            \
  58         "sf erase 0 30000;"                     \
  59         "sf write ${loadaddr} 0 30000;"         \
  60         "save\0"                                \
  61         ""
  62 #endif
  63 #ifdef CONFIG_SYS_SPANSION_BOOT
  64 #define CONFIG_EXTRA_ENV_SETTINGS               \
  65         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  66         "loadaddr=0x40010000\0"                 \
  67         "uboot=u-boot.bin\0"                    \
  68         "load=loadb ${loadaddr} ${baudrate}\0"  \
  69         "upd=run load; run prog\0"              \
  70         "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)     \
  71         " " __stringify(CONFIG_SYS_UBOOT_END) ";"               \
  72         "era " __stringify(CONFIG_SYS_FLASH_BASE) " "           \
  73         __stringify(CONFIG_SYS_UBOOT_END) ";"                   \
  74         "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)  \
  75         " ${filesize}; save\0"                  \
  76         "updsbf=run loadsbf; run progsbf\0"     \
  77         "loadsbf=loadb ${loadaddr} ${baudrate};"        \
  78         "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"   \
  79         "progsbf=sf probe 0:2 10000 1;"         \
  80         "sf erase 0 30000;"                     \
  81         "sf write ${loadaddr} 0 30000;"         \
  82         ""
  83 #endif
  84
  85 /* LCD */
  86 #ifdef CONFIG_CMD_BMP
  87 #define CONFIG_SPLASH_SCREEN
  88 #define CONFIG_LCD_LOGO
  89 #define CONFIG_SHARP_LQ035Q7DH06
  90 #endif
  91
  92 /* USB */
  93 #ifdef CONFIG_CMD_USB
  94 #define CONFIG_USB_EHCI
  95 #define CONFIG_DOS_PARTITION
  96 #define CONFIG_ISO_PARTITION
  97 #define CONFIG_SYS_USB_EHCI_REGS_BASE   0xFC0B0000
  98 #define CONFIG_SYS_USB_EHCI_CPU_INIT
  99 #endif
 100
 101 /* Realtime clock */
 102 #define CONFIG_MCFRTC
 103 #undef RTC_DEBUG
 104 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
 105
 106 /* Timer */
 107 #define CONFIG_MCFTMR
 108 #undef CONFIG_MCFPIT
 109
 110 /* I2c */
 111 #define CONFIG_SYS_I2C
 112 #define CONFIG_SYS_I2C_FSL
 113 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 114 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 115 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
 116 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 117
 118 /* DSPI and Serial Flash */
 119 #define CONFIG_CF_SPI
 120 #define CONFIG_CF_DSPI
 121 #define CONFIG_HARD_SPI
 122 #define CONFIG_SYS_SBFHDR_SIZE          0x7
 123 #ifdef CONFIG_CMD_SPI
 124 #       define CONFIG_SYS_DSPI_CS2
 125
 126 #       define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
 127                                          DSPI_CTAR_PCSSCK_1CLK | \
 128                                          DSPI_CTAR_PASC(0) | \
 129                                          DSPI_CTAR_PDT(0) | \
 130                                          DSPI_CTAR_CSSCK(0) | \
 131                                          DSPI_CTAR_ASC(0) | \
 132                                          DSPI_CTAR_DT(1))
 133 #endif
 134
 135 /* Input, PCI, Flexbus, and VCO */
 136 #define CONFIG_EXTRA_CLOCK
 137
 138 #define CONFIG_SYS_INPUT_CLKSRC 16000000
 139
 140 #define CONFIG_PRAM             2048    /* 2048 KB */
 141
 142 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 143
 144 #if defined(CONFIG_CMD_KGDB)
 145 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 146 #else
 147 #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 148 #endif
 149 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 150 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 151 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 152
 153 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_SDRAM_BASE + 0x10000)
 154
 155 #define CONFIG_SYS_MBAR         0xFC000000
 156
 157 /*
 158  * Low Level Configuration Settings
 159  * (address mappings, register initial values, etc.)
 160  * You should know what you are doing if you make changes here.
 161  */
 162
 163 /*
 164  * Definitions for initial stack pointer and data area (in DPRAM)
 165  */
 166 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 167 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000  /* Size of used area in internal SRAM */
 168 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 169 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 170 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 171 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 172
 173 /*
 174  * Start addresses for the final memory configuration
 175  * (Set up by the startup code)
 176  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 177  */
 178 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 179 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
 180 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 181 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 182 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 183 #define CONFIG_SYS_SDRAM_EMOD           0x81810000
 184 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 185 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0x00
 186
 187 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 188 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 189
 190 #ifdef CONFIG_CF_SBF
 191 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 192 #else
 193 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 194 #endif
 195 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 196 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 197 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 198
 199 /* Initial Memory map for Linux */
 200 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 201 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 202
 203 /*
 204  * Configuration for environment
 205  * Environment is not embedded in u-boot. First time runing may have env
 206  * crc error warning if there is no correct environment on the flash.
 207  */
 208 #ifdef CONFIG_CF_SBF
 209 #       define CONFIG_ENV_IS_IN_SPI_FLASH
 210 #       define CONFIG_ENV_SPI_CS        2
 211 #else
 212 #       define CONFIG_ENV_IS_IN_FLASH   1
 213 #endif
 214 #define CONFIG_ENV_OVERWRITE            1
 215
 216 /*-----------------------------------------------------------------------
 217  * FLASH organization
 218  */
 219 #ifdef CONFIG_SYS_STMICRO_BOOT
 220 #       define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_CS0_BASE
 221 #       define CONFIG_SYS_FLASH0_BASE   CONFIG_SYS_CS0_BASE
 222 #       define CONFIG_ENV_OFFSET        0x30000
 223 #       define CONFIG_ENV_SIZE          0x1000
 224 #       define CONFIG_ENV_SECT_SIZE     0x10000
 225 #endif
 226 #ifdef CONFIG_SYS_SPANSION_BOOT
 227 #       define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_CS0_BASE
 228 #       define CONFIG_SYS_FLASH0_BASE   CONFIG_SYS_CS0_BASE
 229 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 230 #       define CONFIG_ENV_SIZE          0x1000
 231 #       define CONFIG_ENV_SECT_SIZE     0x8000
 232 #endif
 233
 234 #define CONFIG_SYS_FLASH_CFI
 235 #ifdef CONFIG_SYS_FLASH_CFI
 236 #       define CONFIG_FLASH_CFI_DRIVER  1
 237 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 238 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
 239 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 240 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 241 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 242 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 243 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 244 #       define CONFIG_SYS_FLASH_CHECKSUM
 245 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE }
 246 #endif
 247
 248 #define LDS_BOARD_TEXT \
 249         arch/m68k/cpu/mcf5227x/built-in.o   (.text*) \
 250         arch/m68k/lib/built-in.o            (.text*)
 251
 252 /*
 253  * This is setting for JFFS2 support in u-boot.
 254  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 255  */
 256 #ifdef CONFIG_CMD_JFFS2
 257 #       define CONFIG_JFFS2_DEV         "nor0"
 258 #       define CONFIG_JFFS2_PART_SIZE   (0x01000000 - 0x40000)
 259 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
 260 #endif
 261
 262 /*-----------------------------------------------------------------------
 263  * Cache Configuration
 264  */
 265 #define CONFIG_SYS_CACHELINE_SIZE       16
 266
 267 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 268                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 269 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 270                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 271 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 272 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 273                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 274                                          CF_ACR_EN | CF_ACR_SM_ALL)
 275 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 276                                          CF_CACR_DISD | CF_CACR_INVI | \
 277                                          CF_CACR_CEIB | CF_CACR_DCM | \
 278                                          CF_CACR_EUSP)
 279
 280 /*-----------------------------------------------------------------------
 281  * Memory bank definitions
 282  */
 283 /*
 284  * CS0 - NOR Flash
 285  * CS1 - Available
 286  * CS2 - Available
 287  * CS3 - Available
 288  * CS4 - Available
 289  * CS5 - Available
 290  */
 291
 292 #ifdef CONFIG_CF_SBF
 293 #define CONFIG_SYS_CS0_BASE             0x04000000
 294 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 295 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 296 #else
 297 #define CONFIG_SYS_CS0_BASE             0x00000000
 298 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 299 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 300 #endif
 301
 302 #endif                          /* _M52277EVB_H */