include/configs/M52277EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF52277 EVB board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M52277EVB_H
  15 #define _M52277EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21
  22 #define CONFIG_MCFUART
  23 #define CONFIG_SYS_UART_PORT            (0)
  24
  25 #undef CONFIG_WATCHDOG
  26
  27 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  28
  29 /*
  30  * BOOTP options
  31  */
  32 #define CONFIG_BOOTP_BOOTFILESIZE
  33 #define CONFIG_BOOTP_BOOTPATH
  34 #define CONFIG_BOOTP_GATEWAY
  35 #define CONFIG_BOOTP_HOSTNAME
  36
  37 #define CONFIG_HOSTNAME                 M52277EVB
  38 #define CONFIG_SYS_UBOOT_END            0x3FFFF
  39 #define CONFIG_SYS_LOAD_ADDR2           0x40010007
  40 #ifdef CONFIG_SYS_STMICRO_BOOT
  41 /* ST Micro serial flash */
  42 #define CONFIG_EXTRA_ENV_SETTINGS               \
  43         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  44         "loadaddr=0x40010000\0"                 \
  45         "uboot=u-boot.bin\0"                    \
  46         "load=loadb ${loadaddr} ${baudrate};"   \
  47         "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"   \
  48         "upd=run load; run prog\0"              \
  49         "prog=sf probe 0:2 10000 1;"            \
  50         "sf erase 0 30000;"                     \
  51         "sf write ${loadaddr} 0 30000;"         \
  52         "save\0"                                \
  53         ""
  54 #endif
  55 #ifdef CONFIG_SYS_SPANSION_BOOT
  56 #define CONFIG_EXTRA_ENV_SETTINGS               \
  57         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  58         "loadaddr=0x40010000\0"                 \
  59         "uboot=u-boot.bin\0"                    \
  60         "load=loadb ${loadaddr} ${baudrate}\0"  \
  61         "upd=run load; run prog\0"              \
  62         "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)     \
  63         " " __stringify(CONFIG_SYS_UBOOT_END) ";"               \
  64         "era " __stringify(CONFIG_SYS_FLASH_BASE) " "           \
  65         __stringify(CONFIG_SYS_UBOOT_END) ";"                   \
  66         "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)  \
  67         " ${filesize}; save\0"                  \
  68         "updsbf=run loadsbf; run progsbf\0"     \
  69         "loadsbf=loadb ${loadaddr} ${baudrate};"        \
  70         "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"   \
  71         "progsbf=sf probe 0:2 10000 1;"         \
  72         "sf erase 0 30000;"                     \
  73         "sf write ${loadaddr} 0 30000;"         \
  74         ""
  75 #endif
  76
  77 /* LCD */
  78 #ifdef CONFIG_CMD_BMP
  79 #define CONFIG_SPLASH_SCREEN
  80 #define CONFIG_LCD_LOGO
  81 #define CONFIG_SHARP_LQ035Q7DH06
  82 #endif
  83
  84 /* USB */
  85 #ifdef CONFIG_CMD_USB
  86 #define CONFIG_SYS_USB_EHCI_REGS_BASE   0xFC0B0000
  87 #define CONFIG_SYS_USB_EHCI_CPU_INIT
  88 #endif
  89
  90 /* Realtime clock */
  91 #define CONFIG_MCFRTC
  92 #undef RTC_DEBUG
  93 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
  94
  95 /* Timer */
  96 #define CONFIG_MCFTMR
  97 #undef CONFIG_MCFPIT
  98
  99 /* I2c */
 100 #define CONFIG_SYS_I2C
 101 #define CONFIG_SYS_I2C_FSL
 102 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 103 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 104 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
 105 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 106
 107 /* DSPI and Serial Flash */
 108 #define CONFIG_CF_DSPI
 109 #define CONFIG_HARD_SPI
 110 #define CONFIG_SYS_SBFHDR_SIZE          0x7
 111 #ifdef CONFIG_CMD_SPI
 112 #       define CONFIG_SYS_DSPI_CS2
 113
 114 #       define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
 115                                          DSPI_CTAR_PCSSCK_1CLK | \
 116                                          DSPI_CTAR_PASC(0) | \
 117                                          DSPI_CTAR_PDT(0) | \
 118                                          DSPI_CTAR_CSSCK(0) | \
 119                                          DSPI_CTAR_ASC(0) | \
 120                                          DSPI_CTAR_DT(1))
 121 #endif
 122
 123 /* Input, PCI, Flexbus, and VCO */
 124 #define CONFIG_EXTRA_CLOCK
 125
 126 #define CONFIG_SYS_INPUT_CLKSRC 16000000
 127
 128 #define CONFIG_PRAM             2048    /* 2048 KB */
 129
 130 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 131
 132 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_SDRAM_BASE + 0x10000)
 133
 134 #define CONFIG_SYS_MBAR         0xFC000000
 135
 136 /*
 137  * Low Level Configuration Settings
 138  * (address mappings, register initial values, etc.)
 139  * You should know what you are doing if you make changes here.
 140  */
 141
 142 /*
 143  * Definitions for initial stack pointer and data area (in DPRAM)
 144  */
 145 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 146 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000  /* Size of used area in internal SRAM */
 147 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 148 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 149 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 150 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 151
 152 /*
 153  * Start addresses for the final memory configuration
 154  * (Set up by the startup code)
 155  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 156  */
 157 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 158 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
 159 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 160 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 161 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 162 #define CONFIG_SYS_SDRAM_EMOD           0x81810000
 163 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 164 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0x00
 165
 166 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 167 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 168
 169 #ifdef CONFIG_CF_SBF
 170 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 171 #else
 172 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 173 #endif
 174 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 175 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 176 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 177
 178 /* Initial Memory map for Linux */
 179 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 180 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 181
 182 /*
 183  * Configuration for environment
 184  * Environment is not embedded in u-boot. First time runing may have env
 185  * crc error warning if there is no correct environment on the flash.
 186  */
 187 #ifdef CONFIG_CF_SBF
 188 #       define CONFIG_ENV_SPI_CS        2
 189 #endif
 190 #define CONFIG_ENV_OVERWRITE            1
 191
 192 /*-----------------------------------------------------------------------
 193  * FLASH organization
 194  */
 195 #ifdef CONFIG_SYS_STMICRO_BOOT
 196 #       define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_CS0_BASE
 197 #       define CONFIG_SYS_FLASH0_BASE   CONFIG_SYS_CS0_BASE
 198 #       define CONFIG_ENV_OFFSET        0x30000
 199 #       define CONFIG_ENV_SIZE          0x1000
 200 #       define CONFIG_ENV_SECT_SIZE     0x10000
 201 #endif
 202 #ifdef CONFIG_SYS_SPANSION_BOOT
 203 #       define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_CS0_BASE
 204 #       define CONFIG_SYS_FLASH0_BASE   CONFIG_SYS_CS0_BASE
 205 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 206 #       define CONFIG_ENV_SIZE          0x1000
 207 #       define CONFIG_ENV_SECT_SIZE     0x8000
 208 #endif
 209
 210 #define CONFIG_SYS_FLASH_CFI
 211 #ifdef CONFIG_SYS_FLASH_CFI
 212 #       define CONFIG_FLASH_CFI_DRIVER  1
 213 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 214 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
 215 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 216 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 217 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 218 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 219 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 220 #       define CONFIG_SYS_FLASH_CHECKSUM
 221 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE }
 222 #endif
 223
 224 #define LDS_BOARD_TEXT \
 225         arch/m68k/cpu/mcf5227x/built-in.o   (.text*) \
 226         arch/m68k/lib/built-in.o            (.text*)
 227
 228 /*
 229  * This is setting for JFFS2 support in u-boot.
 230  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 231  */
 232 #ifdef CONFIG_CMD_JFFS2
 233 #       define CONFIG_JFFS2_DEV         "nor0"
 234 #       define CONFIG_JFFS2_PART_SIZE   (0x01000000 - 0x40000)
 235 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
 236 #endif
 237
 238 /*-----------------------------------------------------------------------
 239  * Cache Configuration
 240  */
 241 #define CONFIG_SYS_CACHELINE_SIZE       16
 242
 243 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 244                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 245 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 246                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 247 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 248 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 249                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 250                                          CF_ACR_EN | CF_ACR_SM_ALL)
 251 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 252                                          CF_CACR_DISD | CF_CACR_INVI | \
 253                                          CF_CACR_CEIB | CF_CACR_DCM | \
 254                                          CF_CACR_EUSP)
 255
 256 /*-----------------------------------------------------------------------
 257  * Memory bank definitions
 258  */
 259 /*
 260  * CS0 - NOR Flash
 261  * CS1 - Available
 262  * CS2 - Available
 263  * CS3 - Available
 264  * CS4 - Available
 265  * CS5 - Available
 266  */
 267
 268 #ifdef CONFIG_CF_SBF
 269 #define CONFIG_SYS_CS0_BASE             0x04000000
 270 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 271 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 272 #else
 273 #define CONFIG_SYS_CS0_BASE             0x00000000
 274 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 275 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 276 #endif
 277
 278 #endif                          /* _M52277EVB_H */