1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5208EVBe.
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
13 * High Level Configuration Options
16 #define CONFIG_SYS_UART_PORT (0)
18 #define CONFIG_WATCHDOG_TIMEOUT 5000
21 # define CONFIG_MII_INIT 1
22 # define CONFIG_SYS_DISCOVER_PHY
23 # define CONFIG_SYS_RX_ETH_BUFFER 8
24 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
25 # define CONFIG_HAS_ETH1
26 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
27 # ifndef CONFIG_SYS_DISCOVER_PHY
28 # define FECDUPLEX FULL
29 # define FECSPEED _100BASET
31 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
32 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
34 # endif /* CONFIG_SYS_DISCOVER_PHY */
41 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
43 #define CONFIG_UDP_CHECKSUM
46 # define CONFIG_IPADDR 192.162.1.2
47 # define CONFIG_NETMASK 255.255.255.0
48 # define CONFIG_SERVERIP 192.162.1.1
49 # define CONFIG_GATEWAYIP 192.162.1.1
50 #endif /* CONFIG_MCFFEC */
52 #define CONFIG_HOSTNAME "M5208EVBe"
53 #define CONFIG_EXTRA_ENV_SETTINGS \
55 "loadaddr=40010000\0" \
56 "u-boot=u-boot.bin\0" \
57 "load=tftp ${loadaddr) ${u-boot}\0" \
58 "upd=run load; run prog\0" \
59 "prog=prot off 0 3ffff;" \
61 "cp.b ${loadaddr} 0 ${filesize};" \
65 #define CONFIG_PRAM 512 /* 512 KB */
67 #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
68 #define CONFIG_SYS_PLL_ODR 0x36
69 #define CONFIG_SYS_PLL_FDR 0x7D
71 #define CONFIG_SYS_MBAR 0xFC000000
74 * Low Level Configuration Settings
75 * (address mappings, register initial values, etc.)
76 * You should know what you are doing if you make changes here.
78 /* Definitions for initial stack pointer and data area (in DPRAM) */
79 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
80 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
81 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
82 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
83 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
86 * Start addresses for the final memory configuration
87 * (Set up by the startup code)
88 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
90 #define CONFIG_SYS_SDRAM_BASE 0x40000000
91 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
92 #define CONFIG_SYS_SDRAM_CFG1 0x43711630
93 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
94 #define CONFIG_SYS_SDRAM_CTRL 0xE1002000
95 #define CONFIG_SYS_SDRAM_EMOD 0x80010000
96 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
98 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
99 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
101 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
104 * For booting Linux, the board info and command line data
105 * have to be in the first 8 MB of memory, since this is
106 * the maximum mapped by the Linux kernel during initialization ??
108 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
109 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
111 /* FLASH organization */
112 #ifdef CONFIG_SYS_FLASH_CFI
113 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
114 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
115 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
116 # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */
119 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
122 * Configuration for environment
123 * Environment is embedded in u-boot in the second sector of the flash
126 #define LDS_BOARD_TEXT \
127 . = DEFINED(env_offset) ? env_offset : .; \
128 env/embedded.o(.text*);
130 /* Cache Configuration */
132 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
133 CONFIG_SYS_INIT_RAM_SIZE - 8)
134 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
135 CONFIG_SYS_INIT_RAM_SIZE - 4)
136 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
137 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
138 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
139 CF_ACR_EN | CF_ACR_SM_ALL)
140 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
141 CF_CACR_DISD | CF_CACR_INVI | \
142 CF_CACR_CEIB | CF_CACR_DCM | \
145 /* Chipselect bank definitions */
154 #define CONFIG_SYS_CS0_BASE 0
155 #define CONFIG_SYS_CS0_MASK 0x007F0001
156 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
158 #endif /* _M5208EVBE_H */