include/configs/M5208EVBE.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Freescale MCF5208EVBe.
   4  *
   5  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 #ifndef _M5208EVBE_H
  10 #define _M5208EVBE_H
  11
  12 /*
  13  * High Level Configuration Options
  14  * (easy to change)
  15  */
  16 #define CONFIG_SYS_UART_PORT            (0)
  17
  18 #undef CONFIG_WATCHDOG
  19 #define CONFIG_WATCHDOG_TIMEOUT         5000
  20
  21 #ifdef CONFIG_MCFFEC
  22 #       define CONFIG_MII_INIT          1
  23 #       define CONFIG_SYS_DISCOVER_PHY
  24 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  25 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  26 #       define CONFIG_HAS_ETH1
  27 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  28 #       ifndef CONFIG_SYS_DISCOVER_PHY
  29 #               define FECDUPLEX        FULL
  30 #               define FECSPEED         _100BASET
  31 #       else
  32 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  33 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  34 #               endif
  35 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  36 #endif
  37
  38 /* Timer */
  39 #define CONFIG_MCFTMR
  40
  41 /* I2C */
  42 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
  43
  44 #define CONFIG_UDP_CHECKSUM
  45
  46 #ifdef CONFIG_MCFFEC
  47 #       define CONFIG_IPADDR    192.162.1.2
  48 #       define CONFIG_NETMASK   255.255.255.0
  49 #       define CONFIG_SERVERIP  192.162.1.1
  50 #       define CONFIG_GATEWAYIP 192.162.1.1
  51 #endif                          /* CONFIG_MCFFEC */
  52
  53 #define CONFIG_HOSTNAME         "M5208EVBe"
  54 #define CONFIG_EXTRA_ENV_SETTINGS               \
  55         "netdev=eth0\0"                         \
  56         "loadaddr=40010000\0"                   \
  57         "u-boot=u-boot.bin\0"                   \
  58         "load=tftp ${loadaddr) ${u-boot}\0"     \
  59         "upd=run load; run prog\0"              \
  60         "prog=prot off 0 3ffff;"                \
  61         "era 0 3ffff;"                          \
  62         "cp.b ${loadaddr} 0 ${filesize};"       \
  63         "save\0"                                \
  64         ""
  65
  66 #define CONFIG_PRAM             512     /* 512 KB */
  67
  68 #define CONFIG_SYS_CLK          166666666       /* CPU Core Clock */
  69 #define CONFIG_SYS_PLL_ODR      0x36
  70 #define CONFIG_SYS_PLL_FDR      0x7D
  71
  72 #define CONFIG_SYS_MBAR         0xFC000000
  73
  74 /*
  75  * Low Level Configuration Settings
  76  * (address mappings, register initial values, etc.)
  77  * You should know what you are doing if you make changes here.
  78  */
  79 /* Definitions for initial stack pointer and data area (in DPRAM) */
  80 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
  81 #define CONFIG_SYS_INIT_RAM_SIZE                0x4000  /* Size of used area in internal SRAM */
  82 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
  83 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
  84 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  85
  86 /*
  87  * Start addresses for the final memory configuration
  88  * (Set up by the startup code)
  89  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  90  */
  91 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  92 #define CONFIG_SYS_SDRAM_SIZE           32      /* SDRAM size in MB */
  93 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
  94 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
  95 #define CONFIG_SYS_SDRAM_CTRL           0xE1002000
  96 #define CONFIG_SYS_SDRAM_EMOD           0x80010000
  97 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
  98
  99 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
 100 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 101
 102 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 103
 104 /*
 105  * For booting Linux, the board info and command line data
 106  * have to be in the first 8 MB of memory, since this is
 107  * the maximum mapped by the Linux kernel during initialization ??
 108  */
 109 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 110 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 111
 112 /* FLASH organization */
 113 #ifdef CONFIG_SYS_FLASH_CFI
 114 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
 115 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 116 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 117 #       define CONFIG_SYS_MAX_FLASH_SECT        254     /* max number of sectors on one chip */
 118 #endif
 119
 120 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 121
 122 /*
 123  * Configuration for environment
 124  * Environment is embedded in u-boot in the second sector of the flash
 125  */
 126
 127 #define LDS_BOARD_TEXT \
 128         . = DEFINED(env_offset) ? env_offset : .; \
 129         env/embedded.o(.text*);
 130
 131 /* Cache Configuration */
 132
 133 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 134                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 135 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 136                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 137 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 138 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 139                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 140                                          CF_ACR_EN | CF_ACR_SM_ALL)
 141 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 142                                          CF_CACR_DISD | CF_CACR_INVI | \
 143                                          CF_CACR_CEIB | CF_CACR_DCM | \
 144                                          CF_CACR_EUSP)
 145
 146 /* Chipselect bank definitions */
 147 /*
 148  * CS0 - NOR Flash
 149  * CS1 - Available
 150  * CS2 - Available
 151  * CS3 - Available
 152  * CS4 - Available
 153  * CS5 - Available
 154  */
 155 #define CONFIG_SYS_CS0_BASE             0
 156 #define CONFIG_SYS_CS0_MASK             0x007F0001
 157 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 158
 159 #endif                          /* _M5208EVBE_H */