1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5208EVBe.
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
13 * High Level Configuration Options
16 #define CONFIG_SYS_UART_PORT (0)
18 #define CONFIG_WATCHDOG_TIMEOUT 5000
21 # define CONFIG_SYS_DISCOVER_PHY
22 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
23 # ifndef CONFIG_SYS_DISCOVER_PHY
24 # define FECDUPLEX FULL
25 # define FECSPEED _100BASET
26 # endif /* CONFIG_SYS_DISCOVER_PHY */
32 # define CONFIG_IPADDR 192.162.1.2
33 # define CONFIG_NETMASK 255.255.255.0
34 # define CONFIG_SERVERIP 192.162.1.1
35 # define CONFIG_GATEWAYIP 192.162.1.1
36 #endif /* CONFIG_MCFFEC */
38 #define CONFIG_HOSTNAME "M5208EVBe"
39 #define CONFIG_EXTRA_ENV_SETTINGS \
41 "loadaddr=40010000\0" \
42 "u-boot=u-boot.bin\0" \
43 "load=tftp ${loadaddr) ${u-boot}\0" \
44 "upd=run load; run prog\0" \
45 "prog=prot off 0 3ffff;" \
47 "cp.b ${loadaddr} 0 ${filesize};" \
51 #define CONFIG_PRAM 512 /* 512 KB */
53 #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
54 #define CONFIG_SYS_PLL_ODR 0x36
55 #define CONFIG_SYS_PLL_FDR 0x7D
57 #define CONFIG_SYS_MBAR 0xFC000000
60 * Low Level Configuration Settings
61 * (address mappings, register initial values, etc.)
62 * You should know what you are doing if you make changes here.
64 /* Definitions for initial stack pointer and data area (in DPRAM) */
65 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
66 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
67 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
68 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
69 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
72 * Start addresses for the final memory configuration
73 * (Set up by the startup code)
74 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
76 #define CONFIG_SYS_SDRAM_BASE 0x40000000
77 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
78 #define CONFIG_SYS_SDRAM_CFG1 0x43711630
79 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
80 #define CONFIG_SYS_SDRAM_CTRL 0xE1002000
81 #define CONFIG_SYS_SDRAM_EMOD 0x80010000
82 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
84 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
87 * For booting Linux, the board info and command line data
88 * have to be in the first 8 MB of memory, since this is
89 * the maximum mapped by the Linux kernel during initialization ??
91 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
92 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
94 /* FLASH organization */
95 #ifdef CONFIG_SYS_FLASH_CFI
96 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
97 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
98 # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */
101 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
104 * Configuration for environment
105 * Environment is embedded in u-boot in the second sector of the flash
108 #define LDS_BOARD_TEXT \
109 . = DEFINED(env_offset) ? env_offset : .; \
110 env/embedded.o(.text*);
112 /* Cache Configuration */
114 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
115 CONFIG_SYS_INIT_RAM_SIZE - 8)
116 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
117 CONFIG_SYS_INIT_RAM_SIZE - 4)
118 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
119 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
120 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
121 CF_ACR_EN | CF_ACR_SM_ALL)
122 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
123 CF_CACR_DISD | CF_CACR_INVI | \
124 CF_CACR_CEIB | CF_CACR_DCM | \
127 /* Chipselect bank definitions */
136 #define CONFIG_SYS_CS0_BASE 0
137 #define CONFIG_SYS_CS0_MASK 0x007F0001
138 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
140 #endif /* _M5208EVBE_H */