include/configs/M5208EVBE.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Freescale MCF5208EVBe.
   4  *
   5  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 #ifndef _M5208EVBE_H
  10 #define _M5208EVBE_H
  11
  12 /*
  13  * High Level Configuration Options
  14  * (easy to change)
  15  */
  16 #define CONFIG_MCFUART
  17 #define CONFIG_SYS_UART_PORT            (0)
  18
  19 #undef CONFIG_WATCHDOG
  20 #define CONFIG_WATCHDOG_TIMEOUT         5000
  21
  22 #ifdef CONFIG_MCFFEC
  23 #       define CONFIG_MII_INIT          1
  24 #       define CONFIG_SYS_DISCOVER_PHY
  25 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  26 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  27 #       define CONFIG_HAS_ETH1
  28 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  29 #       ifndef CONFIG_SYS_DISCOVER_PHY
  30 #               define FECDUPLEX        FULL
  31 #               define FECSPEED         _100BASET
  32 #       else
  33 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  34 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  35 #               endif
  36 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  37 #endif
  38
  39 /* Timer */
  40 #define CONFIG_MCFTMR
  41
  42 /* I2C */
  43 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
  44
  45 #define CONFIG_UDP_CHECKSUM
  46
  47 #ifdef CONFIG_MCFFEC
  48 #       define CONFIG_IPADDR    192.162.1.2
  49 #       define CONFIG_NETMASK   255.255.255.0
  50 #       define CONFIG_SERVERIP  192.162.1.1
  51 #       define CONFIG_GATEWAYIP 192.162.1.1
  52 #endif                          /* CONFIG_MCFFEC */
  53
  54 #define CONFIG_HOSTNAME         "M5208EVBe"
  55 #define CONFIG_EXTRA_ENV_SETTINGS               \
  56         "netdev=eth0\0"                         \
  57         "loadaddr=40010000\0"                   \
  58         "u-boot=u-boot.bin\0"                   \
  59         "load=tftp ${loadaddr) ${u-boot}\0"     \
  60         "upd=run load; run prog\0"              \
  61         "prog=prot off 0 3ffff;"                \
  62         "era 0 3ffff;"                          \
  63         "cp.b ${loadaddr} 0 ${filesize};"       \
  64         "save\0"                                \
  65         ""
  66
  67 #define CONFIG_PRAM             512     /* 512 KB */
  68
  69 #define CONFIG_SYS_LOAD_ADDR    0x40010000
  70
  71 #define CONFIG_SYS_CLK          166666666       /* CPU Core Clock */
  72 #define CONFIG_SYS_PLL_ODR      0x36
  73 #define CONFIG_SYS_PLL_FDR      0x7D
  74
  75 #define CONFIG_SYS_MBAR         0xFC000000
  76
  77 /*
  78  * Low Level Configuration Settings
  79  * (address mappings, register initial values, etc.)
  80  * You should know what you are doing if you make changes here.
  81  */
  82 /* Definitions for initial stack pointer and data area (in DPRAM) */
  83 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
  84 #define CONFIG_SYS_INIT_RAM_SIZE                0x4000  /* Size of used area in internal SRAM */
  85 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
  86 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
  87 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  88
  89 /*
  90  * Start addresses for the final memory configuration
  91  * (Set up by the startup code)
  92  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  93  */
  94 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  95 #define CONFIG_SYS_SDRAM_SIZE           32      /* SDRAM size in MB */
  96 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
  97 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
  98 #define CONFIG_SYS_SDRAM_CTRL           0xE1002000
  99 #define CONFIG_SYS_SDRAM_EMOD           0x80010000
 100 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 101
 102 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
 103 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 104
 105 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 106 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 107
 108 /*
 109  * For booting Linux, the board info and command line data
 110  * have to be in the first 8 MB of memory, since this is
 111  * the maximum mapped by the Linux kernel during initialization ??
 112  */
 113 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 114 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 115
 116 /* FLASH organization */
 117 #ifdef CONFIG_SYS_FLASH_CFI
 118 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
 119 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 120 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 121 #       define CONFIG_SYS_MAX_FLASH_SECT        254     /* max number of sectors on one chip */
 122 #endif
 123
 124 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 125
 126 /*
 127  * Configuration for environment
 128  * Environment is embedded in u-boot in the second sector of the flash
 129  */
 130
 131 #define LDS_BOARD_TEXT \
 132         . = DEFINED(env_offset) ? env_offset : .; \
 133         env/embedded.o(.text*);
 134
 135 /* Cache Configuration */
 136 #define CONFIG_SYS_CACHELINE_SIZE       16
 137
 138 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 139                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 140 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 141                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 142 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 143 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 144                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 145                                          CF_ACR_EN | CF_ACR_SM_ALL)
 146 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 147                                          CF_CACR_DISD | CF_CACR_INVI | \
 148                                          CF_CACR_CEIB | CF_CACR_DCM | \
 149                                          CF_CACR_EUSP)
 150
 151 /* Chipselect bank definitions */
 152 /*
 153  * CS0 - NOR Flash
 154  * CS1 - Available
 155  * CS2 - Available
 156  * CS3 - Available
 157  * CS4 - Available
 158  * CS5 - Available
 159  */
 160 #define CONFIG_SYS_CS0_BASE             0
 161 #define CONFIG_SYS_CS0_MASK             0x007F0001
 162 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 163
 164 #endif                          /* _M5208EVBE_H */