3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
16 #include <galileo/core.h>
19 #include "../board/evb64260/local.h"
22 * High Level Configuration Options
26 #define CONFIG_EVB64260 1 /* this is an EVB64260 board */
27 #define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */
29 #define CONFIG_SYS_TEXT_BASE 0xfff00000
30 #define CONFIG_SYS_LDSCRIPT "board/evb64260/u-boot.lds"
32 #define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */
34 #undef CONFIG_ECC /* enable ECC support */
35 /* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */
37 /* which initialization functions to call for this board */
38 #define CONFIG_MISC_INIT_R 1
39 #define CONFIG_BOARD_EARLY_INIT_F 1
41 #ifndef CONFIG_EVB64260_750CX
42 #define CONFIG_SYS_BOARD_NAME "EVB64260"
44 #define CONFIG_SYS_BOARD_NAME "EVB64260-750CX"
47 #define CONFIG_SYS_HUSH_PARSER
50 * The following defines let you select what serial you want to use
51 * for your console driver.
54 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
55 * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
58 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
59 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
62 #define CONFIG_MPSC_PORT 0
65 /* define this if you want to enable GT MAC filtering */
66 #define CONFIG_GT_USE_MAC_HASH_TABLE
68 #undef CONFIG_ETHER_PORT_MII /* use RMII */
71 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
73 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
75 #define CONFIG_ZERO_BOOTDELAY_CHECK
77 #undef CONFIG_BOOTARGS
78 #define CONFIG_BOOTCOMMAND \
80 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
81 "ip=$ipaddr:$serverip:$gatewayip:" \
82 "$netmask:$hostname:eth0:none; && " \
85 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
86 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
88 #undef CONFIG_WATCHDOG /* watchdog disabled */
89 #undef CONFIG_ALTIVEC /* undef to disable */
94 #define CONFIG_BOOTP_SUBNETMASK
95 #define CONFIG_BOOTP_GATEWAY
96 #define CONFIG_BOOTP_HOSTNAME
97 #define CONFIG_BOOTP_BOOTPATH
98 #define CONFIG_BOOTP_BOOTFILESIZE
102 * Command line configuration.
104 #include <config_cmd_default.h>
106 #define CONFIG_CMD_ASKENV
110 * Miscellaneous configurable options
112 #define CONFIG_SYS_LONGHELP /* undef to save memory */
113 #if defined(CONFIG_CMD_KGDB)
114 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
116 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
118 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
119 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
120 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
122 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
123 #define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
125 #define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
127 #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
128 #define CONFIG_SYS_BUS_CLK 100000000 /* 100 MHz */
130 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
132 #ifdef CONFIG_EVB64260_750CX
134 #define CONFIG_SYS_BROKEN_CL2
138 * Low Level Configuration Settings
139 * (address mappings, register initial values, etc.)
140 * You should know what you are doing if you make changes here.
143 /*-----------------------------------------------------------------------
144 * Definitions for initial stack pointer and data area
146 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
147 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
148 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
149 #define CONFIG_SYS_INIT_RAM_LOCK
152 /*-----------------------------------------------------------------------
153 * Start addresses for the final memory configuration
154 * (Set up by the startup code)
155 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
157 #define CONFIG_SYS_SDRAM_BASE 0x00000000
158 #define CONFIG_SYS_FLASH_BASE 0xfff00000
159 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
160 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
161 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
162 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
164 /* areas to map different things with the GT in physical space */
165 #define CONFIG_SYS_DRAM_BANKS 4
166 #define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
168 /* What to put in the bats. */
169 #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
171 /* Peripheral Device section */
172 #define CONFIG_SYS_GT_REGS 0xf8000000
173 #define CONFIG_SYS_DEV_BASE 0xfc000000
175 #define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE
176 #define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
177 #define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
178 #define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
180 #define CONFIG_SYS_DEV0_SIZE _8M /* evb64260 sram @ 0xfc00.0000 */
181 #define CONFIG_SYS_DEV1_SIZE _8M /* evb64260 rtc @ 0xfc80.0000 */
182 #define CONFIG_SYS_DEV2_SIZE _16M /* evb64260 duart @ 0xfd00.0000 */
183 #define CONFIG_SYS_DEV3_SIZE _16M /* evb64260 flash @ 0xfe00.0000 */
185 #define CONFIG_SYS_DEV0_PAR 0x20205093
186 #define CONFIG_SYS_DEV1_PAR 0xcfcfffff
187 #define CONFIG_SYS_DEV2_PAR 0xc0059bd4
188 #define CONFIG_SYS_8BIT_BOOT_PAR 0xc00b5e7c
189 #define CONFIG_SYS_32BIT_BOOT_PAR 0xc4a8241c
190 /* c 4 a 8 2 4 1 c */
191 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
192 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
193 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
194 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
196 #if 0 /* Wrong?? NTL */
197 #define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */
198 /* DMAAck[1:0] GNT0[1:0] */
200 #define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */
201 /* REQ0[1:0] GNT0[1:0] */
203 #define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */
204 /* DMAReq[4] DMAAck[4] WDNMI WDE */
205 #if 0 /* Wrong?? NTL */
206 #define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */
207 /* DMAAck[1:0] GNT1[1:0] */
209 #define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */
210 /* GPP[22] (RS232IntB or PCI1Int) */
211 /* GPP[21] (RS323IntA) */
213 /* REQ1[1:0] GNT1[1:0] */
216 #if 0 /* Wrong?? NTL */
217 # define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */
218 /* GPP[27:26] Int[1:0] */
220 # define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */
221 /* GPP[29] (PCI1Int) */
223 /* GPP[27] (PCI0Int) */
224 /* GPP[26] (RtcInt or PCI1Int) */
228 # define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 /* 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
230 #if 0 /* Wrong?? - NTL */
231 # define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6
233 # define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */
238 # define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */
239 /* idmas use buffer 1,1
243 normal load (see also ifdef HVL)
244 standard SDRAM (see also ifdef REG)
245 non staggered refresh */
246 /* 31:26 25 23 20 19 18 16 */
247 /* 110110 00 111 0 0 00 1 */
248 /* refresh_count=0x200
249 phisical interleaving disable
250 virtual interleaving enable */
255 #define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE
256 #define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */
257 #define CONFIG_SYS_INIT_CHAN1
258 #define CONFIG_SYS_INIT_CHAN2
260 #define SRAM_BASE CONFIG_SYS_DEV0_SPACE
261 #define SRAM_SIZE 0x00100000 /* 1 MB of sram */
264 /*-----------------------------------------------------------------------
266 *-----------------------------------------------------------------------
269 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
270 #define PCI_HOST_FORCE 1 /* configure as pci host */
271 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
273 #define CONFIG_PCI /* include pci support */
274 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
275 #define CONFIG_PCI_PNP /* do pci plug-and-play */
277 /* PCI MEMORY MAP section */
278 #define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
279 #define CONFIG_SYS_PCI0_MEM_SIZE _128M
280 #define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
281 #define CONFIG_SYS_PCI1_MEM_SIZE _128M
283 #define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
284 #define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
287 /* PCI I/O MAP section */
288 #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
289 #define CONFIG_SYS_PCI0_IO_SIZE _16M
290 #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
291 #define CONFIG_SYS_PCI1_IO_SIZE _16M
293 #define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
294 #define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
295 #define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
296 #define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
299 * NS16550 Configuration
301 #define CONFIG_SYS_NS16550
303 #define CONFIG_SYS_NS16550_REG_SIZE -4
305 #define CONFIG_SYS_NS16550_CLK 3686400
307 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_DUART_IO + 0)
308 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_DUART_IO + 0x20)
310 /*----------------------------------------------------------------------
311 * Initial BAT mappings
315 * 1) GUARDED and WRITE_THRU not allowed in IBATS
316 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
320 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
321 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
322 #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
323 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
326 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
327 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
328 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
329 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
331 /* PCI0, PCI1 in one BAT */
332 #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
333 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
334 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
335 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
337 /* GT regs, bootrom, all the devices, PCI I/O */
338 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
339 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
340 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
341 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
343 /* I2C speed and slave address (for compatability) defaults */
344 #define CONFIG_SYS_I2C_SPEED 400000
345 #define CONFIG_SYS_I2C_SLAVE 0x7F
347 /* I2C addresses for the two DIMM SPD chips */
348 #ifndef CONFIG_EVB64260_750CX
349 #define DIMM0_I2C_ADDR 0x56
350 #define DIMM1_I2C_ADDR 0x54
351 #else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
352 #define DIMM0_I2C_ADDR 0x54
353 #define DIMM1_I2C_ADDR 0x54
357 * For booting Linux, the board info and command line data
358 * have to be in the first 8 MB of memory, since this is
359 * the maximum mapped by the Linux kernel during initialization.
361 #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
363 /*-----------------------------------------------------------------------
366 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
367 #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
369 #define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
370 #define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */
372 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
373 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
374 #define CONFIG_SYS_FLASH_CFI 1
376 #define CONFIG_ENV_IS_IN_FLASH 1
377 #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
378 #define CONFIG_ENV_SECT_SIZE 0x10000
379 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
381 /*-----------------------------------------------------------------------
382 * Cache Configuration
384 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
385 #if defined(CONFIG_CMD_KGDB)
386 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
389 /*-----------------------------------------------------------------------
390 * L2CR setup -- make sure this is right for your board!
391 * look in include/74xx_7xx.h for the defines used here
394 #define CONFIG_SYS_L2
399 #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
400 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
403 #define L2_ENABLE (L2_INIT | L2CR_L2E)
405 #define CONFIG_SYS_BOARD_ASM_INIT 1
408 #endif /* __CONFIG_H */