include/configs/CPU86.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU               */
  21 #define CONFIG_CPU86            1       /* ...on a CPU86 board  */
  22 #define CONFIG_CPM2             1       /* Has a CPM2 */
  23
  24 #ifdef CONFIG_BOOT_ROM
  25 #define CONFIG_SYS_TEXT_BASE    0xFF800000
  26 #else
  27 #define CONFIG_SYS_TEXT_BASE    0xFF000000
  28 #endif
  29
  30 /*
  31  * select serial console configuration
  32  *
  33  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  34  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  35  * for SCC).
  36  *
  37  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  38  * defined elsewhere (for example, on the cogent platform, there are serial
  39  * ports on the motherboard which are used for the serial console - see
  40  * cogent/cma101/serial.[ch]).
  41  */
  42 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  43 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  44 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  45 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  46
  47 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  48 #define CONFIG_BAUDRATE         230400
  49 #else
  50 #define CONFIG_BAUDRATE         9600
  51 #endif
  52
  53 /*
  54  * select ethernet configuration
  55  *
  56  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  57  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  58  * for FCC)
  59  *
  60  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  61  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  62  */
  63 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  64 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
  65 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  66 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
  67
  68 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
  69
  70 /*
  71  * - Rx-CLK is CLK11
  72  * - Tx-CLK is CLK12
  73  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  74  * - Enable Full Duplex in FSMR
  75  */
  76 # define CONFIG_SYS_CMXFCR_MASK1        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
  77 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
  78 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  79 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  80
  81 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
  82
  83 /*
  84  * - Rx-CLK is CLK13
  85  * - Tx-CLK is CLK14
  86  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  87  * - Enable Full Duplex in FSMR
  88  */
  89 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
  90 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
  91 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  92 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  93
  94 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
  95
  96 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
  97 #define CONFIG_8260_CLKIN       64000000        /* in Hz */
  98
  99 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 100
 101 #define CONFIG_PREBOOT                                                          \
 102         "echo; "                                                                \
 103         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "   \
 104         "echo"
 105
 106 #undef  CONFIG_BOOTARGS
 107 #define CONFIG_BOOTCOMMAND                                                      \
 108         "bootp; "                                                               \
 109         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
 110         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
 111         "bootm"
 112
 113 /*-----------------------------------------------------------------------
 114  * I2C/EEPROM/RTC configuration
 115  */
 116 #define CONFIG_SYS_I2C
 117 #define CONFIG_SYS_I2C_SOFT                     /* I2C bit-banged */
 118 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 119 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 120
 121 /*
 122  * Software (bit-bang) I2C driver configuration
 123  */
 124 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 125 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 126 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 127 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 128 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 129                         else    iop->pdat &= ~0x00010000
 130 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 131                         else    iop->pdat &= ~0x00020000
 132 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 133
 134 #define CONFIG_RTC_PCF8563
 135 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 136
 137 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 138
 139 /*-----------------------------------------------------------------------
 140  * Miscellaneous configuration options
 141  */
 142
 143 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 144 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 145
 146 /*
 147  * BOOTP options
 148  */
 149 #define CONFIG_BOOTP_SUBNETMASK
 150 #define CONFIG_BOOTP_GATEWAY
 151 #define CONFIG_BOOTP_HOSTNAME
 152 #define CONFIG_BOOTP_BOOTPATH
 153 #define CONFIG_BOOTP_BOOTFILESIZE
 154
 155
 156 /*
 157  * Command line configuration.
 158  */
 159 #include <config_cmd_default.h>
 160
 161 #define CONFIG_CMD_BEDBUG
 162 #define CONFIG_CMD_DATE
 163 #define CONFIG_CMD_DHCP
 164 #define CONFIG_CMD_EEPROM
 165 #define CONFIG_CMD_I2C
 166 #define CONFIG_CMD_NFS
 167 #define CONFIG_CMD_SNTP
 168
 169
 170 /*
 171  * Miscellaneous configurable options
 172  */
 173 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 174 #if defined(CONFIG_CMD_KGDB)
 175 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 176 #else
 177 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 178 #endif
 179 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 180 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 181 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 182
 183 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 184 #define CONFIG_SYS_MEMTEST_END  0x0C00000       /* 4 ... 12 MB in DRAM  */
 185
 186 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 187
 188 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100     /* "bad" address                */
 189
 190 /*
 191  * For booting Linux, the board info and command line data
 192  * have to be in the first 8 MB of memory, since this is
 193  * the maximum mapped by the Linux kernel during initialization.
 194  */
 195 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 196
 197 /*-----------------------------------------------------------------------
 198  * Flash configuration
 199  */
 200
 201 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
 202 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
 203 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 204 #define CONFIG_SYS_FLASH_SIZE           0x00800000
 205
 206 /*-----------------------------------------------------------------------
 207  * FLASH organization
 208  */
 209 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks      */
 210 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 211
 212 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 213 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 214
 215 /*-----------------------------------------------------------------------
 216  * Other areas to be mapped
 217  */
 218
 219 /* CS3: Dual ported SRAM */
 220 #define CONFIG_SYS_DPSRAM_BASE          0x40000000
 221 #define CONFIG_SYS_DPSRAM_SIZE          0x00020000
 222
 223 /* CS4: DiskOnChip */
 224 #define CONFIG_SYS_DOC_BASE             0xF4000000
 225 #define CONFIG_SYS_DOC_SIZE             0x00100000
 226
 227 /* CS5: FDC37C78 controller */
 228 #define CONFIG_SYS_FDC37C78_BASE        0xF1000000
 229 #define CONFIG_SYS_FDC37C78_SIZE        0x00100000
 230
 231 /* CS6: Board configuration registers */
 232 #define CONFIG_SYS_BCRS_BASE            0xF2000000
 233 #define CONFIG_SYS_BCRS_SIZE            0x00010000
 234
 235 /* CS7: VME Extended Access Range */
 236 #define CONFIG_SYS_VMEEAR_BASE          0x80000000
 237 #define CONFIG_SYS_VMEEAR_SIZE          0x01000000
 238
 239 /* CS8: VME Standard Access Range */
 240 #define CONFIG_SYS_VMESAR_BASE          0xFE000000
 241 #define CONFIG_SYS_VMESAR_SIZE          0x01000000
 242
 243 /* CS9: VME Short I/O Access Range */
 244 #define CONFIG_SYS_VMESIOAR_BASE        0xFD000000
 245 #define CONFIG_SYS_VMESIOAR_SIZE        0x01000000
 246
 247 /*-----------------------------------------------------------------------
 248  * Hard Reset Configuration Words
 249  *
 250  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 251  * defines for the various registers affected by the HRCW e.g. changing
 252  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 253  */
 254 #if defined(CONFIG_BOOT_ROM)
 255 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 256                                  HRCW_BPS01 | HRCW_CS10PC01)
 257 #else
 258 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
 259 #endif
 260
 261 /* no slaves so just fill with zeros */
 262 #define CONFIG_SYS_HRCW_SLAVE1          0
 263 #define CONFIG_SYS_HRCW_SLAVE2          0
 264 #define CONFIG_SYS_HRCW_SLAVE3          0
 265 #define CONFIG_SYS_HRCW_SLAVE4          0
 266 #define CONFIG_SYS_HRCW_SLAVE5          0
 267 #define CONFIG_SYS_HRCW_SLAVE6          0
 268 #define CONFIG_SYS_HRCW_SLAVE7          0
 269
 270 /*-----------------------------------------------------------------------
 271  * Internal Memory Mapped Register
 272  */
 273 #define CONFIG_SYS_IMMR         0xF0000000
 274
 275 /*-----------------------------------------------------------------------
 276  * Definitions for initial stack pointer and data area (in DPRAM)
 277  */
 278 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 279 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM    */
 280 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 281 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 282
 283 /*-----------------------------------------------------------------------
 284  * Start addresses for the final memory configuration
 285  * (Set up by the startup code)
 286  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 287  *
 288  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
 289  */
 290 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 291 #define CONFIG_SYS_SDRAM_MAX_SIZE       0x08000000      /* max. 128 MB          */
 292 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 293 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 294 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 295
 296 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 297 # define CONFIG_SYS_RAMBOOT
 298 #endif
 299
 300 #if 0
 301 /* environment is in Flash */
 302 #define CONFIG_ENV_IS_IN_FLASH  1
 303 #ifdef CONFIG_BOOT_ROM
 304 # define CONFIG_ENV_ADDR                (CONFIG_SYS_FLASH_BASE+0x70000)
 305 # define CONFIG_ENV_SIZE                0x10000
 306 # define CONFIG_ENV_SECT_SIZE   0x10000
 307 #endif
 308 #else
 309 /* environment is in EEPROM */
 310 #define CONFIG_ENV_IS_IN_EEPROM 1
 311 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58    /* EEPROM X24C16                */
 312 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 313 /* mask of address bits that overflow into the "EEPROM chip address"    */
 314 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 315 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 316 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 317 #define CONFIG_ENV_OFFSET               512
 318 #define CONFIG_ENV_SIZE         (2048 - 512)
 319 #endif
 320
 321 /*-----------------------------------------------------------------------
 322  * Cache Configuration
 323  */
 324 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 325 #if defined(CONFIG_CMD_KGDB)
 326 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 327 #endif
 328
 329 /*-----------------------------------------------------------------------
 330  * HIDx - Hardware Implementation-dependent Registers                    2-11
 331  *-----------------------------------------------------------------------
 332  * HID0 also contains cache control - initially enable both caches and
 333  * invalidate contents, then the final state leaves only the instruction
 334  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 335  * but Soft reset does not.
 336  *
 337  * HID1 has only read-only information - nothing to set.
 338  */
 339 #define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
 340                          HID0_DCI|HID0_IFEM|HID0_ABE)
 341 #define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 342 #define CONFIG_SYS_HID2        0
 343
 344 /*-----------------------------------------------------------------------
 345  * RMR - Reset Mode Register                                     5-5
 346  *-----------------------------------------------------------------------
 347  * turn on Checkstop Reset Enable
 348  */
 349 #define CONFIG_SYS_RMR         RMR_CSRE
 350
 351 /*-----------------------------------------------------------------------
 352  * BCR - Bus Configuration                                       4-25
 353  *-----------------------------------------------------------------------
 354  */
 355 #define BCR_APD01       0x10000000
 356 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 357
 358 /*-----------------------------------------------------------------------
 359  * SIUMCR - SIU Module Configuration                             4-31
 360  *-----------------------------------------------------------------------
 361  */
 362 #define CONFIG_SYS_SIUMCR      (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
 363                          SIUMCR_CS10PC01|SIUMCR_BCTLC10)
 364
 365 /*-----------------------------------------------------------------------
 366  * SYPCR - System Protection Control                             4-35
 367  * SYPCR can only be written once after reset!
 368  *-----------------------------------------------------------------------
 369  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 370  */
 371 #if defined(CONFIG_WATCHDOG)
 372 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 373                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 374 #else
 375 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 376                          SYPCR_SWRI|SYPCR_SWP)
 377 #endif /* CONFIG_WATCHDOG */
 378
 379 /*-----------------------------------------------------------------------
 380  * TMCNTSC - Time Counter Status and Control                     4-40
 381  *-----------------------------------------------------------------------
 382  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 383  * and enable Time Counter
 384  */
 385 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 386
 387 /*-----------------------------------------------------------------------
 388  * PISCR - Periodic Interrupt Status and Control                 4-42
 389  *-----------------------------------------------------------------------
 390  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 391  * Periodic timer
 392  */
 393 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 394
 395 /*-----------------------------------------------------------------------
 396  * SCCR - System Clock Control                                   9-8
 397  *-----------------------------------------------------------------------
 398  * Ensure DFBRG is Divide by 16
 399  */
 400 #define CONFIG_SYS_SCCR        SCCR_DFBRG01
 401
 402 /*-----------------------------------------------------------------------
 403  * RCCR - RISC Controller Configuration                         13-7
 404  *-----------------------------------------------------------------------
 405  */
 406 #define CONFIG_SYS_RCCR        0
 407
 408 #define CONFIG_SYS_MIN_AM_MASK  0xC0000000
 409 /*-----------------------------------------------------------------------
 410  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 411  *-----------------------------------------------------------------------
 412  */
 413 #define CONFIG_SYS_MPTPR       0x1F00
 414
 415 /*-----------------------------------------------------------------------
 416  * PSRT - Refresh Timer Register                                10-16
 417  *-----------------------------------------------------------------------
 418  */
 419 #define CONFIG_SYS_PSRT        0x0f
 420
 421 /*-----------------------------------------------------------------------
 422  * PSRT - SDRAM Mode Register                                   10-10
 423  *-----------------------------------------------------------------------
 424  */
 425
 426         /* SDRAM initialization values for 8-column chips
 427          */
 428 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
 429                          ORxS_BPD_4                     |\
 430                          ORxS_ROWST_PBI0_A9             |\
 431                          ORxS_NUMR_12)
 432
 433 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_SDAM_A13_IS_A5           |\
 434                          PSDMR_BSMA_A14_A16             |\
 435                          PSDMR_SDA10_PBI0_A10           |\
 436                          PSDMR_RFRC_7_CLK               |\
 437                          PSDMR_PRETOACT_2W              |\
 438                          PSDMR_ACTTORW_1W               |\
 439                          PSDMR_LDOTOPRE_1C              |\
 440                          PSDMR_WRC_1C                   |\
 441                          PSDMR_CL_2)
 442
 443         /* SDRAM initialization values for 9-column chips
 444          */
 445 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
 446                          ORxS_BPD_4                     |\
 447                          ORxS_ROWST_PBI0_A7             |\
 448                          ORxS_NUMR_13)
 449
 450 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_SDAM_A14_IS_A5           |\
 451                          PSDMR_BSMA_A13_A15             |\
 452                          PSDMR_SDA10_PBI0_A9            |\
 453                          PSDMR_RFRC_7_CLK               |\
 454                          PSDMR_PRETOACT_2W              |\
 455                          PSDMR_ACTTORW_1W               |\
 456                          PSDMR_LDOTOPRE_1C              |\
 457                          PSDMR_WRC_1C                   |\
 458                          PSDMR_CL_2)
 459
 460 /*
 461  * Init Memory Controller:
 462  *
 463  * Bank Bus     Machine PortSz  Device
 464  * ---- ---     ------- ------  ------
 465  *  0   60x     GPCM    8  bit  Boot ROM
 466  *  1   60x     GPCM    64 bit  FLASH
 467  *  2   60x     SDRAM   64 bit  SDRAM
 468  *
 469  */
 470
 471 #define CONFIG_SYS_MRS_OFFS     0x00000000
 472
 473 #ifdef CONFIG_BOOT_ROM
 474 /* Bank 0 - Boot ROM
 475  */
 476 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 477                          BRx_PS_8                       |\
 478                          BRx_MS_GPCM_P                  |\
 479                          BRx_V)
 480
 481 #define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
 482                          ORxG_CSNT                      |\
 483                          ORxG_ACS_DIV1                  |\
 484                          ORxG_SCY_3_CLK                 |\
 485                          ORxU_EHTR_8IDLE)
 486
 487 /* Bank 1 - FLASH
 488  */
 489 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 490                          BRx_PS_64                      |\
 491                          BRx_MS_GPCM_P                  |\
 492                          BRx_V)
 493
 494 #define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
 495                          ORxG_CSNT                      |\
 496                          ORxG_ACS_DIV1                  |\
 497                          ORxG_SCY_3_CLK                 |\
 498                          ORxU_EHTR_8IDLE)
 499
 500 #else /* CONFIG_BOOT_ROM */
 501 /* Bank 0 - FLASH
 502  */
 503 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 504                          BRx_PS_64                      |\
 505                          BRx_MS_GPCM_P                  |\
 506                          BRx_V)
 507
 508 #define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
 509                          ORxG_CSNT                      |\
 510                          ORxG_ACS_DIV1                  |\
 511                          ORxG_SCY_3_CLK                 |\
 512                          ORxU_EHTR_8IDLE)
 513
 514 /* Bank 1 - Boot ROM
 515  */
 516 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 517                          BRx_PS_8                       |\
 518                          BRx_MS_GPCM_P                  |\
 519                          BRx_V)
 520
 521 #define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
 522                          ORxG_CSNT                      |\
 523                          ORxG_ACS_DIV1                  |\
 524                          ORxG_SCY_3_CLK                 |\
 525                          ORxU_EHTR_8IDLE)
 526
 527 #endif /* CONFIG_BOOT_ROM */
 528
 529
 530 /* Bank 2 - 60x bus SDRAM
 531  */
 532 #ifndef CONFIG_SYS_RAMBOOT
 533 #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 534                          BRx_PS_64                      |\
 535                          BRx_MS_SDRAM_P                 |\
 536                          BRx_V)
 537
 538 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_9COL
 539
 540 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_9COL
 541 #endif /* CONFIG_SYS_RAMBOOT */
 542
 543 /* Bank 3 - Dual Ported SRAM
 544  */
 545 #define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
 546                          BRx_PS_16                      |\
 547                          BRx_MS_GPCM_P                  |\
 548                          BRx_V)
 549
 550 #define CONFIG_SYS_OR3_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)    |\
 551                          ORxG_CSNT                      |\
 552                          ORxG_ACS_DIV1                  |\
 553                          ORxG_SCY_5_CLK                 |\
 554                          ORxG_SETA)
 555
 556 /* Bank 4 - DiskOnChip
 557  */
 558 #define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)    |\
 559                          BRx_PS_8                       |\
 560                          BRx_MS_GPCM_P                  |\
 561                          BRx_V)
 562
 563 #define CONFIG_SYS_OR4_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)       |\
 564                          ORxG_ACS_DIV2                  |\
 565                          ORxG_SCY_5_CLK                 |\
 566                          ORxU_EHTR_8IDLE)
 567
 568 /* Bank 5 - FDC37C78 controller
 569  */
 570 #define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
 571                          BRx_PS_8                         |\
 572                          BRx_MS_GPCM_P                    |\
 573                          BRx_V)
 574
 575 #define CONFIG_SYS_OR5_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)    |\
 576                          ORxG_ACS_DIV2                    |\
 577                          ORxG_SCY_8_CLK                   |\
 578                          ORxU_EHTR_8IDLE)
 579
 580 /* Bank 6 - Board control registers
 581  */
 582 #define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)   |\
 583                          BRx_PS_8                       |\
 584                          BRx_MS_GPCM_P                  |\
 585                          BRx_V)
 586
 587 #define CONFIG_SYS_OR6_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)      |\
 588                          ORxG_CSNT                      |\
 589                          ORxG_SCY_5_CLK)
 590
 591 /* Bank 7 - VME Extended Access Range
 592  */
 593 #define CONFIG_SYS_BR7_PRELIM  ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
 594                          BRx_PS_32                      |\
 595                          BRx_MS_GPCM_P                  |\
 596                          BRx_V)
 597
 598 #define CONFIG_SYS_OR7_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)    |\
 599                          ORxG_CSNT                      |\
 600                          ORxG_ACS_DIV1                  |\
 601                          ORxG_SCY_5_CLK                 |\
 602                          ORxG_SETA)
 603
 604 /* Bank 8 - VME Standard Access Range
 605  */
 606 #define CONFIG_SYS_BR8_PRELIM  ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
 607                          BRx_PS_16                      |\
 608                          BRx_MS_GPCM_P                  |\
 609                          BRx_V)
 610
 611 #define CONFIG_SYS_OR8_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)    |\
 612                          ORxG_CSNT                      |\
 613                          ORxG_ACS_DIV1                  |\
 614                          ORxG_SCY_5_CLK                 |\
 615                          ORxG_SETA)
 616
 617 /* Bank 9 - VME Short I/O Access Range
 618  */
 619 #define CONFIG_SYS_BR9_PRELIM  ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
 620                          BRx_PS_16                        |\
 621                          BRx_MS_GPCM_P                    |\
 622                          BRx_V)
 623
 624 #define CONFIG_SYS_OR9_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)    |\
 625                          ORxG_CSNT                        |\
 626                          ORxG_ACS_DIV1                    |\
 627                          ORxG_SCY_5_CLK                   |\
 628                          ORxG_SETA)
 629
 630 #endif  /* __CONFIG_H */