include/configs/CPU86.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU               */
  21 #define CONFIG_CPU86            1       /* ...on a CPU86 board  */
  22 #define CONFIG_CPM2             1       /* Has a CPM2 */
  23
  24 #ifdef CONFIG_BOOT_ROM
  25 #define CONFIG_SYS_TEXT_BASE    0xFF800000
  26 #else
  27 #define CONFIG_SYS_TEXT_BASE    0xFF000000
  28 #endif
  29
  30 /*
  31  * select serial console configuration
  32  *
  33  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  34  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  35  * for SCC).
  36  *
  37  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  38  * defined elsewhere (for example, on the cogent platform, there are serial
  39  * ports on the motherboard which are used for the serial console - see
  40  * cogent/cma101/serial.[ch]).
  41  */
  42 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  43 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  44 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  45 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  46
  47 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  48 #define CONFIG_BAUDRATE         230400
  49 #else
  50 #define CONFIG_BAUDRATE         9600
  51 #endif
  52
  53 /*
  54  * select ethernet configuration
  55  *
  56  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  57  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  58  * for FCC)
  59  *
  60  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  61  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  62  */
  63 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  64 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
  65 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  66 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
  67
  68 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
  69
  70 /*
  71  * - Rx-CLK is CLK11
  72  * - Tx-CLK is CLK12
  73  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  74  * - Enable Full Duplex in FSMR
  75  */
  76 # define CONFIG_SYS_CMXFCR_MASK1        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
  77 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
  78 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  79 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  80
  81 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
  82
  83 /*
  84  * - Rx-CLK is CLK13
  85  * - Tx-CLK is CLK14
  86  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  87  * - Enable Full Duplex in FSMR
  88  */
  89 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
  90 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
  91 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  92 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  93
  94 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
  95
  96 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
  97 #define CONFIG_8260_CLKIN       64000000        /* in Hz */
  98
  99 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 100
 101 #define CONFIG_PREBOOT                                                          \
 102         "echo; "                                                                \
 103         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "   \
 104         "echo"
 105
 106 #undef  CONFIG_BOOTARGS
 107 #define CONFIG_BOOTCOMMAND                                                      \
 108         "bootp; "                                                               \
 109         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
 110         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
 111         "bootm"
 112
 113 /*-----------------------------------------------------------------------
 114  * I2C/EEPROM/RTC configuration
 115  */
 116 #define CONFIG_SOFT_I2C                 /* Software I2C support enabled */
 117
 118 # define CONFIG_SYS_I2C_SPEED           50000
 119 # define CONFIG_SYS_I2C_SLAVE           0xFE
 120 /*
 121  * Software (bit-bang) I2C driver configuration
 122  */
 123 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 124 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 125 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 126 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 127 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 128                         else    iop->pdat &= ~0x00010000
 129 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 130                         else    iop->pdat &= ~0x00020000
 131 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 132
 133 #define CONFIG_RTC_PCF8563
 134 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 135
 136 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 137
 138 /*-----------------------------------------------------------------------
 139  * Miscellaneous configuration options
 140  */
 141
 142 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 143 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 144
 145 /*
 146  * BOOTP options
 147  */
 148 #define CONFIG_BOOTP_SUBNETMASK
 149 #define CONFIG_BOOTP_GATEWAY
 150 #define CONFIG_BOOTP_HOSTNAME
 151 #define CONFIG_BOOTP_BOOTPATH
 152 #define CONFIG_BOOTP_BOOTFILESIZE
 153
 154
 155 /*
 156  * Command line configuration.
 157  */
 158 #include <config_cmd_default.h>
 159
 160 #define CONFIG_CMD_BEDBUG
 161 #define CONFIG_CMD_DATE
 162 #define CONFIG_CMD_DHCP
 163 #define CONFIG_CMD_EEPROM
 164 #define CONFIG_CMD_I2C
 165 #define CONFIG_CMD_NFS
 166 #define CONFIG_CMD_SNTP
 167
 168
 169 /*
 170  * Miscellaneous configurable options
 171  */
 172 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 173 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 174 #if defined(CONFIG_CMD_KGDB)
 175 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 176 #else
 177 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 178 #endif
 179 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 180 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 181 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 182
 183 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 184 #define CONFIG_SYS_MEMTEST_END  0x0C00000       /* 4 ... 12 MB in DRAM  */
 185
 186 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 187
 188 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 189
 190 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100     /* "bad" address                */
 191
 192 /*
 193  * For booting Linux, the board info and command line data
 194  * have to be in the first 8 MB of memory, since this is
 195  * the maximum mapped by the Linux kernel during initialization.
 196  */
 197 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 198
 199 /*-----------------------------------------------------------------------
 200  * Flash configuration
 201  */
 202
 203 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
 204 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
 205 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 206 #define CONFIG_SYS_FLASH_SIZE           0x00800000
 207
 208 /*-----------------------------------------------------------------------
 209  * FLASH organization
 210  */
 211 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks      */
 212 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 213
 214 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 215 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 216
 217 /*-----------------------------------------------------------------------
 218  * Other areas to be mapped
 219  */
 220
 221 /* CS3: Dual ported SRAM */
 222 #define CONFIG_SYS_DPSRAM_BASE          0x40000000
 223 #define CONFIG_SYS_DPSRAM_SIZE          0x00020000
 224
 225 /* CS4: DiskOnChip */
 226 #define CONFIG_SYS_DOC_BASE             0xF4000000
 227 #define CONFIG_SYS_DOC_SIZE             0x00100000
 228
 229 /* CS5: FDC37C78 controller */
 230 #define CONFIG_SYS_FDC37C78_BASE        0xF1000000
 231 #define CONFIG_SYS_FDC37C78_SIZE        0x00100000
 232
 233 /* CS6: Board configuration registers */
 234 #define CONFIG_SYS_BCRS_BASE            0xF2000000
 235 #define CONFIG_SYS_BCRS_SIZE            0x00010000
 236
 237 /* CS7: VME Extended Access Range */
 238 #define CONFIG_SYS_VMEEAR_BASE          0x80000000
 239 #define CONFIG_SYS_VMEEAR_SIZE          0x01000000
 240
 241 /* CS8: VME Standard Access Range */
 242 #define CONFIG_SYS_VMESAR_BASE          0xFE000000
 243 #define CONFIG_SYS_VMESAR_SIZE          0x01000000
 244
 245 /* CS9: VME Short I/O Access Range */
 246 #define CONFIG_SYS_VMESIOAR_BASE        0xFD000000
 247 #define CONFIG_SYS_VMESIOAR_SIZE        0x01000000
 248
 249 /*-----------------------------------------------------------------------
 250  * Hard Reset Configuration Words
 251  *
 252  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 253  * defines for the various registers affected by the HRCW e.g. changing
 254  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 255  */
 256 #if defined(CONFIG_BOOT_ROM)
 257 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 258                                  HRCW_BPS01 | HRCW_CS10PC01)
 259 #else
 260 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
 261 #endif
 262
 263 /* no slaves so just fill with zeros */
 264 #define CONFIG_SYS_HRCW_SLAVE1          0
 265 #define CONFIG_SYS_HRCW_SLAVE2          0
 266 #define CONFIG_SYS_HRCW_SLAVE3          0
 267 #define CONFIG_SYS_HRCW_SLAVE4          0
 268 #define CONFIG_SYS_HRCW_SLAVE5          0
 269 #define CONFIG_SYS_HRCW_SLAVE6          0
 270 #define CONFIG_SYS_HRCW_SLAVE7          0
 271
 272 /*-----------------------------------------------------------------------
 273  * Internal Memory Mapped Register
 274  */
 275 #define CONFIG_SYS_IMMR         0xF0000000
 276
 277 /*-----------------------------------------------------------------------
 278  * Definitions for initial stack pointer and data area (in DPRAM)
 279  */
 280 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 281 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM    */
 282 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 283 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 284
 285 /*-----------------------------------------------------------------------
 286  * Start addresses for the final memory configuration
 287  * (Set up by the startup code)
 288  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 289  *
 290  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
 291  */
 292 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 293 #define CONFIG_SYS_SDRAM_MAX_SIZE       0x08000000      /* max. 128 MB          */
 294 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 295 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 296 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 297
 298 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 299 # define CONFIG_SYS_RAMBOOT
 300 #endif
 301
 302 #if 0
 303 /* environment is in Flash */
 304 #define CONFIG_ENV_IS_IN_FLASH  1
 305 #ifdef CONFIG_BOOT_ROM
 306 # define CONFIG_ENV_ADDR                (CONFIG_SYS_FLASH_BASE+0x70000)
 307 # define CONFIG_ENV_SIZE                0x10000
 308 # define CONFIG_ENV_SECT_SIZE   0x10000
 309 #endif
 310 #else
 311 /* environment is in EEPROM */
 312 #define CONFIG_ENV_IS_IN_EEPROM 1
 313 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58    /* EEPROM X24C16                */
 314 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 315 /* mask of address bits that overflow into the "EEPROM chip address"    */
 316 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 317 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 318 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 319 #define CONFIG_ENV_OFFSET               512
 320 #define CONFIG_ENV_SIZE         (2048 - 512)
 321 #endif
 322
 323 /*-----------------------------------------------------------------------
 324  * Cache Configuration
 325  */
 326 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 327 #if defined(CONFIG_CMD_KGDB)
 328 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 329 #endif
 330
 331 /*-----------------------------------------------------------------------
 332  * HIDx - Hardware Implementation-dependent Registers                    2-11
 333  *-----------------------------------------------------------------------
 334  * HID0 also contains cache control - initially enable both caches and
 335  * invalidate contents, then the final state leaves only the instruction
 336  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 337  * but Soft reset does not.
 338  *
 339  * HID1 has only read-only information - nothing to set.
 340  */
 341 #define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
 342                          HID0_DCI|HID0_IFEM|HID0_ABE)
 343 #define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 344 #define CONFIG_SYS_HID2        0
 345
 346 /*-----------------------------------------------------------------------
 347  * RMR - Reset Mode Register                                     5-5
 348  *-----------------------------------------------------------------------
 349  * turn on Checkstop Reset Enable
 350  */
 351 #define CONFIG_SYS_RMR         RMR_CSRE
 352
 353 /*-----------------------------------------------------------------------
 354  * BCR - Bus Configuration                                       4-25
 355  *-----------------------------------------------------------------------
 356  */
 357 #define BCR_APD01       0x10000000
 358 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 359
 360 /*-----------------------------------------------------------------------
 361  * SIUMCR - SIU Module Configuration                             4-31
 362  *-----------------------------------------------------------------------
 363  */
 364 #define CONFIG_SYS_SIUMCR      (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
 365                          SIUMCR_CS10PC01|SIUMCR_BCTLC10)
 366
 367 /*-----------------------------------------------------------------------
 368  * SYPCR - System Protection Control                             4-35
 369  * SYPCR can only be written once after reset!
 370  *-----------------------------------------------------------------------
 371  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 372  */
 373 #if defined(CONFIG_WATCHDOG)
 374 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 375                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 376 #else
 377 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 378                          SYPCR_SWRI|SYPCR_SWP)
 379 #endif /* CONFIG_WATCHDOG */
 380
 381 /*-----------------------------------------------------------------------
 382  * TMCNTSC - Time Counter Status and Control                     4-40
 383  *-----------------------------------------------------------------------
 384  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 385  * and enable Time Counter
 386  */
 387 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 388
 389 /*-----------------------------------------------------------------------
 390  * PISCR - Periodic Interrupt Status and Control                 4-42
 391  *-----------------------------------------------------------------------
 392  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 393  * Periodic timer
 394  */
 395 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 396
 397 /*-----------------------------------------------------------------------
 398  * SCCR - System Clock Control                                   9-8
 399  *-----------------------------------------------------------------------
 400  * Ensure DFBRG is Divide by 16
 401  */
 402 #define CONFIG_SYS_SCCR        SCCR_DFBRG01
 403
 404 /*-----------------------------------------------------------------------
 405  * RCCR - RISC Controller Configuration                         13-7
 406  *-----------------------------------------------------------------------
 407  */
 408 #define CONFIG_SYS_RCCR        0
 409
 410 #define CONFIG_SYS_MIN_AM_MASK  0xC0000000
 411 /*-----------------------------------------------------------------------
 412  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 413  *-----------------------------------------------------------------------
 414  */
 415 #define CONFIG_SYS_MPTPR       0x1F00
 416
 417 /*-----------------------------------------------------------------------
 418  * PSRT - Refresh Timer Register                                10-16
 419  *-----------------------------------------------------------------------
 420  */
 421 #define CONFIG_SYS_PSRT        0x0f
 422
 423 /*-----------------------------------------------------------------------
 424  * PSRT - SDRAM Mode Register                                   10-10
 425  *-----------------------------------------------------------------------
 426  */
 427
 428         /* SDRAM initialization values for 8-column chips
 429          */
 430 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
 431                          ORxS_BPD_4                     |\
 432                          ORxS_ROWST_PBI0_A9             |\
 433                          ORxS_NUMR_12)
 434
 435 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_SDAM_A13_IS_A5           |\
 436                          PSDMR_BSMA_A14_A16             |\
 437                          PSDMR_SDA10_PBI0_A10           |\
 438                          PSDMR_RFRC_7_CLK               |\
 439                          PSDMR_PRETOACT_2W              |\
 440                          PSDMR_ACTTORW_1W               |\
 441                          PSDMR_LDOTOPRE_1C              |\
 442                          PSDMR_WRC_1C                   |\
 443                          PSDMR_CL_2)
 444
 445         /* SDRAM initialization values for 9-column chips
 446          */
 447 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
 448                          ORxS_BPD_4                     |\
 449                          ORxS_ROWST_PBI0_A7             |\
 450                          ORxS_NUMR_13)
 451
 452 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_SDAM_A14_IS_A5           |\
 453                          PSDMR_BSMA_A13_A15             |\
 454                          PSDMR_SDA10_PBI0_A9            |\
 455                          PSDMR_RFRC_7_CLK               |\
 456                          PSDMR_PRETOACT_2W              |\
 457                          PSDMR_ACTTORW_1W               |\
 458                          PSDMR_LDOTOPRE_1C              |\
 459                          PSDMR_WRC_1C                   |\
 460                          PSDMR_CL_2)
 461
 462 /*
 463  * Init Memory Controller:
 464  *
 465  * Bank Bus     Machine PortSz  Device
 466  * ---- ---     ------- ------  ------
 467  *  0   60x     GPCM    8  bit  Boot ROM
 468  *  1   60x     GPCM    64 bit  FLASH
 469  *  2   60x     SDRAM   64 bit  SDRAM
 470  *
 471  */
 472
 473 #define CONFIG_SYS_MRS_OFFS     0x00000000
 474
 475 #ifdef CONFIG_BOOT_ROM
 476 /* Bank 0 - Boot ROM
 477  */
 478 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 479                          BRx_PS_8                       |\
 480                          BRx_MS_GPCM_P                  |\
 481                          BRx_V)
 482
 483 #define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
 484                          ORxG_CSNT                      |\
 485                          ORxG_ACS_DIV1                  |\
 486                          ORxG_SCY_3_CLK                 |\
 487                          ORxU_EHTR_8IDLE)
 488
 489 /* Bank 1 - FLASH
 490  */
 491 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 492                          BRx_PS_64                      |\
 493                          BRx_MS_GPCM_P                  |\
 494                          BRx_V)
 495
 496 #define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
 497                          ORxG_CSNT                      |\
 498                          ORxG_ACS_DIV1                  |\
 499                          ORxG_SCY_3_CLK                 |\
 500                          ORxU_EHTR_8IDLE)
 501
 502 #else /* CONFIG_BOOT_ROM */
 503 /* Bank 0 - FLASH
 504  */
 505 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 506                          BRx_PS_64                      |\
 507                          BRx_MS_GPCM_P                  |\
 508                          BRx_V)
 509
 510 #define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
 511                          ORxG_CSNT                      |\
 512                          ORxG_ACS_DIV1                  |\
 513                          ORxG_SCY_3_CLK                 |\
 514                          ORxU_EHTR_8IDLE)
 515
 516 /* Bank 1 - Boot ROM
 517  */
 518 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 519                          BRx_PS_8                       |\
 520                          BRx_MS_GPCM_P                  |\
 521                          BRx_V)
 522
 523 #define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
 524                          ORxG_CSNT                      |\
 525                          ORxG_ACS_DIV1                  |\
 526                          ORxG_SCY_3_CLK                 |\
 527                          ORxU_EHTR_8IDLE)
 528
 529 #endif /* CONFIG_BOOT_ROM */
 530
 531
 532 /* Bank 2 - 60x bus SDRAM
 533  */
 534 #ifndef CONFIG_SYS_RAMBOOT
 535 #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 536                          BRx_PS_64                      |\
 537                          BRx_MS_SDRAM_P                 |\
 538                          BRx_V)
 539
 540 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_9COL
 541
 542 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_9COL
 543 #endif /* CONFIG_SYS_RAMBOOT */
 544
 545 /* Bank 3 - Dual Ported SRAM
 546  */
 547 #define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
 548                          BRx_PS_16                      |\
 549                          BRx_MS_GPCM_P                  |\
 550                          BRx_V)
 551
 552 #define CONFIG_SYS_OR3_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)    |\
 553                          ORxG_CSNT                      |\
 554                          ORxG_ACS_DIV1                  |\
 555                          ORxG_SCY_5_CLK                 |\
 556                          ORxG_SETA)
 557
 558 /* Bank 4 - DiskOnChip
 559  */
 560 #define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)    |\
 561                          BRx_PS_8                       |\
 562                          BRx_MS_GPCM_P                  |\
 563                          BRx_V)
 564
 565 #define CONFIG_SYS_OR4_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)       |\
 566                          ORxG_ACS_DIV2                  |\
 567                          ORxG_SCY_5_CLK                 |\
 568                          ORxU_EHTR_8IDLE)
 569
 570 /* Bank 5 - FDC37C78 controller
 571  */
 572 #define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
 573                          BRx_PS_8                         |\
 574                          BRx_MS_GPCM_P                    |\
 575                          BRx_V)
 576
 577 #define CONFIG_SYS_OR5_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)    |\
 578                          ORxG_ACS_DIV2                    |\
 579                          ORxG_SCY_8_CLK                   |\
 580                          ORxU_EHTR_8IDLE)
 581
 582 /* Bank 6 - Board control registers
 583  */
 584 #define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)   |\
 585                          BRx_PS_8                       |\
 586                          BRx_MS_GPCM_P                  |\
 587                          BRx_V)
 588
 589 #define CONFIG_SYS_OR6_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)      |\
 590                          ORxG_CSNT                      |\
 591                          ORxG_SCY_5_CLK)
 592
 593 /* Bank 7 - VME Extended Access Range
 594  */
 595 #define CONFIG_SYS_BR7_PRELIM  ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
 596                          BRx_PS_32                      |\
 597                          BRx_MS_GPCM_P                  |\
 598                          BRx_V)
 599
 600 #define CONFIG_SYS_OR7_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)    |\
 601                          ORxG_CSNT                      |\
 602                          ORxG_ACS_DIV1                  |\
 603                          ORxG_SCY_5_CLK                 |\
 604                          ORxG_SETA)
 605
 606 /* Bank 8 - VME Standard Access Range
 607  */
 608 #define CONFIG_SYS_BR8_PRELIM  ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
 609                          BRx_PS_16                      |\
 610                          BRx_MS_GPCM_P                  |\
 611                          BRx_V)
 612
 613 #define CONFIG_SYS_OR8_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)    |\
 614                          ORxG_CSNT                      |\
 615                          ORxG_ACS_DIV1                  |\
 616                          ORxG_SCY_5_CLK                 |\
 617                          ORxG_SETA)
 618
 619 /* Bank 9 - VME Short I/O Access Range
 620  */
 621 #define CONFIG_SYS_BR9_PRELIM  ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
 622                          BRx_PS_16                        |\
 623                          BRx_MS_GPCM_P                    |\
 624                          BRx_V)
 625
 626 #define CONFIG_SYS_OR9_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)    |\
 627                          ORxG_CSNT                        |\
 628                          ORxG_ACS_DIV1                    |\
 629                          ORxG_SCY_5_CLK                   |\
 630                          ORxG_SETA)
 631
 632 #endif  /* __CONFIG_H */