4 * (C) Copyright 2003-2005
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * (C) Copyright 2004-2005
8 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
14 * 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 * High Level Configuration Options
41 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
42 #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
43 #define CONFIG_TQM5200 1 /* ... on a TQM5200 module */
45 #define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */
46 #define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */
47 #define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */
48 #define CONFIG_BC3450_USB 1 /* + USB support */
49 # define CONFIG_FAT 1 /* + FAT support */
50 # define CONFIG_EXT2 1 /* + EXT2 support */
51 #undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */
52 #undef CONFIG_BC3450_CAN /* + CAN transceiver */
53 #undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */
54 #undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */
55 #undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */
56 #define CONFIG_BC3450_FP 1 /* + enable FP O/P */
57 #undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */
60 * Valid values for CONFIG_SYS_TEXT_BASE are:
61 * 0xFC000000 boot low (standard configuration with room for
62 * max 64 MByte Flash ROM)
63 * 0x00100000 boot from RAM (for testing only)
65 #ifndef CONFIG_SYS_TEXT_BASE
66 #define CONFIG_SYS_TEXT_BASE 0xFC000000
69 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
71 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
72 #define BOOTFLAG_WARM 0x02 /* Software reboot */
74 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
77 * Serial console configuration
79 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
80 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
81 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
86 #ifdef CONFIG_BC3450_PS2
87 # define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
88 # define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
89 # define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
90 # define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
91 # define CONFIG_BOARD_EARLY_INIT_R
92 #endif /* CONFIG_BC3450_PS2 */
96 * 0x40000000 - 0x4fffffff - PCI Memory
97 * 0x50000000 - 0x50ffffff - PCI IO Space
100 # define CONFIG_PCI_PNP 1
101 /* #define CONFIG_PCI_SCAN_SHOW 1 */
102 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
104 #define CONFIG_PCI_MEM_BUS 0x40000000
105 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
106 #define CONFIG_PCI_MEM_SIZE 0x10000000
108 #define CONFIG_PCI_IO_BUS 0x50000000
109 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
110 #define CONFIG_PCI_IO_SIZE 0x01000000
112 #define CONFIG_NET_MULTI 1
113 /*#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
114 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
115 #define CONFIG_NS8382X 1
120 # define CONFIG_VIDEO
121 # define CONFIG_VIDEO_SM501
122 # define CONFIG_VIDEO_SM501_32BPP
123 # define CONFIG_CFB_CONSOLE
124 # define CONFIG_VIDEO_LOGO
125 # define CONFIG_VGA_AS_SINGLE_DEVICE
126 # define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */
127 # define CONFIG_VIDEO_SW_CURSOR
128 # define CONFIG_SPLASH_SCREEN
129 # define CONFIG_SYS_CONSOLE_IS_IN_ENV
134 #define CONFIG_MAC_PARTITION
135 #define CONFIG_DOS_PARTITION
136 #define CONFIG_ISO_PARTITION
141 #ifdef CONFIG_BC3450_USB
142 # define CONFIG_USB_OHCI
143 # define CONFIG_USB_STORAGE
144 #endif /* CONFIG_BC3450_USB */
149 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
150 CONFIG_SYS_POST_CPU | \
154 /* preserve space for the post_word at end of on-chip SRAM */
155 # define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
156 #endif /* CONFIG_POST */
162 #define CONFIG_BOOTP_BOOTFILESIZE
163 #define CONFIG_BOOTP_BOOTPATH
164 #define CONFIG_BOOTP_GATEWAY
165 #define CONFIG_BOOTP_HOSTNAME
169 * Command line configuration.
171 #include <config_cmd_default.h>
173 #define CONFIG_CMD_ASKENV
174 #define CONFIG_CMD_DATE
175 #define CONFIG_CMD_DHCP
176 #define CONFIG_CMD_ECHO
177 #define CONFIG_CMD_EEPROM
178 #define CONFIG_CMD_I2C
179 #define CONFIG_CMD_JFFS2
180 #define CONFIG_CMD_MII
181 #define CONFIG_CMD_NFS
182 #define CONFIG_CMD_PING
183 #define CONFIG_CMD_REGINFO
184 #define CONFIG_CMD_SNTP
185 #define CONFIG_CMD_BSP
188 #define CONFIG_CMD_BMP
191 #ifdef CONFIG_BC3450_IDE
192 #define CONFIG_CMD_IDE
195 #if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
197 #define CONFIG_CMD_FAT
201 #define CONFIG_CMD_EXT2
205 #ifdef CONFIG_BC3450_USB
206 #define CONFIG_CMD_USB
210 #define CONFIG_CMD_PCI
214 #define CONFIG_CMD_DIAG
218 #define CONFIG_TIMESTAMP /* display image timestamps */
220 #if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
221 # define CONFIG_SYS_LOWBOOT 1
227 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
228 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
230 #define CONFIG_PREBOOT "echo;" \
231 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
234 #undef CONFIG_BOOTARGS
236 #define CONFIG_EXTRA_ENV_SETTINGS \
238 "ipaddr=192.168.1.10\0" \
239 "serverip=192.168.1.3\0" \
240 "netmask=255.255.255.0\0" \
241 "hostname=bc3450\0" \
242 "rootpath=/opt/eldk/ppc_6xx\0" \
243 "kernel_addr=fc0a0000\0" \
244 "ramdisk_addr=fc1c0000\0" \
245 "ramargs=setenv bootargs root=/dev/ram rw\0" \
246 "nfsargs=setenv bootargs root=/dev/nfs rw " \
247 "nfsroot=$(serverip):$(rootpath)\0" \
248 "ideargs=setenv bootargs root=/dev/hda2 ro\0" \
249 "addip=setenv bootargs $(bootargs) " \
250 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
251 ":$(hostname):$(netdev):off panic=1\0" \
252 "addcons=setenv bootargs $(bootargs) " \
253 "console=ttyS0,$(baudrate) console=tty0\0" \
254 "flash_self=run ramargs addip addcons;" \
255 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
256 "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \
257 "net_nfs=tftp 200000 $(bootfile); " \
258 "run nfsargs addip addcons; bootm\0" \
259 "ide_nfs=run nfsargs addip addcons; " \
260 "disk 200000 0:1; bootm\0" \
261 "ide_ide=run ideargs addip addcons; " \
262 "disk 200000 0:1; bootm\0" \
263 "usb_self=run usbload; run ramargs addip addcons; " \
264 "bootm 200000 400000\0" \
265 "usbload=usb reset; usb scan; usbboot 200000 0:1; " \
266 "usbboot 400000 0:2\0" \
267 "bootfile=uImage\0" \
268 "load=tftp 200000 $(u-boot)\0" \
269 "u-boot=u-boot.bin\0" \
270 "update=protect off FC000000 FC05FFFF;" \
271 "erase FC000000 FC05FFFF;" \
272 "cp.b 200000 FC000000 $(filesize);" \
273 "protect on FC000000 FC05FFFF\0" \
276 #define CONFIG_BOOTCOMMAND "run flash_self"
279 * IPB Bus clocking configuration.
281 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
284 * PCI Bus clocking configuration
286 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
287 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
288 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
290 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
291 # define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
297 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
298 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
301 * I2C clock frequency
303 * Please notice, that the resulting clock frequency could differ from the
304 * configured value. This is because the I2C clock is derived from system
305 * clock over a frequency divider with only a few divider values. U-boot
306 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
307 * approximation allways lies below the configured value, never above.
309 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
310 #define CONFIG_SYS_I2C_SLAVE 0x7F
313 * EEPROM configuration for I²C EEPROM M24C32
314 * M24C64 should work also. For other EEPROMs config should be verified.
316 * The TQM5200 module may hold an EEPROM at address 0x50.
318 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */
319 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
320 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
321 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
326 #if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
327 # define CONFIG_RTC_M41T11 1
328 # define CONFIG_SYS_I2C_RTC_ADDR 0x68
330 # define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */
331 # define CONFIG_BOARD_EARLY_INIT_R
335 * Flash configuration
337 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
339 /* use CFI flash driver if no module variant is spezified */
340 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
341 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
342 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
343 #define CONFIG_SYS_FLASH_EMPTY_INFO
344 #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
345 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
346 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
348 #if !defined(CONFIG_SYS_LOWBOOT)
349 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
350 #else /* CONFIG_SYS_LOWBOOT */
351 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
352 #endif /* CONFIG_SYS_LOWBOOT */
353 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
355 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
356 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
358 /* Dynamic MTD partition support */
359 #define CONFIG_CMD_MTDPARTS
360 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
361 #define CONFIG_FLASH_CFI_MTD
362 #define MTDIDS_DEFAULT "nor0=TQM5200-0"
363 #define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
371 * Environment settings
373 #define CONFIG_ENV_IS_IN_FLASH 1
374 #define CONFIG_ENV_SIZE 0x10000
375 #define CONFIG_ENV_SECT_SIZE 0x20000
376 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
377 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
382 #define CONFIG_SYS_MBAR 0xF0000000
383 #define CONFIG_SYS_SDRAM_BASE 0x00000000
384 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
386 /* Use ON-Chip SRAM until RAM will be available */
387 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
389 /* preserve space for the post_word at end of on-chip SRAM */
390 # define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
392 # define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
393 #endif /*CONFIG_POST*/
395 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Bytes reserved for initial data */
396 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
397 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
399 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
400 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
401 # define CONFIG_SYS_RAMBOOT 1
404 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
405 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
406 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
409 * Ethernet configuration
411 * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
413 #define CONFIG_MPC5xxx_FEC 1
414 #define CONFIG_MPC5xxx_FEC_MII100
415 #undef CONFIG_MPC5xxx_MII10
416 #define CONFIG_PHY_ADDR 0x00
419 * GPIO configuration on BC3450
421 * PSC1: UART1 (Service-UART) [0x xxxxxxx4]
422 * PSC2: UART2 [0x xxxxxx4x]
423 * or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x]
424 * PSC3: USB2 [0x xxxxx1xx]
425 * USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx]
427 * CONFIG_USB_CONFIG which is
428 * used by usb_ohci.c to set
430 * Eth: 10/100Mbit Ethernet [0x xxx0xxxx]
431 * (this is reset to '5'
432 * in FEC driver: fec.c)
433 * PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx]
434 * ATA/CS: ??? [0x x1xxxxxx]
435 * FIXME! UM Fig 2-10 suggests [0x x0xxxxxx]
436 * CS1: Use Pin gpio_wkup_6 as second
437 * SDRAM chip select (mem_cs1)
439 * I2C: CAN1 / I²C2 [0x bxxxxxxx]
441 #ifdef CONFIG_BC3450_AC97
442 # define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502124
443 #else /* PSC2=UART2 */
444 # define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502144
448 * Miscellaneous configurable options
450 #define CONFIG_SYS_LONGHELP /* undef to save memory */
451 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
452 #if defined(CONFIG_CMD_KGDB)
453 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
455 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
457 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
458 #define CONFIG_SYS_MAXARGS 16 /* max no of command args */
459 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg. Buffer Size */
461 #define CONFIG_SYS_ALT_MEMTEST /* Enable an alternative, */
462 /* more extensive mem test */
464 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
465 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
467 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
469 #define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */
471 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
472 #if defined(CONFIG_CMD_KGDB)
473 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
477 * Enable loopw command.
482 * Various low-level settings
484 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
485 #define CONFIG_SYS_HID0_FINAL HID0_ICE
487 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
488 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
489 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
490 # define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
492 # define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
494 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
495 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
497 /* automatic configuration of chip selects */
498 #ifdef CONFIG_TQM5200
499 # define CONFIG_LAST_STAGE_INIT
500 #endif /* CONFIG_TQM5200 */
503 * SRAM - Do not map below 2 GB in address space, because this area is used
504 * for SDRAM autosizing.
506 #ifdef CONFIG_TQM5200
507 # define CONFIG_SYS_CS2_START 0xE5000000
508 # define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
509 # define CONFIG_SYS_CS2_CFG 0x0004D930
510 #endif /* CONFIG_TQM5200 */
513 * Grafic controller - Do not map below 2 GB in address space, because this
514 * area is used for SDRAM autosizing.
516 #ifdef CONFIG_TQM5200
517 # define SM501_FB_BASE 0xE0000000
518 # define CONFIG_SYS_CS1_START (SM501_FB_BASE)
519 # define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
520 # define CONFIG_SYS_CS1_CFG 0x8F48FF70
521 # define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
522 #endif /* CONFIG_TQM5200 */
524 #define CONFIG_SYS_CS_BURST 0x00000000
525 #define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */
526 /* flash and SM501 */
528 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
533 #define CONFIG_USB_CLOCK 0x0001BBBB
534 #define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */
537 * IDE/ATA stuff Supports IDE harddisk
539 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
541 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
542 #undef CONFIG_IDE_LED /* LED for ide not supported */
544 #define CONFIG_IDE_RESET /* reset for ide supported */
545 #define CONFIG_IDE_PREINIT
547 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
548 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
550 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
552 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
554 /* Offset for data I/O */
555 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
557 /* Offset for normal register accesses */
558 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
560 /* Offset for alternate registers */
561 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
563 /* Interval between registers */
564 #define CONFIG_SYS_ATA_STRIDE 4
566 #endif /* __CONFIG_H */