include/configs/B4860QDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 /*
  10  * B4860 QDS board configuration file
  11  */
  12 #ifdef CONFIG_RAMBOOT_PBL
  13 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
  14 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
  15 #ifndef CONFIG_NAND
  16 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  17 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  18 #else
  19 #define CONFIG_SPL_FLUSH_IMAGE
  20 #define CONFIG_SPL_PAD_TO               0x40000
  21 #define CONFIG_SPL_MAX_SIZE             0x28000
  22 #define RESET_VECTOR_OFFSET             0x27FFC
  23 #define BOOT_PAGE_OFFSET                0x27000
  24 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  25 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  26 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  27 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  28 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  29 #define CONFIG_SPL_NAND_BOOT
  30 #ifdef CONFIG_SPL_BUILD
  31 #define CONFIG_SPL_SKIP_RELOCATE
  32 #define CONFIG_SPL_COMMON_INIT_DDR
  33 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  34 #endif
  35 #endif
  36 #endif
  37
  38 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  39 /* Set 1M boot space */
  40 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  42                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  43 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  44 #endif
  45
  46 /* High Level Configuration Options */
  47 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  48
  49 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  50 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  51 #endif
  52
  53 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  54 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  55 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  56 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  57 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  58
  59 #ifndef CONFIG_ARCH_B4420
  60 #define CONFIG_SYS_SRIO
  61 #define CONFIG_SRIO1                    /* SRIO port 1 */
  62 #define CONFIG_SRIO2                    /* SRIO port 2 */
  63 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  64 #endif
  65
  66 /* I2C bus multiplexer */
  67 #define I2C_MUX_PCA_ADDR                0x77
  68
  69 /* VSC Crossbar switches */
  70 #define CONFIG_VSC_CROSSBAR
  71 #define I2C_CH_DEFAULT                  0x8
  72 #define I2C_CH_VSC3316                  0xc
  73 #define I2C_CH_VSC3308                  0xd
  74
  75 #define VSC3316_TX_ADDRESS              0x70
  76 #define VSC3316_RX_ADDRESS              0x71
  77 #define VSC3308_TX_ADDRESS              0x02
  78 #define VSC3308_RX_ADDRESS              0x03
  79
  80 /* IDT clock synthesizers */
  81 #define CONFIG_IDT8T49N222A
  82 #define I2C_CH_IDT                     0x9
  83
  84 #define IDT_SERDES1_ADDRESS            0x6E
  85 #define IDT_SERDES2_ADDRESS            0x6C
  86
  87 /* Voltage monitor on channel 2*/
  88 #define I2C_MUX_CH_VOL_MONITOR          0xa
  89 #define I2C_VOL_MONITOR_ADDR            0x40
  90 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
  91 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
  92 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
  93
  94 #define CONFIG_ZM7300
  95 #define I2C_MUX_CH_DPM                  0xa
  96 #define I2C_DPM_ADDR                    0x28
  97
  98 #define CONFIG_ENV_OVERWRITE
  99
 100 #if defined(CONFIG_SPIFLASH)
 101 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 102 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 103 #define CONFIG_ENV_SECT_SIZE            0x10000
 104 #elif defined(CONFIG_SDCARD)
 105 #define CONFIG_SYS_MMC_ENV_DEV          0
 106 #define CONFIG_ENV_SIZE                 0x2000
 107 #define CONFIG_ENV_OFFSET               (512 * 1097)
 108 #elif defined(CONFIG_NAND)
 109 #define CONFIG_ENV_SIZE                 0x2000
 110 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 111 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 112 #define CONFIG_ENV_ADDR         0xffe20000
 113 #define CONFIG_ENV_SIZE         0x2000
 114 #elif defined(CONFIG_ENV_IS_NOWHERE)
 115 #define CONFIG_ENV_SIZE         0x2000
 116 #else
 117 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 118 #define CONFIG_ENV_SIZE         0x2000
 119 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 120 #endif
 121
 122 #ifndef __ASSEMBLY__
 123 unsigned long get_board_sys_clk(void);
 124 unsigned long get_board_ddr_clk(void);
 125 #endif
 126 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 127 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 128
 129 /*
 130  * These can be toggled for performance analysis, otherwise use default.
 131  */
 132 #define CONFIG_SYS_CACHE_STASHING
 133 #define CONFIG_BTB                      /* toggle branch predition */
 134 #define CONFIG_DDR_ECC
 135 #ifdef CONFIG_DDR_ECC
 136 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 137 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 138 #endif
 139
 140 #define CONFIG_ENABLE_36BIT_PHYS
 141
 142 #ifdef CONFIG_PHYS_64BIT
 143 #define CONFIG_ADDR_MAP
 144 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 145 #endif
 146
 147 #if 0
 148 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 149 #endif
 150 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 151 #define CONFIG_SYS_MEMTEST_END          0x00400000
 152
 153 /*
 154  *  Config the L3 Cache as L3 SRAM
 155  */
 156 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 157 #define CONFIG_SYS_L3_SIZE              256 << 10
 158 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 159 #ifdef CONFIG_NAND
 160 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 161 #endif
 162 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 163 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 164 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 165
 166 #ifdef CONFIG_PHYS_64BIT
 167 #define CONFIG_SYS_DCSRBAR              0xf0000000
 168 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 169 #endif
 170
 171 /* EEPROM */
 172 #define CONFIG_ID_EEPROM
 173 #define CONFIG_SYS_I2C_EEPROM_NXID
 174 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 175 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 176 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 177 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 178 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 179
 180 /*
 181  * DDR Setup
 182  */
 183 #define CONFIG_VERY_BIG_RAM
 184 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 185 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 186
 187 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 188 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 189
 190 #define CONFIG_DDR_SPD
 191 #define CONFIG_SYS_DDR_RAW_TIMING
 192
 193 #define CONFIG_SYS_SPD_BUS_NUM  0
 194 #define SPD_EEPROM_ADDRESS1     0x51
 195 #define SPD_EEPROM_ADDRESS2     0x53
 196
 197 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 198 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 199
 200 /*
 201  * IFC Definitions
 202  */
 203 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 204 #ifdef CONFIG_PHYS_64BIT
 205 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 206 #else
 207 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 208 #endif
 209
 210 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 211 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 212                                 + 0x8000000) | \
 213                                 CSPR_PORT_SIZE_16 | \
 214                                 CSPR_MSEL_NOR | \
 215                                 CSPR_V)
 216 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 217 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 218                                 CSPR_PORT_SIZE_16 | \
 219                                 CSPR_MSEL_NOR | \
 220                                 CSPR_V)
 221 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
 222 /* NOR Flash Timing Params */
 223 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
 224 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
 225                                 FTIM0_NOR_TEADC(0x04) | \
 226                                 FTIM0_NOR_TEAHC(0x20))
 227 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 228                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 229                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 230 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
 231                                 FTIM2_NOR_TCH(0x0E) | \
 232                                 FTIM2_NOR_TWPH(0x0E) | \
 233                                 FTIM2_NOR_TWP(0x1c))
 234 #define CONFIG_SYS_NOR_FTIM3    0x0
 235
 236 #define CONFIG_SYS_FLASH_QUIET_TEST
 237 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 238
 239 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 240 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 241 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 242 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 243
 244 #define CONFIG_SYS_FLASH_EMPTY_INFO
 245 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 246                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 247
 248 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 249 #define CONFIG_FSL_QIXIS_V2
 250 #define QIXIS_BASE              0xffdf0000
 251 #ifdef CONFIG_PHYS_64BIT
 252 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 253 #else
 254 #define QIXIS_BASE_PHYS         QIXIS_BASE
 255 #endif
 256 #define QIXIS_LBMAP_SWITCH              0x01
 257 #define QIXIS_LBMAP_MASK                0x0f
 258 #define QIXIS_LBMAP_SHIFT               0
 259 #define QIXIS_LBMAP_DFLTBANK            0x00
 260 #define QIXIS_LBMAP_ALTBANK             0x02
 261 #define QIXIS_RST_CTL_RESET             0x31
 262 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 263 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 264 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 265
 266 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 267 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 268                                 | CSPR_PORT_SIZE_8 \
 269                                 | CSPR_MSEL_GPCM \
 270                                 | CSPR_V)
 271 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 272 #define CONFIG_SYS_CSOR3        0x0
 273 /* QIXIS Timing parameters for IFC CS3 */
 274 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 275                                         FTIM0_GPCM_TEADC(0x0e) | \
 276                                         FTIM0_GPCM_TEAHC(0x0e))
 277 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 278                                         FTIM1_GPCM_TRAD(0x1f))
 279 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 280                                         FTIM2_GPCM_TCH(0x8) | \
 281                                         FTIM2_GPCM_TWP(0x1f))
 282 #define CONFIG_SYS_CS3_FTIM3            0x0
 283
 284 /* NAND Flash on IFC */
 285 #define CONFIG_NAND_FSL_IFC
 286 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 287 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 288 #define CONFIG_SYS_NAND_BASE            0xff800000
 289 #ifdef CONFIG_PHYS_64BIT
 290 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 291 #else
 292 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 293 #endif
 294
 295 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 296 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 297                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 298                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 299                                 | CSPR_V)
 300 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 301
 302 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 303                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 304                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 305                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 306                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 307                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 308                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 309
 310 #define CONFIG_SYS_NAND_ONFI_DETECTION
 311
 312 /* ONFI NAND Flash mode0 Timing Params */
 313 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 314                                         FTIM0_NAND_TWP(0x18)   | \
 315                                         FTIM0_NAND_TWCHT(0x07) | \
 316                                         FTIM0_NAND_TWH(0x0a))
 317 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 318                                         FTIM1_NAND_TWBE(0x39)  | \
 319                                         FTIM1_NAND_TRR(0x0e)   | \
 320                                         FTIM1_NAND_TRP(0x18))
 321 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 322                                         FTIM2_NAND_TREH(0x0a) | \
 323                                         FTIM2_NAND_TWHRE(0x1e))
 324 #define CONFIG_SYS_NAND_FTIM3           0x0
 325
 326 #define CONFIG_SYS_NAND_DDR_LAW         11
 327
 328 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 329 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 330
 331 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 332
 333 #if defined(CONFIG_NAND)
 334 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 335 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 336 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 337 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 338 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 339 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 340 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 341 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 342 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 343 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 344 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 345 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 346 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 347 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 348 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 349 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 350 #else
 351 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 352 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 353 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 354 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 355 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 356 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 357 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 358 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 359 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 360 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 361 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 362 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 363 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 364 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 365 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 366 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 367 #endif
 368 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 369 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 370 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 371 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 372 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 373 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 374 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 375 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 376
 377 #ifdef CONFIG_SPL_BUILD
 378 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 379 #else
 380 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 381 #endif
 382
 383 #if defined(CONFIG_RAMBOOT_PBL)
 384 #define CONFIG_SYS_RAMBOOT
 385 #endif
 386
 387 #define CONFIG_HWCONFIG
 388
 389 /* define to use L1 as initial stack */
 390 #define CONFIG_L1_INIT_RAM
 391 #define CONFIG_SYS_INIT_RAM_LOCK
 392 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 393 #ifdef CONFIG_PHYS_64BIT
 394 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 395 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 396 /* The assembler doesn't like typecast */
 397 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 398         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 399           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 400 #else
 401 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 402 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 403 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 404 #endif
 405 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 406
 407 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 408                                         GENERATED_GBL_DATA_SIZE)
 409 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 410
 411 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 412 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 413
 414 /* Serial Port - controlled on board with jumper J8
 415  * open - index 2
 416  * shorted - index 1
 417  */
 418 #define CONFIG_SYS_NS16550_SERIAL
 419 #define CONFIG_SYS_NS16550_REG_SIZE     1
 420 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 421
 422 #define CONFIG_SYS_BAUDRATE_TABLE       \
 423         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 424
 425 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 426 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 427 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 428 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 429
 430 /* I2C */
 431 #define CONFIG_SYS_I2C
 432 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 433 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 434 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 435 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
 436 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 437 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 438 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
 439
 440 /*
 441  * RTC configuration
 442  */
 443 #define RTC
 444 #define CONFIG_RTC_DS3231               1
 445 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 446
 447 /*
 448  * RapidIO
 449  */
 450 #ifdef CONFIG_SYS_SRIO
 451 #ifdef CONFIG_SRIO1
 452 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 453 #ifdef CONFIG_PHYS_64BIT
 454 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 455 #else
 456 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 457 #endif
 458 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 459 #endif
 460
 461 #ifdef CONFIG_SRIO2
 462 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 463 #ifdef CONFIG_PHYS_64BIT
 464 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 465 #else
 466 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 467 #endif
 468 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 469 #endif
 470 #endif
 471
 472 /*
 473  * for slave u-boot IMAGE instored in master memory space,
 474  * PHYS must be aligned based on the SIZE
 475  */
 476 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 477 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 478 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 479 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 480 /*
 481  * for slave UCODE and ENV instored in master memory space,
 482  * PHYS must be aligned based on the SIZE
 483  */
 484 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 485 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 486 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 487
 488 /* slave core release by master*/
 489 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 490 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 491
 492 /*
 493  * SRIO_PCIE_BOOT - SLAVE
 494  */
 495 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 496 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 497 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 498                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 499 #endif
 500
 501 /*
 502  * eSPI - Enhanced SPI
 503  */
 504
 505 /*
 506  * MAPLE
 507  */
 508 #ifdef CONFIG_PHYS_64BIT
 509 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
 510 #else
 511 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
 512 #endif
 513
 514 /*
 515  * General PCI
 516  * Memory space is mapped 1-1, but I/O space must start from 0.
 517  */
 518
 519 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 520 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 521 #ifdef CONFIG_PHYS_64BIT
 522 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 523 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 524 #else
 525 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 526 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 527 #endif
 528 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 529 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 530 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 531 #ifdef CONFIG_PHYS_64BIT
 532 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 533 #else
 534 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 535 #endif
 536 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 537
 538 /* Qman/Bman */
 539 #ifndef CONFIG_NOBQFMAN
 540 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
 541 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 542 #ifdef CONFIG_PHYS_64BIT
 543 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 544 #else
 545 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 546 #endif
 547 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 548 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 549 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 550 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 551 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 552 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 553                                         CONFIG_SYS_BMAN_CENA_SIZE)
 554 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 555 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 556 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
 557 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 558 #ifdef CONFIG_PHYS_64BIT
 559 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 560 #else
 561 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 562 #endif
 563 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 564 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 565 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 566 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 567 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 568 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 569                                         CONFIG_SYS_QMAN_CENA_SIZE)
 570 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 571 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 572
 573 #define CONFIG_SYS_DPAA_FMAN
 574
 575 #define CONFIG_SYS_DPAA_RMAN
 576
 577 /* Default address of microcode for the Linux Fman driver */
 578 #if defined(CONFIG_SPIFLASH)
 579 /*
 580  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 581  * env, so we got 0x110000.
 582  */
 583 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 584 #elif defined(CONFIG_SDCARD)
 585 /*
 586  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 587  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 588  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 589  */
 590 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
 591 #elif defined(CONFIG_NAND)
 592 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
 593 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 594 /*
 595  * Slave has no ucode locally, it can fetch this from remote. When implementing
 596  * in two corenet boards, slave's ucode could be stored in master's memory
 597  * space, the address can be mapped from slave TLB->slave LAW->
 598  * slave SRIO or PCIE outbound window->master inbound window->
 599  * master LAW->the ucode address in master's memory space.
 600  */
 601 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 602 #else
 603 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 604 #endif
 605 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 606 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 607 #endif /* CONFIG_NOBQFMAN */
 608
 609 #ifdef CONFIG_SYS_DPAA_FMAN
 610 #define CONFIG_PHYLIB_10G
 611 #define CONFIG_PHY_VITESSE
 612 #define CONFIG_PHY_TERANETICS
 613 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 614 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 615 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 616 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 617 #endif
 618
 619 #ifdef CONFIG_PCI
 620 #define CONFIG_PCI_INDIRECT_BRIDGE
 621
 622 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 623 #endif  /* CONFIG_PCI */
 624
 625 #ifdef CONFIG_FMAN_ENET
 626 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
 627 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
 628
 629 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
 630 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
 631 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
 632
 633 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 634 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 635 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 636 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 637
 638 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 639 #endif
 640
 641 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
 642
 643 /*
 644  * Environment
 645  */
 646 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 647 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 648
 649 /*
 650 * USB
 651 */
 652 #define CONFIG_HAS_FSL_DR_USB
 653
 654 #ifdef CONFIG_HAS_FSL_DR_USB
 655 #ifdef CONFIG_USB_EHCI_HCD
 656 #define CONFIG_USB_EHCI_FSL
 657 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 658 #endif
 659 #endif
 660
 661 /*
 662  * Miscellaneous configurable options
 663  */
 664 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 665
 666 /*
 667  * For booting Linux, the board info and command line data
 668  * have to be in the first 64 MB of memory, since this is
 669  * the maximum mapped by the Linux kernel during initialization.
 670  */
 671 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 672 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 673
 674 #ifdef CONFIG_CMD_KGDB
 675 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 676 #endif
 677
 678 /*
 679  * Environment Configuration
 680  */
 681 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 682 #define CONFIG_BOOTFILE         "uImage"
 683 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 684
 685 /* default location for tftp and bootm */
 686 #define CONFIG_LOADADDR         1000000
 687
 688 #define __USB_PHY_TYPE  ulpi
 689
 690 #ifdef CONFIG_ARCH_B4860
 691 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
 692                         "bank_intlv=cs0_cs1;"   \
 693                         "en_cpc:cpc2;"
 694 #else
 695 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
 696 #endif
 697
 698 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 699         HWCONFIG                                                \
 700         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 701         "netdev=eth0\0"                                         \
 702         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 703         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
 704         "tftpflash=tftpboot $loadaddr $uboot && "               \
 705         "protect off $ubootaddr +$filesize && "                 \
 706         "erase $ubootaddr +$filesize && "                       \
 707         "cp.b $loadaddr $ubootaddr $filesize && "               \
 708         "protect on $ubootaddr +$filesize && "                  \
 709         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 710         "consoledev=ttyS0\0"                                    \
 711         "ramdiskaddr=2000000\0"                                 \
 712         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
 713         "fdtaddr=1e00000\0"                                     \
 714         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
 715         "bdev=sda3\0"
 716
 717 /* For emulation this causes u-boot to jump to the start of the proof point
 718    app code automatically */
 719 #define CONFIG_PROOF_POINTS                     \
 720  "setenv bootargs root=/dev/$bdev rw "          \
 721  "console=$consoledev,$baudrate $othbootargs;"  \
 722  "cpu 1 release 0x29000000 - - -;"              \
 723  "cpu 2 release 0x29000000 - - -;"              \
 724  "cpu 3 release 0x29000000 - - -;"              \
 725  "cpu 4 release 0x29000000 - - -;"              \
 726  "cpu 5 release 0x29000000 - - -;"              \
 727  "cpu 6 release 0x29000000 - - -;"              \
 728  "cpu 7 release 0x29000000 - - -;"              \
 729  "go 0x29000000"
 730
 731 #define CONFIG_HVBOOT   \
 732  "setenv bootargs config-addr=0x60000000; "     \
 733  "bootm 0x01000000 - 0x00f00000"
 734
 735 #define CONFIG_ALU                              \
 736  "setenv bootargs root=/dev/$bdev rw "          \
 737  "console=$consoledev,$baudrate $othbootargs;"  \
 738  "cpu 1 release 0x01000000 - - -;"              \
 739  "cpu 2 release 0x01000000 - - -;"              \
 740  "cpu 3 release 0x01000000 - - -;"              \
 741  "cpu 4 release 0x01000000 - - -;"              \
 742  "cpu 5 release 0x01000000 - - -;"              \
 743  "cpu 6 release 0x01000000 - - -;"              \
 744  "cpu 7 release 0x01000000 - - -;"              \
 745  "go 0x01000000"
 746
 747 #define CONFIG_LINUX                            \
 748  "setenv bootargs root=/dev/ram rw "            \
 749  "console=$consoledev,$baudrate $othbootargs;"  \
 750  "setenv ramdiskaddr 0x02000000;"               \
 751  "setenv fdtaddr 0x01e00000;"                   \
 752  "setenv loadaddr 0x1000000;"                   \
 753  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 754
 755 #define CONFIG_HDBOOT                                   \
 756         "setenv bootargs root=/dev/$bdev rw "           \
 757         "console=$consoledev,$baudrate $othbootargs;"   \
 758         "tftp $loadaddr $bootfile;"                     \
 759         "tftp $fdtaddr $fdtfile;"                       \
 760         "bootm $loadaddr - $fdtaddr"
 761
 762 #define CONFIG_NFSBOOTCOMMAND                   \
 763         "setenv bootargs root=/dev/nfs rw "     \
 764         "nfsroot=$serverip:$rootpath "          \
 765         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 766         "console=$consoledev,$baudrate $othbootargs;"   \
 767         "tftp $loadaddr $bootfile;"             \
 768         "tftp $fdtaddr $fdtfile;"               \
 769         "bootm $loadaddr - $fdtaddr"
 770
 771 #define CONFIG_RAMBOOTCOMMAND                           \
 772         "setenv bootargs root=/dev/ram rw "             \
 773         "console=$consoledev,$baudrate $othbootargs;"   \
 774         "tftp $ramdiskaddr $ramdiskfile;"               \
 775         "tftp $loadaddr $bootfile;"                     \
 776         "tftp $fdtaddr $fdtfile;"                       \
 777         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 778
 779 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 780
 781 #include <asm/fsl_secure_boot.h>
 782
 783 #endif  /* __CONFIG_H */