include/configs/B4860QDS.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * B4860 QDS board configuration file
  12  */
  13 #ifdef CONFIG_RAMBOOT_PBL
  14 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
  15 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
  16 #ifndef CONFIG_NAND
  17 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  18 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  19 #else
  20 #define CONFIG_SPL_FLUSH_IMAGE
  21 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  22 #define CONFIG_SYS_TEXT_BASE            0x00201000
  23 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  24 #define CONFIG_SPL_PAD_TO               0x40000
  25 #define CONFIG_SPL_MAX_SIZE             0x28000
  26 #define RESET_VECTOR_OFFSET             0x27FFC
  27 #define BOOT_PAGE_OFFSET                0x27000
  28 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  29 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  30 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  31 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  32 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  33 #define CONFIG_SPL_NAND_BOOT
  34 #ifdef CONFIG_SPL_BUILD
  35 #define CONFIG_SPL_SKIP_RELOCATE
  36 #define CONFIG_SPL_COMMON_INIT_DDR
  37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  38 #endif
  39 #endif
  40 #endif
  41
  42 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  43 /* Set 1M boot space */
  44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  45 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  46                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  47 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  48 #endif
  49
  50 /* High Level Configuration Options */
  51 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  52 #define CONFIG_MP                       /* support multiple processors */
  53
  54 #ifndef CONFIG_SYS_TEXT_BASE
  55 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  56 #endif
  57
  58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  59 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  60 #endif
  61
  62 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  63 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  64 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  65 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  66 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  67
  68 #ifndef CONFIG_ARCH_B4420
  69 #define CONFIG_SYS_SRIO
  70 #define CONFIG_SRIO1                    /* SRIO port 1 */
  71 #define CONFIG_SRIO2                    /* SRIO port 2 */
  72 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  73 #endif
  74
  75 /* I2C bus multiplexer */
  76 #define I2C_MUX_PCA_ADDR                0x77
  77
  78 /* VSC Crossbar switches */
  79 #define CONFIG_VSC_CROSSBAR
  80 #define I2C_CH_DEFAULT                  0x8
  81 #define I2C_CH_VSC3316                  0xc
  82 #define I2C_CH_VSC3308                  0xd
  83
  84 #define VSC3316_TX_ADDRESS              0x70
  85 #define VSC3316_RX_ADDRESS              0x71
  86 #define VSC3308_TX_ADDRESS              0x02
  87 #define VSC3308_RX_ADDRESS              0x03
  88
  89 /* IDT clock synthesizers */
  90 #define CONFIG_IDT8T49N222A
  91 #define I2C_CH_IDT                     0x9
  92
  93 #define IDT_SERDES1_ADDRESS            0x6E
  94 #define IDT_SERDES2_ADDRESS            0x6C
  95
  96 /* Voltage monitor on channel 2*/
  97 #define I2C_MUX_CH_VOL_MONITOR          0xa
  98 #define I2C_VOL_MONITOR_ADDR            0x40
  99 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 100 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 101 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 102
 103 #define CONFIG_ZM7300
 104 #define I2C_MUX_CH_DPM                  0xa
 105 #define I2C_DPM_ADDR                    0x28
 106
 107 #define CONFIG_ENV_OVERWRITE
 108
 109 #ifndef CONFIG_MTD_NOR_FLASH
 110 #else
 111 #define CONFIG_FLASH_CFI_DRIVER
 112 #define CONFIG_SYS_FLASH_CFI
 113 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 114 #endif
 115
 116 #if defined(CONFIG_SPIFLASH)
 117 #define CONFIG_SYS_EXTRA_ENV_RELOC
 118 #define CONFIG_ENV_SPI_BUS              0
 119 #define CONFIG_ENV_SPI_CS               0
 120 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 121 #define CONFIG_ENV_SPI_MODE             0
 122 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 123 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 124 #define CONFIG_ENV_SECT_SIZE            0x10000
 125 #elif defined(CONFIG_SDCARD)
 126 #define CONFIG_SYS_EXTRA_ENV_RELOC
 127 #define CONFIG_SYS_MMC_ENV_DEV          0
 128 #define CONFIG_ENV_SIZE                 0x2000
 129 #define CONFIG_ENV_OFFSET               (512 * 1097)
 130 #elif defined(CONFIG_NAND)
 131 #define CONFIG_SYS_EXTRA_ENV_RELOC
 132 #define CONFIG_ENV_SIZE                 0x2000
 133 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 134 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 135 #define CONFIG_ENV_IS_IN_REMOTE
 136 #define CONFIG_ENV_ADDR         0xffe20000
 137 #define CONFIG_ENV_SIZE         0x2000
 138 #elif defined(CONFIG_ENV_IS_NOWHERE)
 139 #define CONFIG_ENV_SIZE         0x2000
 140 #else
 141 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 142 #define CONFIG_ENV_SIZE         0x2000
 143 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 144 #endif
 145
 146 #ifndef __ASSEMBLY__
 147 unsigned long get_board_sys_clk(void);
 148 unsigned long get_board_ddr_clk(void);
 149 #endif
 150 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 151 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 152
 153 /*
 154  * These can be toggled for performance analysis, otherwise use default.
 155  */
 156 #define CONFIG_SYS_CACHE_STASHING
 157 #define CONFIG_BTB                      /* toggle branch predition */
 158 #define CONFIG_DDR_ECC
 159 #ifdef CONFIG_DDR_ECC
 160 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 161 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 162 #endif
 163
 164 #define CONFIG_ENABLE_36BIT_PHYS
 165
 166 #ifdef CONFIG_PHYS_64BIT
 167 #define CONFIG_ADDR_MAP
 168 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 169 #endif
 170
 171 #if 0
 172 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 173 #endif
 174 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 175 #define CONFIG_SYS_MEMTEST_END          0x00400000
 176 #define CONFIG_SYS_ALT_MEMTEST
 177 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 178
 179 /*
 180  *  Config the L3 Cache as L3 SRAM
 181  */
 182 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 183 #define CONFIG_SYS_L3_SIZE              256 << 10
 184 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 185 #ifdef CONFIG_NAND
 186 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 187 #endif
 188 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 189 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 190 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 191 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 192
 193 #ifdef CONFIG_PHYS_64BIT
 194 #define CONFIG_SYS_DCSRBAR              0xf0000000
 195 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 196 #endif
 197
 198 /* EEPROM */
 199 #define CONFIG_ID_EEPROM
 200 #define CONFIG_SYS_I2C_EEPROM_NXID
 201 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 202 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 203 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 204 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 205 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 206
 207 /*
 208  * DDR Setup
 209  */
 210 #define CONFIG_VERY_BIG_RAM
 211 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 212 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 213
 214 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 215 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 216
 217 #define CONFIG_DDR_SPD
 218 #define CONFIG_SYS_DDR_RAW_TIMING
 219 #ifndef CONFIG_SPL_BUILD
 220 #define CONFIG_FSL_DDR_INTERACTIVE
 221 #endif
 222
 223 #define CONFIG_SYS_SPD_BUS_NUM  0
 224 #define SPD_EEPROM_ADDRESS1     0x51
 225 #define SPD_EEPROM_ADDRESS2     0x53
 226
 227 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 228 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 229
 230 /*
 231  * IFC Definitions
 232  */
 233 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 234 #ifdef CONFIG_PHYS_64BIT
 235 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 236 #else
 237 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 238 #endif
 239
 240 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 241 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 242                                 + 0x8000000) | \
 243                                 CSPR_PORT_SIZE_16 | \
 244                                 CSPR_MSEL_NOR | \
 245                                 CSPR_V)
 246 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 247 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 248                                 CSPR_PORT_SIZE_16 | \
 249                                 CSPR_MSEL_NOR | \
 250                                 CSPR_V)
 251 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
 252 /* NOR Flash Timing Params */
 253 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
 254 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
 255                                 FTIM0_NOR_TEADC(0x04) | \
 256                                 FTIM0_NOR_TEAHC(0x20))
 257 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 258                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 259                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 260 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
 261                                 FTIM2_NOR_TCH(0x0E) | \
 262                                 FTIM2_NOR_TWPH(0x0E) | \
 263                                 FTIM2_NOR_TWP(0x1c))
 264 #define CONFIG_SYS_NOR_FTIM3    0x0
 265
 266 #define CONFIG_SYS_FLASH_QUIET_TEST
 267 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 268
 269 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 270 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 271 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 272 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 273
 274 #define CONFIG_SYS_FLASH_EMPTY_INFO
 275 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 276                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 277
 278 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 279 #define CONFIG_FSL_QIXIS_V2
 280 #define QIXIS_BASE              0xffdf0000
 281 #ifdef CONFIG_PHYS_64BIT
 282 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 283 #else
 284 #define QIXIS_BASE_PHYS         QIXIS_BASE
 285 #endif
 286 #define QIXIS_LBMAP_SWITCH              0x01
 287 #define QIXIS_LBMAP_MASK                0x0f
 288 #define QIXIS_LBMAP_SHIFT               0
 289 #define QIXIS_LBMAP_DFLTBANK            0x00
 290 #define QIXIS_LBMAP_ALTBANK             0x02
 291 #define QIXIS_RST_CTL_RESET             0x31
 292 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 293 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 294 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 295
 296 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 297 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 298                                 | CSPR_PORT_SIZE_8 \
 299                                 | CSPR_MSEL_GPCM \
 300                                 | CSPR_V)
 301 #define CONFIG_SYS_AMASK3       IFC_AMASK(4 * 1024)
 302 #define CONFIG_SYS_CSOR3        0x0
 303 /* QIXIS Timing parameters for IFC CS3 */
 304 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 305                                         FTIM0_GPCM_TEADC(0x0e) | \
 306                                         FTIM0_GPCM_TEAHC(0x0e))
 307 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 308                                         FTIM1_GPCM_TRAD(0x1f))
 309 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 310                                         FTIM2_GPCM_TCH(0x8) | \
 311                                         FTIM2_GPCM_TWP(0x1f))
 312 #define CONFIG_SYS_CS3_FTIM3            0x0
 313
 314 /* NAND Flash on IFC */
 315 #define CONFIG_NAND_FSL_IFC
 316 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 317 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 318 #define CONFIG_SYS_NAND_BASE            0xff800000
 319 #ifdef CONFIG_PHYS_64BIT
 320 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 321 #else
 322 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 323 #endif
 324
 325 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 326 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 327                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 328                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 329                                 | CSPR_V)
 330 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 331
 332 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 333                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 334                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 335                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 336                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 337                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 338                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 339
 340 #define CONFIG_SYS_NAND_ONFI_DETECTION
 341
 342 /* ONFI NAND Flash mode0 Timing Params */
 343 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 344                                         FTIM0_NAND_TWP(0x18)   | \
 345                                         FTIM0_NAND_TWCHT(0x07) | \
 346                                         FTIM0_NAND_TWH(0x0a))
 347 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 348                                         FTIM1_NAND_TWBE(0x39)  | \
 349                                         FTIM1_NAND_TRR(0x0e)   | \
 350                                         FTIM1_NAND_TRP(0x18))
 351 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 352                                         FTIM2_NAND_TREH(0x0a) | \
 353                                         FTIM2_NAND_TWHRE(0x1e))
 354 #define CONFIG_SYS_NAND_FTIM3           0x0
 355
 356 #define CONFIG_SYS_NAND_DDR_LAW         11
 357
 358 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 359 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 360 #define CONFIG_CMD_NAND
 361
 362 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 363
 364 #if defined(CONFIG_NAND)
 365 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 366 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 367 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 368 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 369 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 370 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 371 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 372 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 373 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 374 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 375 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 376 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 377 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 378 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 379 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 380 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 381 #else
 382 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 383 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 384 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 385 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 386 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 387 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 388 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 389 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 390 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 391 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 392 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 393 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 394 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 395 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 396 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 397 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 398 #endif
 399 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 400 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 401 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 402 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 403 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 404 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 405 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 406 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 407
 408 #ifdef CONFIG_SPL_BUILD
 409 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 410 #else
 411 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 412 #endif
 413
 414 #if defined(CONFIG_RAMBOOT_PBL)
 415 #define CONFIG_SYS_RAMBOOT
 416 #endif
 417
 418 #define CONFIG_BOARD_EARLY_INIT_R
 419 #define CONFIG_MISC_INIT_R
 420
 421 #define CONFIG_HWCONFIG
 422
 423 /* define to use L1 as initial stack */
 424 #define CONFIG_L1_INIT_RAM
 425 #define CONFIG_SYS_INIT_RAM_LOCK
 426 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 427 #ifdef CONFIG_PHYS_64BIT
 428 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 429 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 430 /* The assembler doesn't like typecast */
 431 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 432         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 433           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 434 #else
 435 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 437 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 438 #endif
 439 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 440
 441 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 442                                         GENERATED_GBL_DATA_SIZE)
 443 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 444
 445 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 446 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 447
 448 /* Serial Port - controlled on board with jumper J8
 449  * open - index 2
 450  * shorted - index 1
 451  */
 452 #define CONFIG_CONS_INDEX       1
 453 #define CONFIG_SYS_NS16550_SERIAL
 454 #define CONFIG_SYS_NS16550_REG_SIZE     1
 455 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 456
 457 #define CONFIG_SYS_BAUDRATE_TABLE       \
 458         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 459
 460 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 461 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 462 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 463 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 464
 465 /* I2C */
 466 #define CONFIG_SYS_I2C
 467 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 468 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 469 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 470 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
 471 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 472 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 473 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
 474
 475 /*
 476  * RTC configuration
 477  */
 478 #define RTC
 479 #define CONFIG_RTC_DS3231               1
 480 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 481
 482 /*
 483  * RapidIO
 484  */
 485 #ifdef CONFIG_SYS_SRIO
 486 #ifdef CONFIG_SRIO1
 487 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 488 #ifdef CONFIG_PHYS_64BIT
 489 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 490 #else
 491 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 492 #endif
 493 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 494 #endif
 495
 496 #ifdef CONFIG_SRIO2
 497 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 498 #ifdef CONFIG_PHYS_64BIT
 499 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 500 #else
 501 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 502 #endif
 503 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 504 #endif
 505 #endif
 506
 507 /*
 508  * for slave u-boot IMAGE instored in master memory space,
 509  * PHYS must be aligned based on the SIZE
 510  */
 511 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 512 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 513 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 514 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 515 /*
 516  * for slave UCODE and ENV instored in master memory space,
 517  * PHYS must be aligned based on the SIZE
 518  */
 519 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 520 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 521 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 522
 523 /* slave core release by master*/
 524 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 525 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 526
 527 /*
 528  * SRIO_PCIE_BOOT - SLAVE
 529  */
 530 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 531 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 532 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 533                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 534 #endif
 535
 536 /*
 537  * eSPI - Enhanced SPI
 538  */
 539 #define CONFIG_SF_DEFAULT_SPEED         10000000
 540 #define CONFIG_SF_DEFAULT_MODE          0
 541
 542 /*
 543  * MAPLE
 544  */
 545 #ifdef CONFIG_PHYS_64BIT
 546 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
 547 #else
 548 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
 549 #endif
 550
 551 /*
 552  * General PCI
 553  * Memory space is mapped 1-1, but I/O space must start from 0.
 554  */
 555
 556 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 557 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 558 #ifdef CONFIG_PHYS_64BIT
 559 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 560 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 561 #else
 562 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 563 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 564 #endif
 565 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 566 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 567 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 568 #ifdef CONFIG_PHYS_64BIT
 569 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 570 #else
 571 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 572 #endif
 573 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 574
 575 /* Qman/Bman */
 576 #ifndef CONFIG_NOBQFMAN
 577 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 578 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
 579 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 580 #ifdef CONFIG_PHYS_64BIT
 581 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 582 #else
 583 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 584 #endif
 585 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 586 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 587 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 588 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 589 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 590 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 591                                         CONFIG_SYS_BMAN_CENA_SIZE)
 592 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 593 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 594 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
 595 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 596 #ifdef CONFIG_PHYS_64BIT
 597 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 598 #else
 599 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 600 #endif
 601 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 602 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 603 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 604 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 605 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 606 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 607                                         CONFIG_SYS_QMAN_CENA_SIZE)
 608 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 609 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 610
 611 #define CONFIG_SYS_DPAA_FMAN
 612
 613 #define CONFIG_SYS_DPAA_RMAN
 614
 615 /* Default address of microcode for the Linux Fman driver */
 616 #if defined(CONFIG_SPIFLASH)
 617 /*
 618  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 619  * env, so we got 0x110000.
 620  */
 621 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 622 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 623 #elif defined(CONFIG_SDCARD)
 624 /*
 625  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 626  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 627  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 628  */
 629 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 630 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
 631 #elif defined(CONFIG_NAND)
 632 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 633 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
 634 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 635 /*
 636  * Slave has no ucode locally, it can fetch this from remote. When implementing
 637  * in two corenet boards, slave's ucode could be stored in master's memory
 638  * space, the address can be mapped from slave TLB->slave LAW->
 639  * slave SRIO or PCIE outbound window->master inbound window->
 640  * master LAW->the ucode address in master's memory space.
 641  */
 642 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 643 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 644 #else
 645 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 646 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 647 #endif
 648 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 649 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 650 #endif /* CONFIG_NOBQFMAN */
 651
 652 #ifdef CONFIG_SYS_DPAA_FMAN
 653 #define CONFIG_FMAN_ENET
 654 #define CONFIG_PHYLIB_10G
 655 #define CONFIG_PHY_VITESSE
 656 #define CONFIG_PHY_TERANETICS
 657 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 658 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 659 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 660 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 661 #endif
 662
 663 #ifdef CONFIG_PCI
 664 #define CONFIG_PCI_INDIRECT_BRIDGE
 665
 666 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 667 #endif  /* CONFIG_PCI */
 668
 669 #ifdef CONFIG_FMAN_ENET
 670 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
 671 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
 672
 673 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
 674 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
 675 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
 676
 677 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 678 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 679 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 680 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 681
 682 #define CONFIG_MII              /* MII PHY management */
 683 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 684 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 685 #endif
 686
 687 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
 688
 689 /*
 690  * Environment
 691  */
 692 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 693 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 694
 695 /*
 696  * Command line configuration.
 697  */
 698 #define CONFIG_CMD_REGINFO
 699
 700 #ifdef CONFIG_PCI
 701 #define CONFIG_CMD_PCI
 702 #endif
 703
 704 /*
 705 * USB
 706 */
 707 #define CONFIG_HAS_FSL_DR_USB
 708
 709 #ifdef CONFIG_HAS_FSL_DR_USB
 710 #ifdef CONFIG_USB_EHCI_HCD
 711 #define CONFIG_USB_EHCI_FSL
 712 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 713 #endif
 714 #endif
 715
 716 /*
 717  * Miscellaneous configurable options
 718  */
 719 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 720 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 721 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 722 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 723 #ifdef CONFIG_CMD_KGDB
 724 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 725 #else
 726 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 727 #endif
 728 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 729 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 730 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 731
 732 /*
 733  * For booting Linux, the board info and command line data
 734  * have to be in the first 64 MB of memory, since this is
 735  * the maximum mapped by the Linux kernel during initialization.
 736  */
 737 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 738 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 739
 740 #ifdef CONFIG_CMD_KGDB
 741 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 742 #endif
 743
 744 /*
 745  * Environment Configuration
 746  */
 747 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 748 #define CONFIG_BOOTFILE         "uImage"
 749 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 750
 751 /* default location for tftp and bootm */
 752 #define CONFIG_LOADADDR         1000000
 753
 754 #define __USB_PHY_TYPE  ulpi
 755
 756 #ifdef CONFIG_ARCH_B4860
 757 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
 758                         "bank_intlv=cs0_cs1;"   \
 759                         "en_cpc:cpc2;"
 760 #else
 761 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
 762 #endif
 763
 764 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 765         HWCONFIG                                                \
 766         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 767         "netdev=eth0\0"                                         \
 768         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 769         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
 770         "tftpflash=tftpboot $loadaddr $uboot && "               \
 771         "protect off $ubootaddr +$filesize && "                 \
 772         "erase $ubootaddr +$filesize && "                       \
 773         "cp.b $loadaddr $ubootaddr $filesize && "               \
 774         "protect on $ubootaddr +$filesize && "                  \
 775         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 776         "consoledev=ttyS0\0"                                    \
 777         "ramdiskaddr=2000000\0"                                 \
 778         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
 779         "fdtaddr=1e00000\0"                                     \
 780         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
 781         "bdev=sda3\0"
 782
 783 /* For emulation this causes u-boot to jump to the start of the proof point
 784    app code automatically */
 785 #define CONFIG_PROOF_POINTS                     \
 786  "setenv bootargs root=/dev/$bdev rw "          \
 787  "console=$consoledev,$baudrate $othbootargs;"  \
 788  "cpu 1 release 0x29000000 - - -;"              \
 789  "cpu 2 release 0x29000000 - - -;"              \
 790  "cpu 3 release 0x29000000 - - -;"              \
 791  "cpu 4 release 0x29000000 - - -;"              \
 792  "cpu 5 release 0x29000000 - - -;"              \
 793  "cpu 6 release 0x29000000 - - -;"              \
 794  "cpu 7 release 0x29000000 - - -;"              \
 795  "go 0x29000000"
 796
 797 #define CONFIG_HVBOOT   \
 798  "setenv bootargs config-addr=0x60000000; "     \
 799  "bootm 0x01000000 - 0x00f00000"
 800
 801 #define CONFIG_ALU                              \
 802  "setenv bootargs root=/dev/$bdev rw "          \
 803  "console=$consoledev,$baudrate $othbootargs;"  \
 804  "cpu 1 release 0x01000000 - - -;"              \
 805  "cpu 2 release 0x01000000 - - -;"              \
 806  "cpu 3 release 0x01000000 - - -;"              \
 807  "cpu 4 release 0x01000000 - - -;"              \
 808  "cpu 5 release 0x01000000 - - -;"              \
 809  "cpu 6 release 0x01000000 - - -;"              \
 810  "cpu 7 release 0x01000000 - - -;"              \
 811  "go 0x01000000"
 812
 813 #define CONFIG_LINUX                            \
 814  "setenv bootargs root=/dev/ram rw "            \
 815  "console=$consoledev,$baudrate $othbootargs;"  \
 816  "setenv ramdiskaddr 0x02000000;"               \
 817  "setenv fdtaddr 0x01e00000;"                   \
 818  "setenv loadaddr 0x1000000;"                   \
 819  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 820
 821 #define CONFIG_HDBOOT                                   \
 822         "setenv bootargs root=/dev/$bdev rw "           \
 823         "console=$consoledev,$baudrate $othbootargs;"   \
 824         "tftp $loadaddr $bootfile;"                     \
 825         "tftp $fdtaddr $fdtfile;"                       \
 826         "bootm $loadaddr - $fdtaddr"
 827
 828 #define CONFIG_NFSBOOTCOMMAND                   \
 829         "setenv bootargs root=/dev/nfs rw "     \
 830         "nfsroot=$serverip:$rootpath "          \
 831         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 832         "console=$consoledev,$baudrate $othbootargs;"   \
 833         "tftp $loadaddr $bootfile;"             \
 834         "tftp $fdtaddr $fdtfile;"               \
 835         "bootm $loadaddr - $fdtaddr"
 836
 837 #define CONFIG_RAMBOOTCOMMAND                           \
 838         "setenv bootargs root=/dev/ram rw "             \
 839         "console=$consoledev,$baudrate $othbootargs;"   \
 840         "tftp $ramdiskaddr $ramdiskfile;"               \
 841         "tftp $loadaddr $bootfile;"                     \
 842         "tftp $fdtaddr $fdtfile;"                       \
 843         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 844
 845 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 846
 847 #include <asm/fsl_secure_boot.h>
 848
 849 #endif  /* __CONFIG_H */