include/configs/B4860QDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 /*
  10  * B4860 QDS board configuration file
  11  */
  12 #ifdef CONFIG_RAMBOOT_PBL
  13 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
  14 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
  15 #ifndef CONFIG_NAND
  16 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  17 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  18 #else
  19 #define CONFIG_SPL_FLUSH_IMAGE
  20 #define CONFIG_SPL_PAD_TO               0x40000
  21 #define CONFIG_SPL_MAX_SIZE             0x28000
  22 #define RESET_VECTOR_OFFSET             0x27FFC
  23 #define BOOT_PAGE_OFFSET                0x27000
  24 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  25 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  26 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  27 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  28 #ifdef CONFIG_SPL_BUILD
  29 #define CONFIG_SPL_SKIP_RELOCATE
  30 #define CONFIG_SPL_COMMON_INIT_DDR
  31 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  32 #endif
  33 #endif
  34 #endif
  35
  36 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  37 /* Set 1M boot space */
  38 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  39 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  40                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  41 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  42 #endif
  43
  44 /* High Level Configuration Options */
  45 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  46
  47 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  48 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  49 #endif
  50
  51 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  52 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  53 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  54 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  55 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  56
  57 #ifndef CONFIG_ARCH_B4420
  58 #define CONFIG_SYS_SRIO
  59 #define CONFIG_SRIO1                    /* SRIO port 1 */
  60 #define CONFIG_SRIO2                    /* SRIO port 2 */
  61 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  62 #endif
  63
  64 /* I2C bus multiplexer */
  65 #define I2C_MUX_PCA_ADDR                0x77
  66
  67 /* VSC Crossbar switches */
  68 #define CONFIG_VSC_CROSSBAR
  69 #define I2C_CH_DEFAULT                  0x8
  70 #define I2C_CH_VSC3316                  0xc
  71 #define I2C_CH_VSC3308                  0xd
  72
  73 #define VSC3316_TX_ADDRESS              0x70
  74 #define VSC3316_RX_ADDRESS              0x71
  75 #define VSC3308_TX_ADDRESS              0x02
  76 #define VSC3308_RX_ADDRESS              0x03
  77
  78 /* IDT clock synthesizers */
  79 #define CONFIG_IDT8T49N222A
  80 #define I2C_CH_IDT                     0x9
  81
  82 #define IDT_SERDES1_ADDRESS            0x6E
  83 #define IDT_SERDES2_ADDRESS            0x6C
  84
  85 /* Voltage monitor on channel 2*/
  86 #define I2C_MUX_CH_VOL_MONITOR          0xa
  87 #define I2C_VOL_MONITOR_ADDR            0x40
  88 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
  89 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
  90 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
  91
  92 #define CONFIG_ZM7300
  93 #define I2C_MUX_CH_DPM                  0xa
  94 #define I2C_DPM_ADDR                    0x28
  95
  96 #define CONFIG_ENV_OVERWRITE
  97
  98 #if defined(CONFIG_SPIFLASH)
  99 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 100 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 101 #define CONFIG_ENV_SECT_SIZE            0x10000
 102 #elif defined(CONFIG_SDCARD)
 103 #define CONFIG_SYS_MMC_ENV_DEV          0
 104 #define CONFIG_ENV_SIZE                 0x2000
 105 #define CONFIG_ENV_OFFSET               (512 * 1097)
 106 #elif defined(CONFIG_NAND)
 107 #define CONFIG_ENV_SIZE                 0x2000
 108 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 109 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 110 #define CONFIG_ENV_ADDR         0xffe20000
 111 #define CONFIG_ENV_SIZE         0x2000
 112 #elif defined(CONFIG_ENV_IS_NOWHERE)
 113 #define CONFIG_ENV_SIZE         0x2000
 114 #else
 115 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 116 #define CONFIG_ENV_SIZE         0x2000
 117 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 118 #endif
 119
 120 #ifndef __ASSEMBLY__
 121 unsigned long get_board_sys_clk(void);
 122 unsigned long get_board_ddr_clk(void);
 123 #endif
 124 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 125 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 126
 127 /*
 128  * These can be toggled for performance analysis, otherwise use default.
 129  */
 130 #define CONFIG_SYS_CACHE_STASHING
 131 #define CONFIG_BTB                      /* toggle branch predition */
 132 #define CONFIG_DDR_ECC
 133 #ifdef CONFIG_DDR_ECC
 134 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 135 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 136 #endif
 137
 138 #define CONFIG_ENABLE_36BIT_PHYS
 139
 140 #ifdef CONFIG_PHYS_64BIT
 141 #define CONFIG_ADDR_MAP
 142 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 143 #endif
 144
 145 #if 0
 146 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 147 #endif
 148 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 149 #define CONFIG_SYS_MEMTEST_END          0x00400000
 150
 151 /*
 152  *  Config the L3 Cache as L3 SRAM
 153  */
 154 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 155 #define CONFIG_SYS_L3_SIZE              256 << 10
 156 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 157 #ifdef CONFIG_NAND
 158 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 159 #endif
 160 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 161 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 162 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 163
 164 #ifdef CONFIG_PHYS_64BIT
 165 #define CONFIG_SYS_DCSRBAR              0xf0000000
 166 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 167 #endif
 168
 169 /* EEPROM */
 170 #define CONFIG_ID_EEPROM
 171 #define CONFIG_SYS_I2C_EEPROM_NXID
 172 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 173 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 174 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 175 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 176 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 177
 178 /*
 179  * DDR Setup
 180  */
 181 #define CONFIG_VERY_BIG_RAM
 182 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 183 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 184
 185 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 186 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 187
 188 #define CONFIG_DDR_SPD
 189 #define CONFIG_SYS_DDR_RAW_TIMING
 190
 191 #define CONFIG_SYS_SPD_BUS_NUM  0
 192 #define SPD_EEPROM_ADDRESS1     0x51
 193 #define SPD_EEPROM_ADDRESS2     0x53
 194
 195 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 196 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 197
 198 /*
 199  * IFC Definitions
 200  */
 201 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 202 #ifdef CONFIG_PHYS_64BIT
 203 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 204 #else
 205 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 206 #endif
 207
 208 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 209 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 210                                 + 0x8000000) | \
 211                                 CSPR_PORT_SIZE_16 | \
 212                                 CSPR_MSEL_NOR | \
 213                                 CSPR_V)
 214 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 215 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 216                                 CSPR_PORT_SIZE_16 | \
 217                                 CSPR_MSEL_NOR | \
 218                                 CSPR_V)
 219 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
 220 /* NOR Flash Timing Params */
 221 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
 222 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
 223                                 FTIM0_NOR_TEADC(0x04) | \
 224                                 FTIM0_NOR_TEAHC(0x20))
 225 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 226                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 227                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 228 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
 229                                 FTIM2_NOR_TCH(0x0E) | \
 230                                 FTIM2_NOR_TWPH(0x0E) | \
 231                                 FTIM2_NOR_TWP(0x1c))
 232 #define CONFIG_SYS_NOR_FTIM3    0x0
 233
 234 #define CONFIG_SYS_FLASH_QUIET_TEST
 235 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 236
 237 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 238 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 239 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 240 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 241
 242 #define CONFIG_SYS_FLASH_EMPTY_INFO
 243 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 244                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 245
 246 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 247 #define CONFIG_FSL_QIXIS_V2
 248 #define QIXIS_BASE              0xffdf0000
 249 #ifdef CONFIG_PHYS_64BIT
 250 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 251 #else
 252 #define QIXIS_BASE_PHYS         QIXIS_BASE
 253 #endif
 254 #define QIXIS_LBMAP_SWITCH              0x01
 255 #define QIXIS_LBMAP_MASK                0x0f
 256 #define QIXIS_LBMAP_SHIFT               0
 257 #define QIXIS_LBMAP_DFLTBANK            0x00
 258 #define QIXIS_LBMAP_ALTBANK             0x02
 259 #define QIXIS_RST_CTL_RESET             0x31
 260 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 261 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 262 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 263
 264 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 265 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 266                                 | CSPR_PORT_SIZE_8 \
 267                                 | CSPR_MSEL_GPCM \
 268                                 | CSPR_V)
 269 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 270 #define CONFIG_SYS_CSOR3        0x0
 271 /* QIXIS Timing parameters for IFC CS3 */
 272 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 273                                         FTIM0_GPCM_TEADC(0x0e) | \
 274                                         FTIM0_GPCM_TEAHC(0x0e))
 275 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 276                                         FTIM1_GPCM_TRAD(0x1f))
 277 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 278                                         FTIM2_GPCM_TCH(0x8) | \
 279                                         FTIM2_GPCM_TWP(0x1f))
 280 #define CONFIG_SYS_CS3_FTIM3            0x0
 281
 282 /* NAND Flash on IFC */
 283 #define CONFIG_NAND_FSL_IFC
 284 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 285 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 286 #define CONFIG_SYS_NAND_BASE            0xff800000
 287 #ifdef CONFIG_PHYS_64BIT
 288 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 289 #else
 290 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 291 #endif
 292
 293 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 294 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 295                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 296                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 297                                 | CSPR_V)
 298 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 299
 300 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 301                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 302                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 303                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 304                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 305                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 306                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 307
 308 #define CONFIG_SYS_NAND_ONFI_DETECTION
 309
 310 /* ONFI NAND Flash mode0 Timing Params */
 311 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 312                                         FTIM0_NAND_TWP(0x18)   | \
 313                                         FTIM0_NAND_TWCHT(0x07) | \
 314                                         FTIM0_NAND_TWH(0x0a))
 315 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 316                                         FTIM1_NAND_TWBE(0x39)  | \
 317                                         FTIM1_NAND_TRR(0x0e)   | \
 318                                         FTIM1_NAND_TRP(0x18))
 319 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 320                                         FTIM2_NAND_TREH(0x0a) | \
 321                                         FTIM2_NAND_TWHRE(0x1e))
 322 #define CONFIG_SYS_NAND_FTIM3           0x0
 323
 324 #define CONFIG_SYS_NAND_DDR_LAW         11
 325
 326 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 327 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 328
 329 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 330
 331 #if defined(CONFIG_NAND)
 332 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 333 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 334 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 335 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 336 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 337 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 338 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 339 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 340 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 341 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 342 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 343 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 344 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 345 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 346 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 347 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 348 #else
 349 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 350 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 351 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 352 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 353 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 354 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 355 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 356 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 357 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 358 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 359 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 360 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 361 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 362 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 363 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 364 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 365 #endif
 366 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 367 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 368 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 369 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 370 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 371 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 372 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 373 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 374
 375 #ifdef CONFIG_SPL_BUILD
 376 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 377 #else
 378 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 379 #endif
 380
 381 #if defined(CONFIG_RAMBOOT_PBL)
 382 #define CONFIG_SYS_RAMBOOT
 383 #endif
 384
 385 #define CONFIG_HWCONFIG
 386
 387 /* define to use L1 as initial stack */
 388 #define CONFIG_L1_INIT_RAM
 389 #define CONFIG_SYS_INIT_RAM_LOCK
 390 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 391 #ifdef CONFIG_PHYS_64BIT
 392 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 393 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 394 /* The assembler doesn't like typecast */
 395 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 396         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 397           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 398 #else
 399 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 400 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 401 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 402 #endif
 403 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 404
 405 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 406                                         GENERATED_GBL_DATA_SIZE)
 407 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 408
 409 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 410 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 411
 412 /* Serial Port - controlled on board with jumper J8
 413  * open - index 2
 414  * shorted - index 1
 415  */
 416 #define CONFIG_SYS_NS16550_SERIAL
 417 #define CONFIG_SYS_NS16550_REG_SIZE     1
 418 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 419
 420 #define CONFIG_SYS_BAUDRATE_TABLE       \
 421         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 422
 423 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 424 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 425 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 426 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 427
 428 /* I2C */
 429 #define CONFIG_SYS_I2C
 430 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 431 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 432 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 433 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
 434 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 435 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 436 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
 437
 438 /*
 439  * RTC configuration
 440  */
 441 #define RTC
 442 #define CONFIG_RTC_DS3231               1
 443 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 444
 445 /*
 446  * RapidIO
 447  */
 448 #ifdef CONFIG_SYS_SRIO
 449 #ifdef CONFIG_SRIO1
 450 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 451 #ifdef CONFIG_PHYS_64BIT
 452 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 453 #else
 454 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 455 #endif
 456 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 457 #endif
 458
 459 #ifdef CONFIG_SRIO2
 460 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 461 #ifdef CONFIG_PHYS_64BIT
 462 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 463 #else
 464 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 465 #endif
 466 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 467 #endif
 468 #endif
 469
 470 /*
 471  * for slave u-boot IMAGE instored in master memory space,
 472  * PHYS must be aligned based on the SIZE
 473  */
 474 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 475 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 476 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 477 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 478 /*
 479  * for slave UCODE and ENV instored in master memory space,
 480  * PHYS must be aligned based on the SIZE
 481  */
 482 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 483 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 484 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 485
 486 /* slave core release by master*/
 487 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 488 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 489
 490 /*
 491  * SRIO_PCIE_BOOT - SLAVE
 492  */
 493 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 494 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 495 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 496                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 497 #endif
 498
 499 /*
 500  * eSPI - Enhanced SPI
 501  */
 502
 503 /*
 504  * MAPLE
 505  */
 506 #ifdef CONFIG_PHYS_64BIT
 507 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
 508 #else
 509 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
 510 #endif
 511
 512 /*
 513  * General PCI
 514  * Memory space is mapped 1-1, but I/O space must start from 0.
 515  */
 516
 517 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 518 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 519 #ifdef CONFIG_PHYS_64BIT
 520 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 521 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 522 #else
 523 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 524 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 525 #endif
 526 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 527 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 528 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 529 #ifdef CONFIG_PHYS_64BIT
 530 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 531 #else
 532 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 533 #endif
 534 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 535
 536 /* Qman/Bman */
 537 #ifndef CONFIG_NOBQFMAN
 538 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
 539 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 540 #ifdef CONFIG_PHYS_64BIT
 541 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 542 #else
 543 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 544 #endif
 545 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 546 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 547 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 548 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 549 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 550 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 551                                         CONFIG_SYS_BMAN_CENA_SIZE)
 552 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 553 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 554 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
 555 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 556 #ifdef CONFIG_PHYS_64BIT
 557 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 558 #else
 559 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 560 #endif
 561 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 562 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 563 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 564 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 565 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 566 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 567                                         CONFIG_SYS_QMAN_CENA_SIZE)
 568 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 569 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 570
 571 #define CONFIG_SYS_DPAA_FMAN
 572
 573 #define CONFIG_SYS_DPAA_RMAN
 574
 575 /* Default address of microcode for the Linux Fman driver */
 576 #if defined(CONFIG_SPIFLASH)
 577 /*
 578  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 579  * env, so we got 0x110000.
 580  */
 581 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 582 #elif defined(CONFIG_SDCARD)
 583 /*
 584  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 585  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 586  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 587  */
 588 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
 589 #elif defined(CONFIG_NAND)
 590 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
 591 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 592 /*
 593  * Slave has no ucode locally, it can fetch this from remote. When implementing
 594  * in two corenet boards, slave's ucode could be stored in master's memory
 595  * space, the address can be mapped from slave TLB->slave LAW->
 596  * slave SRIO or PCIE outbound window->master inbound window->
 597  * master LAW->the ucode address in master's memory space.
 598  */
 599 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 600 #else
 601 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 602 #endif
 603 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 604 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 605 #endif /* CONFIG_NOBQFMAN */
 606
 607 #ifdef CONFIG_SYS_DPAA_FMAN
 608 #define CONFIG_PHYLIB_10G
 609 #define CONFIG_PHY_VITESSE
 610 #define CONFIG_PHY_TERANETICS
 611 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 612 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 613 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 614 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 615 #endif
 616
 617 #ifdef CONFIG_PCI
 618 #define CONFIG_PCI_INDIRECT_BRIDGE
 619
 620 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 621 #endif  /* CONFIG_PCI */
 622
 623 #ifdef CONFIG_FMAN_ENET
 624 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
 625 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
 626
 627 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
 628 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
 629 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
 630
 631 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 632 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 633 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 634 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 635
 636 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 637 #endif
 638
 639 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
 640
 641 /*
 642  * Environment
 643  */
 644 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 645 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 646
 647 /*
 648 * USB
 649 */
 650 #define CONFIG_HAS_FSL_DR_USB
 651
 652 #ifdef CONFIG_HAS_FSL_DR_USB
 653 #ifdef CONFIG_USB_EHCI_HCD
 654 #define CONFIG_USB_EHCI_FSL
 655 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 656 #endif
 657 #endif
 658
 659 /*
 660  * Miscellaneous configurable options
 661  */
 662 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 663
 664 /*
 665  * For booting Linux, the board info and command line data
 666  * have to be in the first 64 MB of memory, since this is
 667  * the maximum mapped by the Linux kernel during initialization.
 668  */
 669 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 670 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 671
 672 #ifdef CONFIG_CMD_KGDB
 673 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 674 #endif
 675
 676 /*
 677  * Environment Configuration
 678  */
 679 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 680 #define CONFIG_BOOTFILE         "uImage"
 681 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 682
 683 /* default location for tftp and bootm */
 684 #define CONFIG_LOADADDR         1000000
 685
 686 #define __USB_PHY_TYPE  ulpi
 687
 688 #ifdef CONFIG_ARCH_B4860
 689 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
 690                         "bank_intlv=cs0_cs1;"   \
 691                         "en_cpc:cpc2;"
 692 #else
 693 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
 694 #endif
 695
 696 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 697         HWCONFIG                                                \
 698         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 699         "netdev=eth0\0"                                         \
 700         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 701         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
 702         "tftpflash=tftpboot $loadaddr $uboot && "               \
 703         "protect off $ubootaddr +$filesize && "                 \
 704         "erase $ubootaddr +$filesize && "                       \
 705         "cp.b $loadaddr $ubootaddr $filesize && "               \
 706         "protect on $ubootaddr +$filesize && "                  \
 707         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 708         "consoledev=ttyS0\0"                                    \
 709         "ramdiskaddr=2000000\0"                                 \
 710         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
 711         "fdtaddr=1e00000\0"                                     \
 712         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
 713         "bdev=sda3\0"
 714
 715 /* For emulation this causes u-boot to jump to the start of the proof point
 716    app code automatically */
 717 #define CONFIG_PROOF_POINTS                     \
 718  "setenv bootargs root=/dev/$bdev rw "          \
 719  "console=$consoledev,$baudrate $othbootargs;"  \
 720  "cpu 1 release 0x29000000 - - -;"              \
 721  "cpu 2 release 0x29000000 - - -;"              \
 722  "cpu 3 release 0x29000000 - - -;"              \
 723  "cpu 4 release 0x29000000 - - -;"              \
 724  "cpu 5 release 0x29000000 - - -;"              \
 725  "cpu 6 release 0x29000000 - - -;"              \
 726  "cpu 7 release 0x29000000 - - -;"              \
 727  "go 0x29000000"
 728
 729 #define CONFIG_HVBOOT   \
 730  "setenv bootargs config-addr=0x60000000; "     \
 731  "bootm 0x01000000 - 0x00f00000"
 732
 733 #define CONFIG_ALU                              \
 734  "setenv bootargs root=/dev/$bdev rw "          \
 735  "console=$consoledev,$baudrate $othbootargs;"  \
 736  "cpu 1 release 0x01000000 - - -;"              \
 737  "cpu 2 release 0x01000000 - - -;"              \
 738  "cpu 3 release 0x01000000 - - -;"              \
 739  "cpu 4 release 0x01000000 - - -;"              \
 740  "cpu 5 release 0x01000000 - - -;"              \
 741  "cpu 6 release 0x01000000 - - -;"              \
 742  "cpu 7 release 0x01000000 - - -;"              \
 743  "go 0x01000000"
 744
 745 #define CONFIG_LINUX                            \
 746  "setenv bootargs root=/dev/ram rw "            \
 747  "console=$consoledev,$baudrate $othbootargs;"  \
 748  "setenv ramdiskaddr 0x02000000;"               \
 749  "setenv fdtaddr 0x01e00000;"                   \
 750  "setenv loadaddr 0x1000000;"                   \
 751  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 752
 753 #define CONFIG_HDBOOT                                   \
 754         "setenv bootargs root=/dev/$bdev rw "           \
 755         "console=$consoledev,$baudrate $othbootargs;"   \
 756         "tftp $loadaddr $bootfile;"                     \
 757         "tftp $fdtaddr $fdtfile;"                       \
 758         "bootm $loadaddr - $fdtaddr"
 759
 760 #define CONFIG_NFSBOOTCOMMAND                   \
 761         "setenv bootargs root=/dev/nfs rw "     \
 762         "nfsroot=$serverip:$rootpath "          \
 763         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 764         "console=$consoledev,$baudrate $othbootargs;"   \
 765         "tftp $loadaddr $bootfile;"             \
 766         "tftp $fdtaddr $fdtfile;"               \
 767         "bootm $loadaddr - $fdtaddr"
 768
 769 #define CONFIG_RAMBOOTCOMMAND                           \
 770         "setenv bootargs root=/dev/ram rw "             \
 771         "console=$consoledev,$baudrate $othbootargs;"   \
 772         "tftp $ramdiskaddr $ramdiskfile;"               \
 773         "tftp $loadaddr $bootfile;"                     \
 774         "tftp $fdtaddr $fdtfile;"                       \
 775         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 776
 777 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 778
 779 #include <asm/fsl_secure_boot.h>
 780
 781 #endif  /* __CONFIG_H */