1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Nexell Co., Ltd.
5 * Author: junghyun, kim <jhkim@nexell.co.kr>
8 #include <linux/types.h>
11 #include "s5pxx18_soc_mlc.h"
14 struct nx_mlc_register_set *pregister;
15 } __g_module_variables[NUMBER_OF_MLC_MODULE] = { { NULL, },};
17 int nx_mlc_initialize(void)
23 for (i = 0; i < NUMBER_OF_MLC_MODULE; i++)
24 __g_module_variables[i].pregister = NULL;
30 u32 nx_mlc_get_physical_address(u32 module_index)
32 const u32 physical_addr[] = PHY_BASEADDR_MLC_LIST;
34 return physical_addr[module_index];
37 void nx_mlc_set_base_address(u32 module_index, void *base_address)
39 __g_module_variables[module_index].pregister =
40 (struct nx_mlc_register_set *)base_address;
43 void *nx_mlc_get_base_address(u32 module_index)
45 return (void *)__g_module_variables[module_index].pregister;
48 void nx_mlc_set_clock_pclk_mode(u32 module_index, enum nx_pclkmode mode)
50 const u32 pclkmode_pos = 3;
53 register u32 regvalue;
54 register struct nx_mlc_register_set *pregister;
56 pregister = __g_module_variables[module_index].pregister;
58 case nx_pclkmode_dynamic:
61 case nx_pclkmode_always:
67 regvalue = pregister->mlcclkenb;
68 regvalue &= ~(1ul << pclkmode_pos);
69 regvalue |= (clkmode & 0x01) << pclkmode_pos;
71 writel(regvalue, &pregister->mlcclkenb);
74 enum nx_pclkmode nx_mlc_get_clock_pclk_mode(u32 module_index)
76 const u32 pclkmode_pos = 3;
78 if (__g_module_variables[module_index].pregister->mlcclkenb &
79 (1ul << pclkmode_pos)) {
80 return nx_pclkmode_always;
82 return nx_pclkmode_dynamic;
85 void nx_mlc_set_clock_bclk_mode(u32 module_index, enum nx_bclkmode mode)
87 register u32 regvalue;
88 register struct nx_mlc_register_set *pregister;
91 pregister = __g_module_variables[module_index].pregister;
93 case nx_bclkmode_disable:
96 case nx_bclkmode_dynamic:
99 case nx_bclkmode_always:
105 regvalue = pregister->mlcclkenb;
107 regvalue |= clkmode & 0x3;
109 writel(regvalue, &pregister->mlcclkenb);
112 enum nx_bclkmode nx_mlc_get_clock_bclk_mode(u32 module_index)
114 const u32 bclkmode = 3ul << 0;
116 switch (__g_module_variables[module_index].pregister->mlcclkenb &
119 return nx_bclkmode_disable;
121 return nx_bclkmode_dynamic;
123 return nx_bclkmode_always;
125 return nx_bclkmode_disable;
128 void nx_mlc_set_top_power_mode(u32 module_index, int bpower)
130 const u32 pixelbuffer_pwd_pos = 11;
131 const u32 pixelbuffer_pwd_mask = 1ul << pixelbuffer_pwd_pos;
132 const u32 dittyflag_mask = 1ul << 3;
133 register struct nx_mlc_register_set *pregister;
134 register u32 regvalue;
136 pregister = __g_module_variables[module_index].pregister;
137 regvalue = pregister->mlccontrolt;
138 regvalue &= ~(pixelbuffer_pwd_mask | dittyflag_mask);
139 regvalue |= (bpower << pixelbuffer_pwd_pos);
141 writel(regvalue, &pregister->mlccontrolt);
144 int nx_mlc_get_top_power_mode(u32 module_index)
146 const u32 pixelbuffer_pwd_pos = 11;
147 const u32 pixelbuffer_pwd_mask = 1ul << pixelbuffer_pwd_pos;
149 return (int)((__g_module_variables[module_index].pregister->mlccontrolt
150 & pixelbuffer_pwd_mask) >>
151 pixelbuffer_pwd_pos);
154 void nx_mlc_set_top_sleep_mode(u32 module_index, int bsleep)
156 const u32 pixelbuffer_sld_pos = 10;
157 const u32 pixelbuffer_sld_mask = 1ul << pixelbuffer_sld_pos;
158 const u32 dittyflag_mask = 1ul << 3;
159 register struct nx_mlc_register_set *pregister;
160 register u32 regvalue;
162 bsleep = (int)((u32)bsleep ^ 1);
163 pregister = __g_module_variables[module_index].pregister;
164 regvalue = pregister->mlccontrolt;
165 regvalue &= ~(pixelbuffer_sld_mask | dittyflag_mask);
166 regvalue |= (bsleep << pixelbuffer_sld_pos);
168 writel(regvalue, &pregister->mlccontrolt);
171 int nx_mlc_get_top_sleep_mode(u32 module_index)
173 const u32 pixelbuffer_sld_pos = 11;
174 const u32 pixelbuffer_sld_mask = 1ul << pixelbuffer_sld_pos;
176 return (int)(((__g_module_variables[module_index].pregister->mlccontrolt
177 & pixelbuffer_sld_mask) >>
178 pixelbuffer_sld_pos) ^ 0x01);
181 void nx_mlc_set_top_dirty_flag(u32 module_index)
183 const u32 dirtyflag = 1ul << 3;
184 register struct nx_mlc_register_set *pregister;
185 register u32 regvalue;
187 pregister = __g_module_variables[module_index].pregister;
188 regvalue = pregister->mlccontrolt;
189 regvalue |= dirtyflag;
191 writel(regvalue, &pregister->mlccontrolt);
194 int nx_mlc_get_top_dirty_flag(u32 module_index)
196 const u32 dirtyflag_pos = 3;
197 const u32 dirtyflag_mask = 1ul << dirtyflag_pos;
199 return (int)((readl(&__g_module_variables[module_index]
200 .pregister->mlccontrolt) &
201 dirtyflag_mask) >> dirtyflag_pos);
204 void nx_mlc_set_mlc_enable(u32 module_index, int benb)
206 const u32 mlcenb_pos = 1;
207 const u32 mlcenb_mask = 1ul << mlcenb_pos;
208 const u32 dirtyflag_pos = 3;
209 const u32 dirtyflag_mask = 1ul << dirtyflag_pos;
210 register u32 regvalue;
211 register struct nx_mlc_register_set *pregister;
213 pregister = __g_module_variables[module_index].pregister;
214 regvalue = pregister->mlccontrolt;
215 regvalue &= ~(mlcenb_mask | dirtyflag_mask);
216 regvalue |= (benb << mlcenb_pos);
218 writel(regvalue, &pregister->mlccontrolt);
221 int nx_mlc_get_mlc_enable(u32 module_index)
223 const u32 mlcenb_pos = 1;
224 const u32 mlcenb_mask = 1ul << mlcenb_pos;
226 return (int)((__g_module_variables[module_index].pregister->mlccontrolt
227 & mlcenb_mask) >> mlcenb_pos);
230 void nx_mlc_set_field_enable(u32 module_index, int benb)
232 const u32 fieldenb_pos = 0;
233 const u32 fieldenb_mask = 1ul << fieldenb_pos;
234 const u32 dirtyflag_pos = 3;
235 const u32 dirtyflag_mask = 1ul << dirtyflag_pos;
236 register u32 regvalue;
237 register struct nx_mlc_register_set *pregister;
239 pregister = __g_module_variables[module_index].pregister;
240 regvalue = pregister->mlccontrolt;
241 regvalue &= ~(fieldenb_mask | dirtyflag_mask);
242 regvalue |= (benb << fieldenb_pos);
244 writel(regvalue, &pregister->mlccontrolt);
247 int nx_mlc_get_field_enable(u32 module_index)
249 const u32 fieldenb_pos = 0;
250 const u32 fieldenb_mask = 1ul << fieldenb_pos;
252 return (int)(__g_module_variables[module_index].pregister->mlccontrolt &
256 void nx_mlc_set_layer_priority(u32 module_index, enum nx_mlc_priority priority)
258 const u32 priority_pos = 8;
259 const u32 priority_mask = 0x03 << priority_pos;
260 const u32 dirtyflag_pos = 3;
261 const u32 dirtyflag_mask = 1ul << dirtyflag_pos;
262 register struct nx_mlc_register_set *pregister;
263 register u32 regvalue;
265 pregister = __g_module_variables[module_index].pregister;
266 regvalue = pregister->mlccontrolt;
267 regvalue &= ~(priority_mask | dirtyflag_mask);
268 regvalue |= (priority << priority_pos);
270 writel(regvalue, &pregister->mlccontrolt);
273 void nx_mlc_set_screen_size(u32 module_index, u32 width, u32 height)
275 register struct nx_mlc_register_set *pregister;
276 register u32 regvalue;
278 pregister = __g_module_variables[module_index].pregister;
279 regvalue = ((height - 1) << 16) | (width - 1);
281 writel(regvalue, &pregister->mlcscreensize);
284 void nx_mlc_get_screen_size(u32 module_index, u32 *pwidth, u32 *pheight)
286 register struct nx_mlc_register_set *pregister;
288 pregister = __g_module_variables[module_index].pregister;
291 *pwidth = (pregister->mlcscreensize & 0x0fff) + 1;
294 *pheight = ((pregister->mlcscreensize >> 16) & 0x0fff) + 1;
297 void nx_mlc_set_background(u32 module_index, u32 color)
299 register struct nx_mlc_register_set *pregister;
301 pregister = __g_module_variables[module_index].pregister;
302 writel(color, &pregister->mlcbgcolor);
305 void nx_mlc_set_dirty_flag(u32 module_index, u32 layer)
307 register struct nx_mlc_register_set *pregister;
308 register u32 regvalue;
309 const u32 dirtyflg_mask = 1ul << 4;
311 pregister = __g_module_variables[module_index].pregister;
312 if (layer == 0 || layer == 1) {
313 regvalue = pregister->mlcrgblayer[layer].mlccontrol;
314 regvalue |= dirtyflg_mask;
316 writel(regvalue, &pregister->mlcrgblayer[layer].mlccontrol);
317 } else if (layer == 3) {
318 regvalue = pregister->mlcvideolayer.mlccontrol;
319 regvalue |= dirtyflg_mask;
321 writel(regvalue, &pregister->mlcvideolayer.mlccontrol);
325 int nx_mlc_get_dirty_flag(u32 module_index, u32 layer)
327 const u32 dirtyflg_pos = 4;
328 const u32 dirtyflg_mask = 1ul << dirtyflg_pos;
330 if (layer == 0 || layer == 1) {
331 return (int)((__g_module_variables[module_index]
332 .pregister->mlcrgblayer[layer]
333 .mlccontrol & dirtyflg_mask) >> dirtyflg_pos);
334 } else if (layer == 2) {
335 return (int)((__g_module_variables[module_index]
336 .pregister->mlcrgblayer2.mlccontrol &
337 dirtyflg_mask) >> dirtyflg_pos);
338 } else if (layer == 3) {
339 return (int)((__g_module_variables[module_index]
340 .pregister->mlcvideolayer.mlccontrol &
341 dirtyflg_mask) >> dirtyflg_pos);
346 void nx_mlc_set_layer_enable(u32 module_index, u32 layer, int benb)
348 const u32 layerenb_pos = 5;
349 const u32 layerenb_mask = 0x01 << layerenb_pos;
350 const u32 dirtyflag_pos = 4;
351 const u32 dirtyflag_mask = 1ul << dirtyflag_pos;
352 register u32 regvalue;
353 register struct nx_mlc_register_set *pregister;
355 pregister = __g_module_variables[module_index].pregister;
356 if (layer == 0 || layer == 1) {
357 regvalue = pregister->mlcrgblayer[layer].mlccontrol;
358 regvalue &= ~(layerenb_mask | dirtyflag_mask);
359 regvalue |= (benb << layerenb_pos);
361 writel(regvalue, &pregister->mlcrgblayer[layer].mlccontrol);
362 } else if (layer == 3) {
363 regvalue = pregister->mlcvideolayer.mlccontrol;
364 regvalue &= ~(layerenb_mask | dirtyflag_mask);
365 regvalue |= (benb << layerenb_pos);
367 writel(regvalue, &pregister->mlcvideolayer.mlccontrol);
371 int nx_mlc_get_layer_enable(u32 module_index, u32 layer)
373 const u32 layerenb_pos = 5;
374 const u32 layerenb_mask = 0x01 << layerenb_pos;
376 if (layer == 0 || layer == 1) {
377 return (int)((__g_module_variables[module_index]
378 .pregister->mlcrgblayer[layer]
379 .mlccontrol & layerenb_mask) >> layerenb_pos);
380 } else if (layer == 3) {
381 return (int)((__g_module_variables[module_index]
382 .pregister->mlcvideolayer.mlccontrol &
383 layerenb_mask) >> layerenb_pos);
388 void nx_mlc_set_lock_size(u32 module_index, u32 layer, u32 locksize)
390 const u32 locksize_mask = 3ul << 12;
391 const u32 dirtyflag_pos = 4;
392 const u32 dirtyflag_mask = 1ul << dirtyflag_pos;
393 register struct nx_mlc_register_set *pregister;
394 register u32 regvalue;
396 pregister = __g_module_variables[module_index].pregister;
398 if (layer == 0 || layer == 1) {
399 regvalue = pregister->mlcrgblayer[layer].mlccontrol;
400 regvalue &= ~(locksize_mask | dirtyflag_mask);
401 regvalue |= (locksize << 12);
403 writel(regvalue, &pregister->mlcrgblayer[layer].mlccontrol);
407 void nx_mlc_set_alpha_blending(u32 module_index, u32 layer, int benb, u32 alpha)
409 const u32 blendenb_pos = 2;
410 const u32 blendenb_mask = 0x01 << blendenb_pos;
411 const u32 dirtyflag_pos = 4;
412 const u32 dirtyflag_mask = 1ul << dirtyflag_pos;
413 const u32 alpha_pos = 28;
414 const u32 alpha_mask = 0xf << alpha_pos;
415 register u32 regvalue;
416 register struct nx_mlc_register_set *pregister;
418 pregister = __g_module_variables[module_index].pregister;
419 if (layer == 0 || layer == 1) {
420 regvalue = pregister->mlcrgblayer[layer].mlccontrol;
421 regvalue &= ~(blendenb_mask | dirtyflag_mask);
422 regvalue |= (benb << blendenb_pos);
424 writel(regvalue, &pregister->mlcrgblayer[layer].mlccontrol);
425 regvalue = pregister->mlcrgblayer[layer].mlctpcolor;
426 regvalue &= ~alpha_mask;
427 regvalue |= alpha << alpha_pos;
429 writel(regvalue, &pregister->mlcrgblayer[layer].mlctpcolor);
430 } else if (layer == 3) {
431 regvalue = pregister->mlcvideolayer.mlccontrol;
432 regvalue &= ~(blendenb_mask | dirtyflag_mask);
433 regvalue |= (benb << blendenb_pos);
435 writel(regvalue, &pregister->mlcvideolayer.mlccontrol);
437 writel(alpha << alpha_pos,
438 &pregister->mlcvideolayer.mlctpcolor);
442 void nx_mlc_set_transparency(u32 module_index, u32 layer, int benb, u32 color)
444 const u32 tpenb_pos = 0;
445 const u32 tpenb_mask = 0x01 << tpenb_pos;
446 const u32 dirtyflag_pos = 4;
447 const u32 dirtyflag_mask = 1ul << dirtyflag_pos;
448 const u32 tpcolor_pos = 0;
449 const u32 tpcolor_mask = ((1 << 24) - 1) << tpcolor_pos;
450 register u32 regvalue;
451 register struct nx_mlc_register_set *pregister;
453 pregister = __g_module_variables[module_index].pregister;
454 if (layer == 0 || layer == 1) {
455 regvalue = pregister->mlcrgblayer[layer].mlccontrol;
456 regvalue &= ~(tpenb_mask | dirtyflag_mask);
457 regvalue |= (benb << tpenb_pos);
459 writel(regvalue, &pregister->mlcrgblayer[layer].mlccontrol);
460 regvalue = pregister->mlcrgblayer[layer].mlctpcolor;
461 regvalue &= ~tpcolor_mask;
462 regvalue |= (color & tpcolor_mask);
464 writel(regvalue, &pregister->mlcrgblayer[layer].mlctpcolor);
468 void nx_mlc_set_color_inversion(u32 module_index, u32 layer, int benb,
471 const u32 invenb_pos = 1;
472 const u32 invenb_mask = 0x01 << invenb_pos;
473 const u32 dirtyflag_pos = 4;
474 const u32 dirtyflag_mask = 1ul << dirtyflag_pos;
475 const u32 invcolor_pos = 0;
476 const u32 invcolor_mask = ((1 << 24) - 1) << invcolor_pos;
477 register u32 regvalue;
478 register struct nx_mlc_register_set *pregister;
480 pregister = __g_module_variables[module_index].pregister;
481 if (layer == 0 || layer == 1) {
482 regvalue = pregister->mlcrgblayer[layer].mlccontrol;
483 regvalue &= ~(invenb_mask | dirtyflag_mask);
484 regvalue |= (benb << invenb_pos);
486 writel(regvalue, &pregister->mlcrgblayer[layer].mlccontrol);
487 regvalue = pregister->mlcrgblayer[layer].mlcinvcolor;
488 regvalue &= ~invcolor_mask;
489 regvalue |= (color & invcolor_mask);
491 writel(regvalue, &pregister->mlcrgblayer[layer].mlcinvcolor);
495 u32 nx_mlc_get_extended_color(u32 module_index, u32 color,
496 enum nx_mlc_rgbfmt format)
512 case nx_mlc_rgbfmt_r5g6b5:
520 case nx_mlc_rgbfmt_b5g6r5:
528 case nx_mlc_rgbfmt_x1r5g5b5:
529 case nx_mlc_rgbfmt_a1r5g5b5:
537 case nx_mlc_rgbfmt_x1b5g5r5:
538 case nx_mlc_rgbfmt_a1b5g5r5:
546 case nx_mlc_rgbfmt_x4r4g4b4:
547 case nx_mlc_rgbfmt_a4r4g4b4:
555 case nx_mlc_rgbfmt_x4b4g4r4:
556 case nx_mlc_rgbfmt_a4b4g4r4:
564 case nx_mlc_rgbfmt_x8r3g3b2:
565 case nx_mlc_rgbfmt_a8r3g3b2:
573 case nx_mlc_rgbfmt_x8b3g3r2:
574 case nx_mlc_rgbfmt_a8b3g3r2:
582 case nx_mlc_rgbfmt_r8g8b8:
583 case nx_mlc_rgbfmt_a8r8g8b8:
591 case nx_mlc_rgbfmt_b8g8r8:
592 case nx_mlc_rgbfmt_a8b8g8r8:
603 for (i = 0; i < 3; i++) {
604 rgb[i] = (color >> bp[i]) & ((u32)(1 << bw[i]) - 1);
609 rgb[i] |= (rgb[i] >> fill);
615 return (rgb[0] << 16) | (rgb[1] << 8) | (rgb[2] << 0);
618 void nx_mlc_set_format_rgb(u32 module_index, u32 layer,
619 enum nx_mlc_rgbfmt format)
621 const u32 dirtyflag_pos = 4;
622 const u32 dirtyflag_mask = 1ul << dirtyflag_pos;
623 const u32 format_mask = 0xffff0000ul;
624 register u32 regvalue;
625 register struct nx_mlc_register_set *pregister;
627 pregister = __g_module_variables[module_index].pregister;
628 if (layer == 0 || layer == 1) {
629 regvalue = pregister->mlcrgblayer[layer].mlccontrol;
630 regvalue &= ~(format_mask | dirtyflag_mask);
631 regvalue |= (u32)format;
633 writel(regvalue, &pregister->mlcrgblayer[layer].mlccontrol);
637 void nx_mlc_set_format_yuv(u32 module_index, enum nx_mlc_yuvfmt format)
639 const u32 format_mask = 0xffff0000ul;
641 register struct nx_mlc_register_set *pregister;
643 pregister = __g_module_variables[module_index].pregister;
644 temp = pregister->mlcvideolayer.mlccontrol;
645 temp &= ~format_mask;
648 writel(temp, &pregister->mlcvideolayer.mlccontrol);
651 void nx_mlc_set_position(u32 module_index, u32 layer, s32 sx, s32 sy,
654 register struct nx_mlc_register_set *pregister;
656 pregister = __g_module_variables[module_index].pregister;
657 if (layer == 0 || layer == 1) {
658 writel((((u32)sx & 0xffful) << 16) | ((u32)ex & 0xffful),
659 &pregister->mlcrgblayer[layer].mlcleftright);
661 writel((((u32)sy & 0xffful) << 16) | ((u32)ey & 0xffful),
662 &pregister->mlcrgblayer[layer].mlctopbottom);
663 } else if (layer == 2) {
664 writel((((u32)sx & 0xffful) << 16) | ((u32)ex & 0xffful),
665 &pregister->mlcrgblayer2.mlcleftright);
667 writel((((u32)sy & 0xffful) << 16) | ((u32)ey & 0xffful),
668 &pregister->mlcrgblayer2.mlctopbottom);
669 } else if (layer == 3) {
670 writel((((u32)sx & 0xffful) << 16) | ((u32)ex & 0xffful),
671 &pregister->mlcvideolayer.mlcleftright);
673 writel((((u32)sy & 0xffful) << 16) | ((u32)ey & 0xffful),
674 &pregister->mlcvideolayer.mlctopbottom);
678 void nx_mlc_set_dither_enable_when_using_gamma(u32 module_index, int benable)
680 const u32 ditherenb_bitpos = 0;
681 const u32 ditherenb_mask = 1 << ditherenb_bitpos;
682 register struct nx_mlc_register_set *pregister;
683 register u32 read_value;
685 pregister = __g_module_variables[module_index].pregister;
686 read_value = pregister->mlcgammacont;
687 read_value &= ~ditherenb_mask;
688 read_value |= ((u32)benable << ditherenb_bitpos);
690 writel(read_value, &pregister->mlcgammacont);
693 int nx_mlc_get_dither_enable_when_using_gamma(u32 module_index)
695 const u32 ditherenb_bitpos = 0;
696 const u32 ditherenb_mask = 1 << ditherenb_bitpos;
698 return (int)(__g_module_variables[module_index].pregister->mlcgammacont
702 void nx_mlc_set_gamma_priority(u32 module_index, int bvideolayer)
704 const u32 alphaselect_bitpos = 5;
705 const u32 alphaselect_mask = 1 << alphaselect_bitpos;
706 register struct nx_mlc_register_set *pregister;
707 register u32 read_value;
709 pregister = __g_module_variables[module_index].pregister;
710 read_value = pregister->mlcgammacont;
711 read_value &= ~alphaselect_mask;
712 read_value |= ((u32)bvideolayer << alphaselect_bitpos);
714 writel(read_value, &pregister->mlcgammacont);
717 int nx_mlc_get_gamma_priority(u32 module_index)
719 const u32 alphaselect_bitpos = 5;
720 const u32 alphaselect_mask = 1 << alphaselect_bitpos;
722 return (int)((__g_module_variables[module_index].pregister->mlcgammacont
723 & alphaselect_mask) >> alphaselect_bitpos);
726 void nx_mlc_set_rgblayer_invalid_position(u32 module_index, u32 layer,
727 u32 region, s32 sx, s32 sy,
728 s32 ex, s32 ey, int benb)
730 const u32 invalidenb_pos = 28;
731 register struct nx_mlc_register_set *pregister;
733 pregister = __g_module_variables[module_index].pregister;
734 if (layer == 0 || layer == 1) {
736 writel(((benb << invalidenb_pos) |
737 ((sx & 0x7ff) << 16) | (ex & 0x7ff)),
738 &pregister->mlcrgblayer[layer]
739 .mlcinvalidleftright0);
741 writel((((sy & 0x7ff) << 16) | (ey & 0x7ff)),
742 &pregister->mlcrgblayer[layer]
743 .mlcinvalidtopbottom0);
745 writel(((benb << invalidenb_pos) |
746 ((sx & 0x7ff) << 16) | (ex & 0x7ff)),
747 &pregister->mlcrgblayer[layer]
748 .mlcinvalidleftright1);
750 writel((((sy & 0x7ff) << 16) | (ey & 0x7ff)),
751 &pregister->mlcrgblayer[layer]
752 .mlcinvalidtopbottom1);
757 void nx_mlc_set_rgblayer_stride(u32 module_index, u32 layer, s32 hstride,
760 register struct nx_mlc_register_set *pregister;
762 pregister = __g_module_variables[module_index].pregister;
763 if (layer == 0 || layer == 1) {
764 writel(hstride, &pregister->mlcrgblayer[layer].mlchstride);
765 writel(vstride, &pregister->mlcrgblayer[layer].mlcvstride);
766 } else if (layer == 2) {
767 writel(hstride, &pregister->mlcrgblayer2.mlchstride);
768 writel(vstride, &pregister->mlcrgblayer2.mlcvstride);
772 void nx_mlc_set_rgblayer_address(u32 module_index, u32 layer, u32 addr)
774 register struct nx_mlc_register_set *pregister;
776 pregister = __g_module_variables[module_index].pregister;
777 if (layer == 0 || layer == 1)
778 writel(addr, &pregister->mlcrgblayer[layer].mlcaddress);
780 writel(addr, &pregister->mlcrgblayer2.mlcaddress);
783 void nx_mlc_set_rgblayer_gama_table_power_mode(u32 module_index, int bred,
784 int bgreen, int bblue)
786 const u32 bgammatable_pwd_bitpos = 11;
787 const u32 ggammatable_pwd_bitpos = 9;
788 const u32 rgammatable_pwd_bitpos = 3;
789 const u32 bgammatable_pwd_mask = (1 << bgammatable_pwd_bitpos);
790 const u32 ggammatable_pwd_mask = (1 << ggammatable_pwd_bitpos);
791 const u32 rgammatable_pwd_mask = (1 << rgammatable_pwd_bitpos);
792 register u32 read_value;
793 register struct nx_mlc_register_set *pregister;
795 pregister = __g_module_variables[module_index].pregister;
796 read_value = pregister->mlcgammacont;
797 read_value &= ~(bgammatable_pwd_mask | ggammatable_pwd_mask |
798 rgammatable_pwd_mask);
799 read_value |= (((u32)bred << rgammatable_pwd_bitpos) |
800 ((u32)bgreen << ggammatable_pwd_bitpos) |
801 ((u32)bblue << bgammatable_pwd_bitpos));
803 writel(read_value, &pregister->mlcgammacont);
806 void nx_mlc_get_rgblayer_gama_table_power_mode(u32 module_index, int *pbred,
807 int *pbgreen, int *pbblue)
809 const u32 bgammatable_pwd_bitpos = 11;
810 const u32 ggammatable_pwd_bitpos = 9;
811 const u32 rgammatable_pwd_bitpos = 3;
812 const u32 bgammatable_pwd_mask = (1 << bgammatable_pwd_bitpos);
813 const u32 ggammatable_pwd_mask = (1 << ggammatable_pwd_bitpos);
814 const u32 rgammatable_pwd_mask = (1 << rgammatable_pwd_bitpos);
815 register u32 read_value;
816 register struct nx_mlc_register_set *pregister;
818 pregister = __g_module_variables[module_index].pregister;
819 read_value = pregister->mlcgammacont;
821 *pbred = (read_value & rgammatable_pwd_mask) ? 1 : 0;
824 *pbgreen = (read_value & ggammatable_pwd_mask) ? 1 : 0;
827 *pbblue = (read_value & bgammatable_pwd_mask) ? 1 : 0;
830 void nx_mlc_set_rgblayer_gama_table_sleep_mode(u32 module_index, int bred,
831 int bgreen, int bblue)
833 const u32 bgammatable_sld_bitpos = 10;
834 const u32 ggammatable_sld_bitpos = 8;
835 const u32 rgammatable_sld_bitpos = 2;
836 const u32 bgammatable_sld_mask = (1 << bgammatable_sld_bitpos);
837 const u32 ggammatable_sld_mask = (1 << ggammatable_sld_bitpos);
838 const u32 rgammatable_sld_mask = (1 << rgammatable_sld_bitpos);
839 register u32 read_value;
840 register struct nx_mlc_register_set *pregister;
842 pregister = __g_module_variables[module_index].pregister;
843 read_value = pregister->mlcgammacont;
845 read_value &= ~rgammatable_sld_mask;
847 read_value |= rgammatable_sld_mask;
850 read_value &= ~ggammatable_sld_mask;
852 read_value |= ggammatable_sld_mask;
855 read_value &= ~bgammatable_sld_mask;
857 read_value |= bgammatable_sld_mask;
859 writel(read_value, &pregister->mlcgammacont);
862 void nx_mlc_get_rgblayer_gama_table_sleep_mode(u32 module_index, int *pbred,
863 int *pbgreen, int *pbblue)
865 const u32 bgammatable_sld_bitpos = 10;
866 const u32 ggammatable_sld_bitpos = 8;
867 const u32 rgammatable_sld_bitpos = 2;
868 const u32 bgammatable_sld_mask = (1 << bgammatable_sld_bitpos);
869 const u32 ggammatable_sld_mask = (1 << ggammatable_sld_bitpos);
870 const u32 rgammatable_sld_mask = (1 << rgammatable_sld_bitpos);
871 register u32 read_value;
872 register struct nx_mlc_register_set *pregister;
874 pregister = __g_module_variables[module_index].pregister;
875 read_value = pregister->mlcgammacont;
878 *pbred = (read_value & rgammatable_sld_mask) ? 0 : 1;
881 *pbgreen = (read_value & ggammatable_sld_mask) ? 0 : 1;
884 *pbblue = (read_value & bgammatable_sld_mask) ? 0 : 1;
887 void nx_mlc_set_rgblayer_rgamma_table(u32 module_index, u32 dwaddress,
890 register struct nx_mlc_register_set *pregister;
891 const u32 tableaddr_bitpos = 24;
893 pregister = __g_module_variables[module_index].pregister;
894 writel(((dwaddress << tableaddr_bitpos) | dwdata),
895 &pregister->mlcrgammatablewrite);
898 void nx_mlc_set_rgblayer_ggamma_table(u32 module_index, u32 dwaddress,
901 register struct nx_mlc_register_set *pregister;
902 const u32 tableaddr_bitpos = 24;
904 pregister = __g_module_variables[module_index].pregister;
905 writel(((dwaddress << tableaddr_bitpos) | dwdata),
906 &pregister->mlcggammatablewrite);
909 void nx_mlc_set_rgblayer_bgamma_table(u32 module_index, u32 dwaddress,
912 register struct nx_mlc_register_set *pregister;
913 const u32 tableaddr_bitpos = 24;
915 pregister = __g_module_variables[module_index].pregister;
916 writel(((dwaddress << tableaddr_bitpos) | dwdata),
917 &pregister->mlcbgammatablewrite);
920 void nx_mlc_set_rgblayer_gamma_enable(u32 module_index, int benable)
922 const u32 rgbgammaemb_bitpos = 1;
923 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos;
924 register u32 read_value;
925 register struct nx_mlc_register_set *pregister;
927 pregister = __g_module_variables[module_index].pregister;
928 read_value = pregister->mlcgammacont;
929 read_value &= ~rgbgammaemb_mask;
930 read_value |= (u32)benable << rgbgammaemb_bitpos;
932 writel(read_value, &pregister->mlcgammacont);
935 int nx_mlc_get_rgblayer_gamma_enable(u32 module_index)
937 const u32 rgbgammaemb_bitpos = 1;
938 const u32 rgbgammaemb_mask = 1 << rgbgammaemb_bitpos;
940 return (int)((__g_module_variables[module_index].pregister->mlcgammacont
941 & rgbgammaemb_mask) >> rgbgammaemb_bitpos);
944 void nx_mlc_set_video_layer_stride(u32 module_index, s32 lu_stride,
945 s32 cb_stride, s32 cr_stride)
947 register struct nx_mlc_register_set *pregister;
949 pregister = __g_module_variables[module_index].pregister;
951 writel(lu_stride, &pregister->mlcvideolayer.mlcvstride);
952 writel(cb_stride, &pregister->mlcvideolayer.mlcvstridecb);
953 writel(cr_stride, &pregister->mlcvideolayer.mlcvstridecr);
956 void nx_mlc_set_video_layer_address(u32 module_index, u32 lu_addr, u32 cb_addr,
959 register struct nx_mlc_register_set *pregister;
961 pregister = __g_module_variables[module_index].pregister;
962 writel(lu_addr, &pregister->mlcvideolayer.mlcaddress);
963 writel(cb_addr, &pregister->mlcvideolayer.mlcaddresscb);
964 writel(cr_addr, &pregister->mlcvideolayer.mlcaddresscr);
967 void nx_mlc_set_video_layer_address_yuyv(u32 module_index, u32 addr,
970 register struct nx_mlc_register_set *pregister;
972 pregister = __g_module_variables[module_index].pregister;
973 writel(addr, &pregister->mlcvideolayer.mlcaddress);
974 writel(stride, &pregister->mlcvideolayer.mlcvstride);
977 void nx_mlc_set_video_layer_scale_factor(u32 module_index, u32 hscale,
978 u32 vscale, int bhlumaenb,
979 int bhchromaenb, int bvlumaenb,
982 const u32 filter_luma_pos = 28;
983 const u32 filter_choma_pos = 29;
984 const u32 scale_mask = ((1 << 23) - 1);
985 register struct nx_mlc_register_set *pregister;
987 pregister = __g_module_variables[module_index].pregister;
989 writel(((bhlumaenb << filter_luma_pos) |
990 (bhchromaenb << filter_choma_pos) | (hscale & scale_mask)),
991 &pregister->mlcvideolayer.mlchscale);
993 writel(((bvlumaenb << filter_luma_pos) |
994 (bvchromaenb << filter_choma_pos) | (vscale & scale_mask)),
995 &pregister->mlcvideolayer.mlcvscale);
998 void nx_mlc_set_video_layer_scale_filter(u32 module_index, int bhlumaenb,
999 int bhchromaenb, int bvlumaenb,
1002 const u32 filter_luma_pos = 28;
1003 const u32 filter_choma_pos = 29;
1004 const u32 scale_mask = ((1 << 23) - 1);
1005 register struct nx_mlc_register_set *pregister;
1006 register u32 read_value;
1008 pregister = __g_module_variables[module_index].pregister;
1009 read_value = pregister->mlcvideolayer.mlchscale;
1010 read_value &= scale_mask;
1012 (bhlumaenb << filter_luma_pos) | (bhchromaenb << filter_choma_pos);
1014 writel(read_value, &pregister->mlcvideolayer.mlchscale);
1015 read_value = pregister->mlcvideolayer.mlcvscale;
1016 read_value &= scale_mask;
1018 (bvlumaenb << filter_luma_pos) | (bvchromaenb << filter_choma_pos);
1020 writel(read_value, &pregister->mlcvideolayer.mlcvscale);
1023 void nx_mlc_get_video_layer_scale_filter(u32 module_index, int *bhlumaenb,
1024 int *bhchromaenb, int *bvlumaenb,
1027 const u32 filter_luma_pos = 28;
1028 const u32 filter_choma_pos = 29;
1029 const u32 filter_mask = 1ul;
1030 register struct nx_mlc_register_set *pregister;
1031 register u32 read_value;
1033 pregister = __g_module_variables[module_index].pregister;
1034 read_value = pregister->mlcvideolayer.mlchscale;
1035 *bhlumaenb = (read_value >> filter_luma_pos) & filter_mask;
1036 *bhchromaenb = (read_value >> filter_choma_pos) & filter_mask;
1037 read_value = pregister->mlcvideolayer.mlcvscale;
1038 *bvlumaenb = (read_value >> filter_luma_pos) & filter_mask;
1039 *bvchromaenb = (read_value >> filter_choma_pos) & filter_mask;
1042 void nx_mlc_set_video_layer_scale(u32 module_index, u32 sw, u32 sh, u32 dw,
1043 u32 dh, int bhlumaenb, int bhchromaenb,
1044 int bvlumaenb, int bvchromaenb)
1046 const u32 filter_luma_pos = 28;
1047 const u32 filter_choma_pos = 29;
1048 const u32 scale_mask = ((1 << 23) - 1);
1049 register u32 hscale, vscale, cal_sh;
1050 register struct nx_mlc_register_set *pregister;
1052 pregister = __g_module_variables[module_index].pregister;
1054 if ((bhlumaenb || bhchromaenb) && dw > sw) {
1058 hscale = (sw << 11) / dw;
1060 if ((bvlumaenb || bvchromaenb) && dh > sh) {
1063 vscale = (sh << 11) / dh;
1065 cal_sh = ((vscale * dh) >> 11);
1070 vscale = (sh << 11) / dh;
1073 writel(((bhlumaenb << filter_luma_pos) |
1074 (bhchromaenb << filter_choma_pos) | (hscale & scale_mask)),
1075 &pregister->mlcvideolayer.mlchscale);
1077 writel(((bvlumaenb << filter_luma_pos) |
1078 (bvchromaenb << filter_choma_pos) | (vscale & scale_mask)),
1079 &pregister->mlcvideolayer.mlcvscale);
1082 void nx_mlc_set_video_layer_luma_enhance(u32 module_index, u32 contrast,
1085 register struct nx_mlc_register_set *pregister;
1087 pregister = __g_module_variables[module_index].pregister;
1089 writel((((u32)brightness & 0xfful) << 8) | contrast,
1090 &pregister->mlcvideolayer.mlcluenh);
1093 void nx_mlc_set_video_layer_chroma_enhance(u32 module_index, u32 quadrant,
1097 register struct nx_mlc_register_set *pregister;
1100 pregister = __g_module_variables[module_index].pregister;
1101 temp = (((u32)cr_b & 0xfful) << 24) | (((u32)cr_a & 0xfful) << 16) |
1102 (((u32)cb_b & 0xfful) << 8) | (((u32)cb_a & 0xfful) << 0);
1104 writel(temp, &pregister->mlcvideolayer.mlcchenh[quadrant - 1]);
1106 writel(temp, &pregister->mlcvideolayer.mlcchenh[0]);
1107 writel(temp, &pregister->mlcvideolayer.mlcchenh[1]);
1108 writel(temp, &pregister->mlcvideolayer.mlcchenh[2]);
1109 writel(temp, &pregister->mlcvideolayer.mlcchenh[3]);
1113 void nx_mlc_set_video_layer_line_buffer_power_mode(u32 module_index,
1116 const u32 linebuff_pwd_pos = 15;
1117 const u32 linebuff_pwd_mask = 1ul << linebuff_pwd_pos;
1118 const u32 dirtyflag_mask = 1ul << 4;
1119 register u32 regvalue;
1120 register struct nx_mlc_register_set *pregister;
1122 pregister = __g_module_variables[module_index].pregister;
1123 regvalue = pregister->mlcvideolayer.mlccontrol;
1124 regvalue &= ~(linebuff_pwd_mask | dirtyflag_mask);
1125 regvalue |= ((u32)benable << linebuff_pwd_pos);
1127 writel(regvalue, &pregister->mlcvideolayer.mlccontrol);
1130 int nx_mlc_get_video_layer_line_buffer_power_mode(u32 module_index)
1132 const u32 linebuff_pwd_pos = 15;
1133 const u32 linebuff_pwd_mask = 1ul << linebuff_pwd_pos;
1135 return (int)((__g_module_variables[module_index]
1136 .pregister->mlcvideolayer.mlccontrol &
1137 linebuff_pwd_mask) >> linebuff_pwd_pos);
1140 void nx_mlc_set_video_layer_line_buffer_sleep_mode(u32 module_index,
1143 const u32 linebuff_slmd_pos = 14;
1144 const u32 linebuff_slmd_mask = 1ul << linebuff_slmd_pos;
1145 const u32 dirtyflag_mask = 1ul << 4;
1146 register u32 regvalue;
1147 register struct nx_mlc_register_set *pregister;
1149 benable = (int)((u32)benable ^ 1);
1150 pregister = __g_module_variables[module_index].pregister;
1151 regvalue = pregister->mlcvideolayer.mlccontrol;
1152 regvalue &= ~(linebuff_slmd_mask | dirtyflag_mask);
1153 regvalue |= (benable << linebuff_slmd_pos);
1155 writel(regvalue, &pregister->mlcvideolayer.mlccontrol);
1158 int nx_mlc_get_video_layer_line_buffer_sleep_mode(u32 module_index)
1160 const u32 linebuff_slmd_pos = 14;
1161 const u32 linebuff_slmd_mask = 1ul << linebuff_slmd_pos;
1162 register struct nx_mlc_register_set *pregister;
1164 pregister = __g_module_variables[module_index].pregister;
1165 if (linebuff_slmd_mask & pregister->mlcvideolayer.mlccontrol)
1171 void nx_mlc_set_video_layer_gama_table_power_mode(u32 module_index, int by,
1174 const u32 vgammatable_pwd_bitpos = 17;
1175 const u32 ugammatable_pwd_bitpos = 15;
1176 const u32 ygammatable_pwd_bitpos = 13;
1177 const u32 vgammatable_pwd_mask = (1 << vgammatable_pwd_bitpos);
1178 const u32 ugammatable_pwd_mask = (1 << ugammatable_pwd_bitpos);
1179 const u32 ygammatable_pwd_mask = (1 << ygammatable_pwd_bitpos);
1180 register u32 read_value;
1181 register struct nx_mlc_register_set *pregister;
1183 pregister = __g_module_variables[module_index].pregister;
1184 read_value = pregister->mlcgammacont;
1185 read_value &= ~(ygammatable_pwd_mask | ugammatable_pwd_mask |
1186 vgammatable_pwd_mask);
1187 read_value |= (((u32)by << ygammatable_pwd_bitpos) |
1188 ((u32)bu << ugammatable_pwd_bitpos) |
1189 ((u32)bv << vgammatable_pwd_bitpos));
1191 writel(read_value, &pregister->mlcgammacont);
1194 void nx_mlc_get_video_layer_gama_table_power_mode(u32 module_index, int *pby,
1197 const u32 vgammatable_pwd_bitpos = 17;
1198 const u32 ugammatable_pwd_bitpos = 15;
1199 const u32 ygammatable_pwd_bitpos = 13;
1200 const u32 vgammatable_pwd_mask = (1 << vgammatable_pwd_bitpos);
1201 const u32 ugammatable_pwd_mask = (1 << ugammatable_pwd_bitpos);
1202 const u32 ygammatable_pwd_mask = (1 << ygammatable_pwd_bitpos);
1203 register u32 read_value;
1204 register struct nx_mlc_register_set *pregister;
1206 pregister = __g_module_variables[module_index].pregister;
1207 read_value = pregister->mlcgammacont;
1209 *pby = (read_value & ygammatable_pwd_mask) ? 1 : 0;
1212 *pbu = (read_value & ugammatable_pwd_mask) ? 1 : 0;
1215 *pbv = (read_value & vgammatable_pwd_mask) ? 1 : 0;
1218 void nx_mlc_set_video_layer_gama_table_sleep_mode(u32 module_index, int by,
1221 const u32 vgammatable_sld_bitpos = 16;
1222 const u32 ugammatable_sld_bitpos = 14;
1223 const u32 ygammatable_sld_bitpos = 12;
1224 const u32 vgammatable_sld_mask = (1 << vgammatable_sld_bitpos);
1225 const u32 ugammatable_sld_mask = (1 << ugammatable_sld_bitpos);
1226 const u32 ygammatable_sld_mask = (1 << ygammatable_sld_bitpos);
1227 register u32 read_value;
1228 register struct nx_mlc_register_set *pregister;
1230 pregister = __g_module_variables[module_index].pregister;
1231 read_value = pregister->mlcgammacont;
1233 read_value &= ~ygammatable_sld_mask;
1235 read_value |= ygammatable_sld_mask;
1238 read_value &= ~ugammatable_sld_mask;
1240 read_value |= ugammatable_sld_mask;
1243 read_value &= ~vgammatable_sld_mask;
1245 read_value |= vgammatable_sld_mask;
1247 writel(read_value, &pregister->mlcgammacont);
1250 void nx_mlc_get_video_layer_gama_table_sleep_mode(u32 module_index, int *pby,
1253 const u32 vgammatable_sld_bitpos = 16;
1254 const u32 ugammatable_sld_bitpos = 14;
1255 const u32 ygammatable_sld_bitpos = 12;
1256 const u32 vgammatable_sld_mask = (1 << vgammatable_sld_bitpos);
1257 const u32 ugammatable_sld_mask = (1 << ugammatable_sld_bitpos);
1258 const u32 ygammatable_sld_mask = (1 << ygammatable_sld_bitpos);
1259 register u32 read_value;
1260 register struct nx_mlc_register_set *pregister;
1262 pregister = __g_module_variables[module_index].pregister;
1263 read_value = pregister->mlcgammacont;
1266 *pby = (read_value & vgammatable_sld_mask) ? 0 : 1;
1269 *pbu = (read_value & ugammatable_sld_mask) ? 0 : 1;
1272 *pbv = (read_value & ygammatable_sld_mask) ? 0 : 1;
1275 void nx_mlc_set_video_layer_gamma_enable(u32 module_index, int benable)
1277 const u32 yuvgammaemb_bitpos = 4;
1278 const u32 yuvgammaemb_mask = 1 << yuvgammaemb_bitpos;
1279 register u32 read_value;
1280 register struct nx_mlc_register_set *pregister;
1282 pregister = __g_module_variables[module_index].pregister;
1283 read_value = pregister->mlcgammacont;
1284 read_value &= ~yuvgammaemb_mask;
1285 read_value |= (u32)benable << yuvgammaemb_bitpos;
1287 writel(read_value, &pregister->mlcgammacont);
1290 int nx_mlc_get_video_layer_gamma_enable(u32 module_index)
1292 const u32 yuvgammaemb_bitpos = 4;
1293 const u32 yuvgammaemb_mask = 1 << yuvgammaemb_bitpos;
1295 return (int)((__g_module_variables[module_index].pregister->mlcgammacont
1296 & yuvgammaemb_mask) >> yuvgammaemb_bitpos);
1299 void nx_mlc_set_gamma_table_poweroff(u32 module_index, int enb)
1301 register struct nx_mlc_register_set *pregister;
1304 pregister = __g_module_variables[module_index].pregister;
1306 regvalue = pregister->mlcgammacont;
1307 regvalue = regvalue & 0xf3;
1308 writel(regvalue, &pregister->mlcgammacont);
1312 void nx_mlc_set_mlctop_control_parameter(u32 module_index, int field_enable,
1313 int mlcenable, u8 priority,
1314 enum g3daddrchangeallowed
1315 g3daddr_change_allowed)
1317 register u32 mlctopcontrolreg;
1318 register struct nx_mlc_register_set *pregister;
1320 pregister = __g_module_variables[module_index].pregister;
1321 mlctopcontrolreg = (readl(&pregister->mlccontrolt)) & 0xfffffcfc;
1322 mlctopcontrolreg = (u32)(mlctopcontrolreg |
1323 ((priority << 8) | ((mlcenable == 1) << 1) |
1325 field_enable)) | (g3daddr_change_allowed <<
1327 writel(mlctopcontrolreg, &pregister->mlccontrolt);
1330 void nx_mlc_set_rgb0layer_control_parameter(u32 module_index, int layer_enable,
1331 int grp3denable, int tp_enable,
1332 u32 transparency_color,
1333 int inv_enable, u32 inverse_color,
1334 int blend_enable, u8 alpha_value,
1335 enum mlc_rgbfmt rbgformat,
1336 enum locksizesel lock_size_select)
1341 u32 lock_size = (u32)(lock_size_select & 0x3);
1344 register struct nx_mlc_register_set *pregister;
1346 layer_format = nx_mlc_get_rgbformat(rbgformat);
1347 pregister = __g_module_variables[module_index].pregister;
1349 (u32)((grp3denable << 8) | (layer_enable << 5) |
1350 (blend_enable << 2) | (inv_enable << 1) | tp_enable) & 0x127;
1351 alpha_argument = (u32)(alpha_value & 0xf);
1353 rgb0controlreg = readl(&pregister->mlcrgblayer[0].mlccontrol) & 0x10;
1355 (u32)(((layer_format << 16) | control_enb | (lock_size << 12)) |
1357 writel(regvalue, &pregister->mlcrgblayer[0].mlccontrol);
1359 regvalue = (u32)((alpha_argument << 28) | transparency_color);
1360 writel(regvalue, &pregister->mlcrgblayer[0].mlctpcolor);
1361 regvalue = inverse_color;
1362 writel(regvalue, &pregister->mlcrgblayer[0].mlcinvcolor);
1365 u32 nx_mlc_get_rgbformat(enum mlc_rgbfmt rbgformat)
1368 const u32 format_table[] = {
1369 0x4432ul, 0x4342ul, 0x4211ul, 0x4120ul, 0x4003ul, 0x4554ul,
1370 0x3342ul, 0x2211ul, 0x1120ul, 0x1003ul, 0x4653ul, 0x4653ul,
1371 0x0653ul, 0x4ed3ul, 0x4f84ul, 0xc432ul, 0xc342ul, 0xc211ul,
1372 0xc120ul, 0xb342ul, 0xa211ul, 0x9120ul, 0xc653ul, 0xc653ul,
1373 0x8653ul, 0xced3ul, 0xcf84ul, 0x443aul
1376 return rgbformatvalue = format_table[rbgformat];
1379 void nx_mlc_set_rgb1layer_control_parameter(u32 module_index, int layer_enable,
1380 int grp3denable, int tp_enable,
1381 u32 transparency_color,
1382 int inv_enable, u32 inverse_color,
1383 int blend_enable, u8 alpha_value,
1384 enum mlc_rgbfmt rbgformat,
1385 enum locksizesel lock_size_select)
1390 u32 lock_size = (u32)(lock_size_select & 0x3);
1393 register struct nx_mlc_register_set *pregister;
1395 layer_format = nx_mlc_get_rgbformat(rbgformat);
1396 pregister = __g_module_variables[module_index].pregister;
1398 rgb0controlreg = readl(&pregister->mlcrgblayer[1].mlccontrol) & 0x10;
1400 (u32)((grp3denable << 8) | (layer_enable << 5) |
1401 (blend_enable << 2) | (inv_enable << 1) | tp_enable) & 0x127;
1402 alpha_argument = (u32)(alpha_value & 0xf);
1404 (u32)(((layer_format << 16) | control_enb | (lock_size << 12)) |
1406 writel(regvalue, &pregister->mlcrgblayer[1].mlccontrol);
1407 regvalue = (u32)((alpha_argument << 28) | transparency_color);
1408 writel(regvalue, &pregister->mlcrgblayer[1].mlctpcolor);
1409 regvalue = inverse_color;
1410 writel(regvalue, &pregister->mlcrgblayer[1].mlcinvcolor);
1413 void nx_mlc_set_rgb2layer_control_parameter(u32 module_index, int layer_enable,
1414 int grp3denable, int tp_enable,
1415 u32 transparency_color,
1416 int inv_enable, u32 inverse_color,
1417 int blend_enable, u8 alpha_value,
1418 enum mlc_rgbfmt rbgformat,
1419 enum locksizesel lock_size_select)
1424 u32 lock_size = (u32)(lock_size_select & 0x3);
1427 register struct nx_mlc_register_set *pregister;
1429 layer_format = nx_mlc_get_rgbformat(rbgformat);
1430 pregister = __g_module_variables[module_index].pregister;
1432 rgb0controlreg = readl(&pregister->mlcrgblayer2.mlccontrol) & 0x10;
1434 (u32)((grp3denable << 8) | (layer_enable << 5) |
1435 (blend_enable << 2) | (inv_enable << 1) | tp_enable) & 0x127;
1436 alpha_argument = (u32)(alpha_value & 0xf);
1438 (u32)(((layer_format << 16) | control_enb | (lock_size << 12)) |
1440 writel(regvalue, &pregister->mlcrgblayer2.mlccontrol);
1441 regvalue = (u32)((alpha_argument << 28) | transparency_color);
1442 writel(regvalue, &pregister->mlcrgblayer2.mlctpcolor);
1443 regvalue = inverse_color;
1444 writel(regvalue, &pregister->mlcrgblayer2.mlcinvcolor);
1447 void nx_mlc_set_video_layer_control_parameter(u32 module_index,
1448 int layer_enable, int tp_enable,
1449 u32 transparency_color,
1450 int inv_enable, u32 inverse_color,
1451 int blend_enable, u8 alpha_value,
1452 enum nx_mlc_yuvfmt yuvformat)
1457 register struct nx_mlc_register_set *pregister;
1458 u32 video_control_reg;
1460 pregister = __g_module_variables[module_index].pregister;
1462 video_control_reg = readl(&pregister->mlcvideolayer.mlccontrol);
1464 (u32)((yuvformat) | (layer_enable << 5) | (blend_enable << 2) |
1465 (inv_enable << 1) | tp_enable) & 0x30027;
1466 alpha_argument = (u32)(alpha_value & 0xf);
1467 regvalue = (u32)(control_enb | video_control_reg);
1468 writel(regvalue, &pregister->mlcvideolayer.mlccontrol);
1469 regvalue = (u32)((alpha_argument << 28) | transparency_color);
1470 writel(regvalue, &pregister->mlcvideolayer.mlctpcolor);
1471 regvalue = (u32)((alpha_argument << 28) | transparency_color);
1472 writel(regvalue, &pregister->mlcvideolayer.mlcinvcolor);
1475 void nx_mlc_set_srammode(u32 module_index, enum latyername layer_name,
1476 enum srammode sram_mode)
1478 u32 control_reg_value;
1479 register struct nx_mlc_register_set *pregister;
1481 pregister = __g_module_variables[module_index].pregister;
1482 switch (layer_name) {
1484 control_reg_value = readl(&pregister->mlccontrolt);
1485 writel((u32)(control_reg_value | (sram_mode << 10)),
1486 &pregister->mlccontrolt);
1487 control_reg_value = 0;
1491 readl(&pregister->mlcrgblayer[0].mlccontrol);
1492 writel((u32)(control_reg_value | (sram_mode << 14)),
1493 &pregister->mlcrgblayer[0].mlccontrol);
1494 control_reg_value = 0;
1498 readl(&pregister->mlcrgblayer[1].mlccontrol);
1499 writel((u32)(control_reg_value | (sram_mode << 14)),
1500 &pregister->mlcrgblayer[1].mlccontrol);
1501 control_reg_value = 0;
1504 control_reg_value = readl(&pregister->mlcrgblayer2.mlccontrol);
1505 writel((u32)(control_reg_value | (sram_mode << 14)),
1506 &pregister->mlcrgblayer2.mlccontrol);
1507 control_reg_value = 0;
1510 control_reg_value = readl(&pregister->mlcvideolayer.mlccontrol);
1511 writel((u32)(control_reg_value | (sram_mode << 14)),
1512 &pregister->mlcvideolayer.mlccontrol);
1513 control_reg_value = 0;
1520 void nx_mlc_set_layer_reg_finish(u32 module_index, enum latyername layer_name)
1522 u32 control_reg_value;
1523 register struct nx_mlc_register_set *pregister;
1525 pregister = __g_module_variables[module_index].pregister;
1527 switch (layer_name) {
1529 control_reg_value = readl(&pregister->mlccontrolt);
1530 writel((u32)(control_reg_value | (1ul << 3)),
1531 &pregister->mlccontrolt);
1532 control_reg_value = 0;
1536 readl(&pregister->mlcrgblayer[0].mlccontrol);
1537 writel((u32)(control_reg_value | (1ul << 4)),
1538 &pregister->mlcrgblayer[0].mlccontrol);
1539 control_reg_value = 0;
1543 readl(&pregister->mlcrgblayer[1].mlccontrol);
1544 writel((u32)(control_reg_value | (1ul << 4)),
1545 &pregister->mlcrgblayer[1].mlccontrol);
1546 control_reg_value = 0;
1549 control_reg_value = readl(&pregister->mlcrgblayer2.mlccontrol);
1550 writel((u32)(control_reg_value | (1ul << 4)),
1551 &pregister->mlcrgblayer2.mlccontrol);
1552 control_reg_value = 0;
1555 control_reg_value = readl(&pregister->mlcvideolayer.mlccontrol);
1556 writel((u32)(control_reg_value | (1ul << 4)),
1557 &pregister->mlcvideolayer.mlccontrol);
1558 control_reg_value = 0;
1565 void nx_mlc_set_video_layer_coordinate(u32 module_index, int vfilterenable,
1566 int hfilterenable, int vfilterenable_c,
1567 int hfilterenable_c,
1568 u16 video_layer_with,
1569 u16 video_layer_height, s16 left,
1573 s32 source_width, source_height;
1574 s32 destination_width;
1575 s32 destination_height;
1577 s32 hfilterenb, vfilterenb;
1578 register struct nx_mlc_register_set *pregister;
1580 pregister = __g_module_variables[module_index].pregister;
1581 writel((s32)(((left & 0x0fff) << 16) | (right & 0x0fff)),
1582 &pregister->mlcvideolayer.mlcleftright);
1583 writel((s32)(((top & 0x0fff) << 16) | (bottom & 0x0fff)),
1584 &pregister->mlcvideolayer.mlctopbottom);
1585 source_width = (s32)(video_layer_with - 1);
1586 source_height = (s32)(video_layer_height - 1);
1587 destination_width = (s32)(right - left);
1588 destination_height = (s32)(bottom - top);
1591 (s32)((source_width * (1ul << 11) + (destination_width / 2)) /
1594 (s32)((source_height * (1ul << 11) +
1595 (destination_height / 2)) / destination_height);
1597 hfilterenb = (u32)(((hfilterenable_c << 29) | (hfilterenable) << 28)) &
1599 vfilterenb = (u32)(((vfilterenable_c << 29) | (vfilterenable) << 28)) &
1601 writel((u32)(hfilterenb | (hscale & 0x00ffffff)),
1602 &pregister->mlcvideolayer.mlchscale);
1603 writel((u32)(vfilterenb | (vscale & 0x00ffffff)),
1604 &pregister->mlcvideolayer.mlcvscale);
1607 void nx_mlc_set_video_layer_filter_scale(u32 module_index, u32 hscale,
1610 register struct nx_mlc_register_set *pregister;
1614 pregister = __g_module_variables[module_index].pregister;
1615 mlchscale = readl(&pregister->mlcvideolayer.mlchscale) & (~0x00ffffff);
1616 mlcvscale = readl(&pregister->mlcvideolayer.mlcvscale) & (~0x00ffffff);
1618 writel((u32)(mlchscale | (hscale & 0x00ffffff)),
1619 &pregister->mlcvideolayer.mlchscale);
1620 writel((u32)(mlcvscale | (vscale & 0x00ffffff)),
1621 &pregister->mlcvideolayer.mlcvscale);
1624 void nx_mlc_set_gamma_control_parameter(u32 module_index, int rgbgammaenb,
1625 int yuvgammaenb, int yuvalphaarray,
1629 register struct nx_mlc_register_set *pregister;
1631 pregister = __g_module_variables[module_index].pregister;
1632 register_data = readl(&pregister->mlcgammacont);
1633 register_data = (register_data & 0xf0c) |
1634 ((yuvalphaarray << 5) | (yuvgammaenb << 4) |
1635 (rgbgammaenb << 1) | (dither_enb << 0));
1636 writel(register_data, &pregister->mlcgammacont);
1639 void nx_mlc_set_layer_alpha256(u32 module_index, u32 layer, u32 alpha)
1642 register struct nx_mlc_register_set *pregister;
1649 pregister = __g_module_variables[module_index].pregister;
1652 readl(&pregister->mlcrgblayer[0].mlctpcolor) & 0x00ffffff;
1653 register_data = register_data | (alpha << 24);
1654 writel(register_data, &pregister->mlcrgblayer[0].mlctpcolor);
1655 } else if (layer == 1) {
1657 readl(&pregister->mlcrgblayer[1].mlctpcolor) & 0x00ffffff;
1658 register_data = register_data | (alpha << 24);
1659 writel(register_data, &pregister->mlcrgblayer[1].mlctpcolor);
1660 } else if (layer == 2) {
1662 readl(&pregister->mlcrgblayer[1].mlctpcolor) & 0x00ffffff;
1663 register_data = register_data | (alpha << 24);
1664 writel(register_data, &pregister->mlcrgblayer2.mlctpcolor);
1667 readl(&pregister->mlcvideolayer.mlctpcolor) & 0x00ffffff;
1668 register_data = register_data | (alpha << 24);
1669 writel(register_data, &pregister->mlcvideolayer.mlctpcolor);
1673 int nx_mlc_is_under_flow(u32 module_index)
1675 const u32 underflow_pend_pos = 31;
1676 const u32 underflow_pend_mask = 1ul << underflow_pend_pos;
1678 return (int)((__g_module_variables[module_index].pregister->mlccontrolt
1679 & underflow_pend_mask) >> underflow_pend_pos);
1682 void nx_mlc_set_gamma_table(u32 module_index, int enb,
1683 struct nx_mlc_gamma_table_parameter *p_gammatable)
1685 register struct nx_mlc_register_set *pregister;
1688 pregister = __g_module_variables[module_index].pregister;
1690 regval = readl(&pregister->mlcgammacont);
1692 regval = (1 << 11) | (1 << 9) | (1 << 3);
1693 writel(regval, &pregister->mlcgammacont);
1695 regval = regval | (1 << 10) | (1 << 8) | (1 << 2);
1696 writel(regval, &pregister->mlcgammacont);
1698 for (i = 0; i < 256; i++) {
1699 nx_mlc_set_rgblayer_rgamma_table(module_index, i,
1700 p_gammatable->r_table[i]);
1701 nx_mlc_set_rgblayer_ggamma_table(module_index, i,
1702 p_gammatable->g_table[i]);
1703 nx_mlc_set_rgblayer_bgamma_table(module_index, i,
1704 p_gammatable->b_table[i]);
1707 regval = regval | (p_gammatable->alphaselect << 5) |
1708 (p_gammatable->yuvgammaenb << 4 |
1709 p_gammatable->allgammaenb << 4) |
1710 (p_gammatable->rgbgammaenb << 1 |
1711 p_gammatable->allgammaenb << 1) |
1712 (p_gammatable->ditherenb << 1);
1713 writel(regval, &pregister->mlcgammacont);
1715 regval = regval & ~(1 << 10) & ~(1 << 8) & ~(1 << 2);
1716 writel(regval, &pregister->mlcgammacont);
1718 regval = regval & ~(1 << 11) & ~(1 << 9) & ~(1 << 3);
1719 writel(regval, &pregister->mlcgammacont);
1723 void nx_mlc_get_rgblayer_stride(u32 module_index, u32 layer, s32 *hstride,
1726 unsigned int hs, vs;
1727 register struct nx_mlc_register_set *pregister;
1729 pregister = __g_module_variables[module_index].pregister;
1731 hs = readl(&pregister->mlcrgblayer[layer].mlchstride);
1732 vs = readl(&pregister->mlcrgblayer[layer].mlcvstride);
1735 *(s32 *)hstride = hs;
1738 *(s32 *)vstride = vs;
1741 void nx_mlc_get_rgblayer_address(u32 module_index, u32 layer,
1745 register struct nx_mlc_register_set *pregister;
1747 pregister = __g_module_variables[module_index].pregister;
1748 pa = readl(&pregister->mlcrgblayer[layer].mlcaddress);
1751 *(u32 *)phys_address = pa;
1754 void nx_mlc_get_position(u32 module_index, u32 layer, int *left, int *top,
1755 int *right, int *bottom)
1758 register struct nx_mlc_register_set *pregister;
1760 pregister = __g_module_variables[module_index].pregister;
1762 lr = readl(&pregister->mlcrgblayer[layer].mlcleftright);
1763 tb = readl(&pregister->mlcrgblayer[layer].mlctopbottom);
1766 *(int *)left = ((lr >> 16) & 0xFFUL);
1769 *(int *)top = ((tb >> 16) & 0xFFUL);
1772 *(int *)right = ((lr >> 0) & 0xFFUL);
1775 *(int *)bottom = ((tb >> 0) & 0xFFUL);
1778 void nx_mlc_get_video_layer_address_yuyv(u32 module_index, u32 *address,
1782 register struct nx_mlc_register_set *pregister;
1784 pregister = __g_module_variables[module_index].pregister;
1785 a = readl(&pregister->mlcvideolayer.mlcaddress);
1786 s = readl(&pregister->mlcvideolayer.mlcvstride);
1789 *(u32 *)address = a;
1795 void nx_mlc_get_video_layer_address(u32 module_index, u32 *lu_address,
1796 u32 *cb_address, u32 *cr_address)
1799 register struct nx_mlc_register_set *pregister;
1801 pregister = __g_module_variables[module_index].pregister;
1803 lua = readl(&pregister->mlcvideolayer.mlcaddress);
1804 cba = readl(&pregister->mlcvideolayer.mlcaddresscb);
1805 cra = readl(&pregister->mlcvideolayer.mlcaddresscr);
1808 *(u32 *)lu_address = lua;
1811 *(u32 *)cb_address = cba;
1814 *(u32 *)cr_address = cra;
1817 void nx_mlc_get_video_layer_stride(u32 module_index, u32 *lu_stride,
1818 u32 *cb_stride, u32 *cr_stride)
1821 register struct nx_mlc_register_set *pregister;
1823 pregister = __g_module_variables[module_index].pregister;
1825 lus = readl(&pregister->mlcvideolayer.mlcvstride);
1826 cbs = readl(&pregister->mlcvideolayer.mlcvstridecb);
1827 crs = readl(&pregister->mlcvideolayer.mlcvstridecr);
1830 *(u32 *)lu_stride = lus;
1833 *(u32 *)cb_stride = cbs;
1836 *(u32 *)cr_stride = crs;
1839 void nx_mlc_get_video_position(u32 module_index, int *left, int *top,
1840 int *right, int *bottom)
1843 register struct nx_mlc_register_set *pregister;
1845 pregister = __g_module_variables[module_index].pregister;
1847 lr = readl(&pregister->mlcvideolayer.mlcleftright);
1848 tb = readl(&pregister->mlcvideolayer.mlctopbottom);
1851 *(int *)left = ((lr >> 16) & 0xFFUL);
1854 *(int *)top = ((tb >> 16) & 0xFFUL);
1857 *(int *)right = ((lr >> 0) & 0xFFUL);
1860 *(int *)bottom = ((tb >> 0) & 0xFFUL);