drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/gadget.c) and ported
  10  * to uboot.
  11  *
  12  * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0
  15  */
  16
  17 #include <common.h>
  18 #include <malloc.h>
  19 #include <asm/dma-mapping.h>
  20 #include <usb/lin_gadget_compat.h>
  21 #include <linux/bug.h>
  22 #include <linux/list.h>
  23
  24 #include <linux/usb/ch9.h>
  25 #include <linux/usb/gadget.h>
  26 #include <asm/arch/sys_proto.h>
  27
  28 #include "core.h"
  29 #include "gadget.h"
  30 #include "io.h"
  31
  32 #include "linux-compat.h"
  33
  34 /**
  35  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  36  * @dwc: pointer to our context structure
  37  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  38  *
  39  * Caller should take care of locking. This function will
  40  * return 0 on success or -EINVAL if wrong Test Selector
  41  * is passed
  42  */
  43 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  44 {
  45         u32             reg;
  46
  47         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  48         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  49
  50         switch (mode) {
  51         case TEST_J:
  52         case TEST_K:
  53         case TEST_SE0_NAK:
  54         case TEST_PACKET:
  55         case TEST_FORCE_EN:
  56                 reg |= mode << 1;
  57                 break;
  58         default:
  59                 return -EINVAL;
  60         }
  61
  62         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  63
  64         return 0;
  65 }
  66
  67 /**
  68  * dwc3_gadget_get_link_state - Gets current state of USB Link
  69  * @dwc: pointer to our context structure
  70  *
  71  * Caller should take care of locking. This function will
  72  * return the link state on success (>= 0) or -ETIMEDOUT.
  73  */
  74 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  75 {
  76         u32             reg;
  77
  78         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  79
  80         return DWC3_DSTS_USBLNKST(reg);
  81 }
  82
  83 /**
  84  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  85  * @dwc: pointer to our context structure
  86  * @state: the state to put link into
  87  *
  88  * Caller should take care of locking. This function will
  89  * return 0 on success or -ETIMEDOUT.
  90  */
  91 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  92 {
  93         int             retries = 10000;
  94         u32             reg;
  95
  96         /*
  97          * Wait until device controller is ready. Only applies to 1.94a and
  98          * later RTL.
  99          */
 100         if (dwc->revision >= DWC3_REVISION_194A) {
 101                 while (--retries) {
 102                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 103                         if (reg & DWC3_DSTS_DCNRD)
 104                                 udelay(5);
 105                         else
 106                                 break;
 107                 }
 108
 109                 if (retries <= 0)
 110                         return -ETIMEDOUT;
 111         }
 112
 113         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 114         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 115
 116         /* set requested state */
 117         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 118         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 119
 120         /*
 121          * The following code is racy when called from dwc3_gadget_wakeup,
 122          * and is not needed, at least on newer versions
 123          */
 124         if (dwc->revision >= DWC3_REVISION_194A)
 125                 return 0;
 126
 127         /* wait for a change in DSTS */
 128         retries = 10000;
 129         while (--retries) {
 130                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 131
 132                 if (DWC3_DSTS_USBLNKST(reg) == state)
 133                         return 0;
 134
 135                 udelay(5);
 136         }
 137
 138         dev_vdbg(dwc->dev, "link state change request timed out\n");
 139
 140         return -ETIMEDOUT;
 141 }
 142
 143 /**
 144  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 145  * @dwc: pointer to our context structure
 146  *
 147  * This function will a best effort FIFO allocation in order
 148  * to improve FIFO usage and throughput, while still allowing
 149  * us to enable as many endpoints as possible.
 150  *
 151  * Keep in mind that this operation will be highly dependent
 152  * on the configured size for RAM1 - which contains TxFifo -,
 153  * the amount of endpoints enabled on coreConsultant tool, and
 154  * the width of the Master Bus.
 155  *
 156  * In the ideal world, we would always be able to satisfy the
 157  * following equation:
 158  *
 159  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 160  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 161  *
 162  * Unfortunately, due to many variables that's not always the case.
 163  */
 164 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 165 {
 166         int             last_fifo_depth = 0;
 167         int             fifo_size;
 168         int             mdwidth;
 169         int             num;
 170
 171         if (!dwc->needs_fifo_resize)
 172                 return 0;
 173
 174         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 175
 176         /* MDWIDTH is represented in bits, we need it in bytes */
 177         mdwidth >>= 3;
 178
 179         /*
 180          * FIXME For now we will only allocate 1 wMaxPacketSize space
 181          * for each enabled endpoint, later patches will come to
 182          * improve this algorithm so that we better use the internal
 183          * FIFO space
 184          */
 185         for (num = 0; num < dwc->num_in_eps; num++) {
 186                 /* bit0 indicates direction; 1 means IN ep */
 187                 struct dwc3_ep  *dep = dwc->eps[(num << 1) | 1];
 188                 int             mult = 1;
 189                 int             tmp;
 190
 191                 if (!(dep->flags & DWC3_EP_ENABLED))
 192                         continue;
 193
 194                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 195                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 196                         mult = 3;
 197
 198                 /*
 199                  * REVISIT: the following assumes we will always have enough
 200                  * space available on the FIFO RAM for all possible use cases.
 201                  * Make sure that's true somehow and change FIFO allocation
 202                  * accordingly.
 203                  *
 204                  * If we have Bulk or Isochronous endpoints, we want
 205                  * them to be able to be very, very fast. So we're giving
 206                  * those endpoints a fifo_size which is enough for 3 full
 207                  * packets
 208                  */
 209                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 210                 tmp += mdwidth;
 211
 212                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 213
 214                 fifo_size |= (last_fifo_depth << 16);
 215
 216                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 217                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 218
 219                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
 220
 221                 last_fifo_depth += (fifo_size & 0xffff);
 222         }
 223
 224         return 0;
 225 }
 226
 227 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 228                 int status)
 229 {
 230         struct dwc3                     *dwc = dep->dwc;
 231
 232         if (req->queued) {
 233                 dep->busy_slot++;
 234                 /*
 235                  * Skip LINK TRB. We can't use req->trb and check for
 236                  * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 237                  * just completed (not the LINK TRB).
 238                  */
 239                 if (((dep->busy_slot & DWC3_TRB_MASK) ==
 240                         DWC3_TRB_NUM- 1) &&
 241                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 242                         dep->busy_slot++;
 243                 req->queued = false;
 244         }
 245
 246         list_del(&req->list);
 247         req->trb = NULL;
 248         dwc3_flush_cache((long)req->request.dma, req->request.length);
 249
 250         if (req->request.status == -EINPROGRESS)
 251                 req->request.status = status;
 252
 253         if (dwc->ep0_bounced && dep->number == 0)
 254                 dwc->ep0_bounced = false;
 255         else
 256                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 257                                 req->direction);
 258
 259         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 260                         req, dep->name, req->request.actual,
 261                         req->request.length, status);
 262
 263         spin_unlock(&dwc->lock);
 264         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 265         spin_lock(&dwc->lock);
 266 }
 267
 268 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 269 {
 270         u32             timeout = 500;
 271         u32             reg;
 272
 273         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 274         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 275
 276         do {
 277                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 278                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 279                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 280                                         DWC3_DGCMD_STATUS(reg));
 281                         return 0;
 282                 }
 283
 284                 /*
 285                  * We can't sleep here, because it's also called from
 286                  * interrupt context.
 287                  */
 288                 timeout--;
 289                 if (!timeout)
 290                         return -ETIMEDOUT;
 291                 udelay(1);
 292         } while (1);
 293 }
 294
 295 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 296                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 297 {
 298         u32                     timeout = 500;
 299         u32                     reg;
 300
 301         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 302         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 303         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 304
 305         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 306         do {
 307                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 308                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 309                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 310                                         DWC3_DEPCMD_STATUS(reg));
 311                         return 0;
 312                 }
 313
 314                 /*
 315                  * We can't sleep here, because it is also called from
 316                  * interrupt context.
 317                  */
 318                 timeout--;
 319                 if (!timeout)
 320                         return -ETIMEDOUT;
 321
 322                 udelay(1);
 323         } while (1);
 324 }
 325
 326 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 327                 struct dwc3_trb *trb)
 328 {
 329         u32             offset = (char *) trb - (char *) dep->trb_pool;
 330
 331         return dep->trb_pool_dma + offset;
 332 }
 333
 334 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 335 {
 336         if (dep->trb_pool)
 337                 return 0;
 338
 339         if (dep->number == 0 || dep->number == 1)
 340                 return 0;
 341
 342         dep->trb_pool = dma_alloc_coherent(sizeof(struct dwc3_trb) *
 343                                            DWC3_TRB_NUM,
 344                                            (unsigned long *)&dep->trb_pool_dma);
 345         if (!dep->trb_pool) {
 346                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 347                                 dep->name);
 348                 return -ENOMEM;
 349         }
 350
 351         return 0;
 352 }
 353
 354 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 355 {
 356         dma_free_coherent(dep->trb_pool);
 357
 358         dep->trb_pool = NULL;
 359         dep->trb_pool_dma = 0;
 360 }
 361
 362 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 363 {
 364         struct dwc3_gadget_ep_cmd_params params;
 365         u32                     cmd;
 366
 367         memset(&params, 0x00, sizeof(params));
 368
 369         if (dep->number != 1) {
 370                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 371                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 372                 if (dep->number > 1) {
 373                         if (dwc->start_config_issued)
 374                                 return 0;
 375                         dwc->start_config_issued = true;
 376                         cmd |= DWC3_DEPCMD_PARAM(2);
 377                 }
 378
 379                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 380         }
 381
 382         return 0;
 383 }
 384
 385 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 386                 const struct usb_endpoint_descriptor *desc,
 387                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 388                 bool ignore, bool restore)
 389 {
 390         struct dwc3_gadget_ep_cmd_params params;
 391
 392         memset(&params, 0x00, sizeof(params));
 393
 394         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 395                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 396
 397         /* Burst size is only needed in SuperSpeed mode */
 398         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 399                 u32 burst = dep->endpoint.maxburst - 1;
 400
 401                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 402         }
 403
 404         if (ignore)
 405                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 406
 407         if (restore) {
 408                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 409                 params.param2 |= dep->saved_state;
 410         }
 411
 412         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 413                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 414
 415         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 416                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 417                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 418                 dep->stream_capable = true;
 419         }
 420
 421         if (!usb_endpoint_xfer_control(desc))
 422                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 423
 424         /*
 425          * We are doing 1:1 mapping for endpoints, meaning
 426          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 427          * so on. We consider the direction bit as part of the physical
 428          * endpoint number. So USB endpoint 0x81 is 0x03.
 429          */
 430         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 431
 432         /*
 433          * We must use the lower 16 TX FIFOs even though
 434          * HW might have more
 435          */
 436         if (dep->direction)
 437                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 438
 439         if (desc->bInterval) {
 440                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 441                 dep->interval = 1 << (desc->bInterval - 1);
 442         }
 443
 444         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 445                         DWC3_DEPCMD_SETEPCONFIG, &params);
 446 }
 447
 448 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 449 {
 450         struct dwc3_gadget_ep_cmd_params params;
 451
 452         memset(&params, 0x00, sizeof(params));
 453
 454         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 455
 456         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 457                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 458 }
 459
 460 /**
 461  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 462  * @dep: endpoint to be initialized
 463  * @desc: USB Endpoint Descriptor
 464  *
 465  * Caller should take care of locking
 466  */
 467 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 468                 const struct usb_endpoint_descriptor *desc,
 469                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 470                 bool ignore, bool restore)
 471 {
 472         struct dwc3             *dwc = dep->dwc;
 473         u32                     reg;
 474         int                     ret;
 475
 476         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 477
 478         if (!(dep->flags & DWC3_EP_ENABLED)) {
 479                 ret = dwc3_gadget_start_config(dwc, dep);
 480                 if (ret)
 481                         return ret;
 482         }
 483
 484         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 485                         restore);
 486         if (ret)
 487                 return ret;
 488
 489         if (!(dep->flags & DWC3_EP_ENABLED)) {
 490                 struct dwc3_trb *trb_st_hw;
 491                 struct dwc3_trb *trb_link;
 492
 493                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 494                 if (ret)
 495                         return ret;
 496
 497                 dep->endpoint.desc = desc;
 498                 dep->comp_desc = comp_desc;
 499                 dep->type = usb_endpoint_type(desc);
 500                 dep->flags |= DWC3_EP_ENABLED;
 501
 502                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 503                 reg |= DWC3_DALEPENA_EP(dep->number);
 504                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 505
 506                 if (!usb_endpoint_xfer_isoc(desc))
 507                         return 0;
 508
 509                 /* Link TRB for ISOC. The HWO bit is never reset */
 510                 trb_st_hw = &dep->trb_pool[0];
 511
 512                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 513                 memset(trb_link, 0, sizeof(*trb_link));
 514
 515                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 516                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 517                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 518                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 519         }
 520
 521         return 0;
 522 }
 523
 524 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 525 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 526 {
 527         struct dwc3_request             *req;
 528
 529         if (!list_empty(&dep->req_queued)) {
 530                 dwc3_stop_active_transfer(dwc, dep->number, true);
 531
 532                 /* - giveback all requests to gadget driver */
 533                 while (!list_empty(&dep->req_queued)) {
 534                         req = next_request(&dep->req_queued);
 535
 536                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 537                 }
 538         }
 539
 540         while (!list_empty(&dep->request_list)) {
 541                 req = next_request(&dep->request_list);
 542
 543                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 544         }
 545 }
 546
 547 /**
 548  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 549  * @dep: the endpoint to disable
 550  *
 551  * This function also removes requests which are currently processed ny the
 552  * hardware and those which are not yet scheduled.
 553  * Caller should take care of locking.
 554  */
 555 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 556 {
 557         struct dwc3             *dwc = dep->dwc;
 558         u32                     reg;
 559
 560         dwc3_remove_requests(dwc, dep);
 561
 562         /* make sure HW endpoint isn't stalled */
 563         if (dep->flags & DWC3_EP_STALL)
 564                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 565
 566         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 567         reg &= ~DWC3_DALEPENA_EP(dep->number);
 568         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 569
 570         dep->stream_capable = false;
 571         dep->endpoint.desc = NULL;
 572         dep->comp_desc = NULL;
 573         dep->type = 0;
 574         dep->flags = 0;
 575
 576         return 0;
 577 }
 578
 579 /* -------------------------------------------------------------------------- */
 580
 581 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 582                 const struct usb_endpoint_descriptor *desc)
 583 {
 584         return -EINVAL;
 585 }
 586
 587 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 588 {
 589         return -EINVAL;
 590 }
 591
 592 /* -------------------------------------------------------------------------- */
 593
 594 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 595                 const struct usb_endpoint_descriptor *desc)
 596 {
 597         struct dwc3_ep                  *dep;
 598         unsigned long                   flags;
 599         int                             ret;
 600
 601         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 602                 pr_debug("dwc3: invalid parameters\n");
 603                 return -EINVAL;
 604         }
 605
 606         if (!desc->wMaxPacketSize) {
 607                 pr_debug("dwc3: missing wMaxPacketSize\n");
 608                 return -EINVAL;
 609         }
 610
 611         dep = to_dwc3_ep(ep);
 612
 613         if (dep->flags & DWC3_EP_ENABLED) {
 614                 WARN(true, "%s is already enabled\n",
 615                                 dep->name);
 616                 return 0;
 617         }
 618
 619         switch (usb_endpoint_type(desc)) {
 620         case USB_ENDPOINT_XFER_CONTROL:
 621                 strlcat(dep->name, "-control", sizeof(dep->name));
 622                 break;
 623         case USB_ENDPOINT_XFER_ISOC:
 624                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 625                 break;
 626         case USB_ENDPOINT_XFER_BULK:
 627                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 628                 break;
 629         case USB_ENDPOINT_XFER_INT:
 630                 strlcat(dep->name, "-int", sizeof(dep->name));
 631                 break;
 632         default:
 633                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 634         }
 635
 636         spin_lock_irqsave(&dwc->lock, flags);
 637         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 638         spin_unlock_irqrestore(&dwc->lock, flags);
 639
 640         return ret;
 641 }
 642
 643 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 644 {
 645         struct dwc3_ep                  *dep;
 646         unsigned long                   flags;
 647         int                             ret;
 648
 649         if (!ep) {
 650                 pr_debug("dwc3: invalid parameters\n");
 651                 return -EINVAL;
 652         }
 653
 654         dep = to_dwc3_ep(ep);
 655
 656         if (!(dep->flags & DWC3_EP_ENABLED)) {
 657                 WARN(true, "%s is already disabled\n",
 658                                 dep->name);
 659                 return 0;
 660         }
 661
 662         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 663                         dep->number >> 1,
 664                         (dep->number & 1) ? "in" : "out");
 665
 666         spin_lock_irqsave(&dwc->lock, flags);
 667         ret = __dwc3_gadget_ep_disable(dep);
 668         spin_unlock_irqrestore(&dwc->lock, flags);
 669
 670         return ret;
 671 }
 672
 673 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 674         gfp_t gfp_flags)
 675 {
 676         struct dwc3_request             *req;
 677         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 678
 679         req = kzalloc(sizeof(*req), gfp_flags);
 680         if (!req)
 681                 return NULL;
 682
 683         req->epnum      = dep->number;
 684         req->dep        = dep;
 685
 686         return &req->request;
 687 }
 688
 689 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 690                 struct usb_request *request)
 691 {
 692         struct dwc3_request             *req = to_dwc3_request(request);
 693
 694         kfree(req);
 695 }
 696
 697 /**
 698  * dwc3_prepare_one_trb - setup one TRB from one request
 699  * @dep: endpoint for which this request is prepared
 700  * @req: dwc3_request pointer
 701  */
 702 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 703                 struct dwc3_request *req, dma_addr_t dma,
 704                 unsigned length, unsigned last, unsigned chain, unsigned node)
 705 {
 706         struct dwc3_trb         *trb;
 707
 708         dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 709                         dep->name, req, (unsigned long long) dma,
 710                         length, last ? " last" : "",
 711                         chain ? " chain" : "");
 712
 713
 714         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 715
 716         if (!req->trb) {
 717                 dwc3_gadget_move_request_queued(req);
 718                 req->trb = trb;
 719                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 720                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 721         }
 722
 723         dep->free_slot++;
 724         /* Skip the LINK-TRB on ISOC */
 725         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 726                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 727                 dep->free_slot++;
 728
 729         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 730         trb->bpl = lower_32_bits(dma);
 731         trb->bph = upper_32_bits(dma);
 732
 733         switch (usb_endpoint_type(dep->endpoint.desc)) {
 734         case USB_ENDPOINT_XFER_CONTROL:
 735                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 736                 break;
 737
 738         case USB_ENDPOINT_XFER_ISOC:
 739                 if (!node)
 740                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 741                 else
 742                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 743                 break;
 744
 745         case USB_ENDPOINT_XFER_BULK:
 746         case USB_ENDPOINT_XFER_INT:
 747                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 748                 break;
 749         default:
 750                 /*
 751                  * This is only possible with faulty memory because we
 752                  * checked it already :)
 753                  */
 754                 BUG();
 755         }
 756
 757         if (!req->request.no_interrupt && !chain)
 758                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 759
 760         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 761                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 762                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 763         } else if (last) {
 764                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 765         }
 766
 767         if (chain)
 768                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 769
 770         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 771                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 772
 773         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 774
 775         dwc3_flush_cache((long)dma, length);
 776         dwc3_flush_cache((long)trb, sizeof(*trb));
 777 }
 778
 779 /*
 780  * dwc3_prepare_trbs - setup TRBs from requests
 781  * @dep: endpoint for which requests are being prepared
 782  * @starting: true if the endpoint is idle and no requests are queued.
 783  *
 784  * The function goes through the requests list and sets up TRBs for the
 785  * transfers. The function returns once there are no more TRBs available or
 786  * it runs out of requests.
 787  */
 788 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 789 {
 790         struct dwc3_request     *req, *n;
 791         u32                     trbs_left;
 792         u32                     max;
 793
 794         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 795
 796         /* the first request must not be queued */
 797         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 798
 799         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 800         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 801                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 802                 if (trbs_left > max)
 803                         trbs_left = max;
 804         }
 805
 806         /*
 807          * If busy & slot are equal than it is either full or empty. If we are
 808          * starting to process requests then we are empty. Otherwise we are
 809          * full and don't do anything
 810          */
 811         if (!trbs_left) {
 812                 if (!starting)
 813                         return;
 814                 trbs_left = DWC3_TRB_NUM;
 815                 /*
 816                  * In case we start from scratch, we queue the ISOC requests
 817                  * starting from slot 1. This is done because we use ring
 818                  * buffer and have no LST bit to stop us. Instead, we place
 819                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 820                  * after the first request so we start at slot 1 and have
 821                  * 7 requests proceed before we hit the first IOC.
 822                  * Other transfer types don't use the ring buffer and are
 823                  * processed from the first TRB until the last one. Since we
 824                  * don't wrap around we have to start at the beginning.
 825                  */
 826                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 827                         dep->busy_slot = 1;
 828                         dep->free_slot = 1;
 829                 } else {
 830                         dep->busy_slot = 0;
 831                         dep->free_slot = 0;
 832                 }
 833         }
 834
 835         /* The last TRB is a link TRB, not used for xfer */
 836         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 837                 return;
 838
 839         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 840                 unsigned        length;
 841                 dma_addr_t      dma;
 842
 843                 dma = req->request.dma;
 844                 length = req->request.length;
 845
 846                 dwc3_prepare_one_trb(dep, req, dma, length,
 847                                      true, false, 0);
 848
 849                 break;
 850         }
 851 }
 852
 853 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 854                 int start_new)
 855 {
 856         struct dwc3_gadget_ep_cmd_params params;
 857         struct dwc3_request             *req;
 858         struct dwc3                     *dwc = dep->dwc;
 859         int                             ret;
 860         u32                             cmd;
 861
 862         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 863                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 864                 return -EBUSY;
 865         }
 866         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 867
 868         /*
 869          * If we are getting here after a short-out-packet we don't enqueue any
 870          * new requests as we try to set the IOC bit only on the last request.
 871          */
 872         if (start_new) {
 873                 if (list_empty(&dep->req_queued))
 874                         dwc3_prepare_trbs(dep, start_new);
 875
 876                 /* req points to the first request which will be sent */
 877                 req = next_request(&dep->req_queued);
 878         } else {
 879                 dwc3_prepare_trbs(dep, start_new);
 880
 881                 /*
 882                  * req points to the first request where HWO changed from 0 to 1
 883                  */
 884                 req = next_request(&dep->req_queued);
 885         }
 886         if (!req) {
 887                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 888                 return 0;
 889         }
 890
 891         memset(&params, 0, sizeof(params));
 892
 893         if (start_new) {
 894                 params.param0 = upper_32_bits(req->trb_dma);
 895                 params.param1 = lower_32_bits(req->trb_dma);
 896                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 897         } else {
 898                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 899         }
 900
 901         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 902         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 903         if (ret < 0) {
 904                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 905
 906                 /*
 907                  * FIXME we need to iterate over the list of requests
 908                  * here and stop, unmap, free and del each of the linked
 909                  * requests instead of what we do now.
 910                  */
 911                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 912                                 req->direction);
 913                 list_del(&req->list);
 914                 return ret;
 915         }
 916
 917         dep->flags |= DWC3_EP_BUSY;
 918
 919         if (start_new) {
 920                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 921                                 dep->number);
 922                 WARN_ON_ONCE(!dep->resource_index);
 923         }
 924
 925         return 0;
 926 }
 927
 928 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
 929                 struct dwc3_ep *dep, u32 cur_uf)
 930 {
 931         u32 uf;
 932
 933         if (list_empty(&dep->request_list)) {
 934                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
 935                         dep->name);
 936                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 937                 return;
 938         }
 939
 940         /* 4 micro frames in the future */
 941         uf = cur_uf + dep->interval * 4;
 942
 943         __dwc3_gadget_kick_transfer(dep, uf, 1);
 944 }
 945
 946 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
 947                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
 948 {
 949         u32 cur_uf, mask;
 950
 951         mask = ~(dep->interval - 1);
 952         cur_uf = event->parameters & mask;
 953
 954         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
 955 }
 956
 957 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
 958 {
 959         struct dwc3             *dwc = dep->dwc;
 960         int                     ret;
 961
 962         req->request.actual     = 0;
 963         req->request.status     = -EINPROGRESS;
 964         req->direction          = dep->direction;
 965         req->epnum              = dep->number;
 966
 967         /*
 968          * DWC3 hangs on OUT requests smaller than maxpacket size,
 969          * so HACK the request length
 970          */
 971         if (dep->direction == 0 &&
 972             req->request.length < dep->endpoint.maxpacket)
 973                 req->request.length = dep->endpoint.maxpacket;
 974
 975         /*
 976          * We only add to our list of requests now and
 977          * start consuming the list once we get XferNotReady
 978          * IRQ.
 979          *
 980          * That way, we avoid doing anything that we don't need
 981          * to do now and defer it until the point we receive a
 982          * particular token from the Host side.
 983          *
 984          * This will also avoid Host cancelling URBs due to too
 985          * many NAKs.
 986          */
 987         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 988                         dep->direction);
 989         if (ret)
 990                 return ret;
 991
 992         list_add_tail(&req->list, &dep->request_list);
 993
 994         /*
 995          * There are a few special cases:
 996          *
 997          * 1. XferNotReady with empty list of requests. We need to kick the
 998          *    transfer here in that situation, otherwise we will be NAKing
 999          *    forever. If we get XferNotReady before gadget driver has a
1000          *    chance to queue a request, we will ACK the IRQ but won't be
1001          *    able to receive the data until the next request is queued.
1002          *    The following code is handling exactly that.
1003          *
1004          */
1005         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1006                 /*
1007                  * If xfernotready is already elapsed and it is a case
1008                  * of isoc transfer, then issue END TRANSFER, so that
1009                  * you can receive xfernotready again and can have
1010                  * notion of current microframe.
1011                  */
1012                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1013                         if (list_empty(&dep->req_queued)) {
1014                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1015                                 dep->flags = DWC3_EP_ENABLED;
1016                         }
1017                         return 0;
1018                 }
1019
1020                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1021                 if (ret && ret != -EBUSY)
1022                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1023                                         dep->name);
1024                 return ret;
1025         }
1026
1027         /*
1028          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1029          *    kick the transfer here after queuing a request, otherwise the
1030          *    core may not see the modified TRB(s).
1031          */
1032         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1033                         (dep->flags & DWC3_EP_BUSY) &&
1034                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1035                 WARN_ON_ONCE(!dep->resource_index);
1036                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1037                                 false);
1038                 if (ret && ret != -EBUSY)
1039                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1040                                         dep->name);
1041                 return ret;
1042         }
1043
1044         /*
1045          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1046          * right away, otherwise host will not know we have streams to be
1047          * handled.
1048          */
1049         if (dep->stream_capable) {
1050                 int     ret;
1051
1052                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1053                 if (ret && ret != -EBUSY) {
1054                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1055                                         dep->name);
1056                 }
1057         }
1058
1059         return 0;
1060 }
1061
1062 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1063         gfp_t gfp_flags)
1064 {
1065         struct dwc3_request             *req = to_dwc3_request(request);
1066         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1067
1068         unsigned long                   flags;
1069
1070         int                             ret;
1071
1072         spin_lock_irqsave(&dwc->lock, flags);
1073         if (!dep->endpoint.desc) {
1074                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1075                                 request, ep->name);
1076                 ret = -ESHUTDOWN;
1077                 goto out;
1078         }
1079
1080         if (req->dep != dep) {
1081                 WARN(true, "request %p belongs to '%s'\n",
1082                                 request, req->dep->name);
1083                 ret = -EINVAL;
1084                 goto out;
1085         }
1086
1087         dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1088                         request, ep->name, request->length);
1089
1090         ret = __dwc3_gadget_ep_queue(dep, req);
1091
1092 out:
1093         spin_unlock_irqrestore(&dwc->lock, flags);
1094
1095         return ret;
1096 }
1097
1098 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1099                 struct usb_request *request)
1100 {
1101         struct dwc3_request             *req = to_dwc3_request(request);
1102         struct dwc3_request             *r = NULL;
1103
1104         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1105         struct dwc3                     *dwc = dep->dwc;
1106
1107         unsigned long                   flags;
1108         int                             ret = 0;
1109
1110         spin_lock_irqsave(&dwc->lock, flags);
1111
1112         list_for_each_entry(r, &dep->request_list, list) {
1113                 if (r == req)
1114                         break;
1115         }
1116
1117         if (r != req) {
1118                 list_for_each_entry(r, &dep->req_queued, list) {
1119                         if (r == req)
1120                                 break;
1121                 }
1122                 if (r == req) {
1123                         /* wait until it is processed */
1124                         dwc3_stop_active_transfer(dwc, dep->number, true);
1125                         goto out1;
1126                 }
1127                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1128                                 request, ep->name);
1129                 ret = -EINVAL;
1130                 goto out0;
1131         }
1132
1133 out1:
1134         /* giveback the request */
1135         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1136
1137 out0:
1138         spin_unlock_irqrestore(&dwc->lock, flags);
1139
1140         return ret;
1141 }
1142
1143 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1144 {
1145         struct dwc3_gadget_ep_cmd_params        params;
1146         struct dwc3                             *dwc = dep->dwc;
1147         int                                     ret;
1148
1149         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1150                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1151                 return -EINVAL;
1152         }
1153
1154         memset(&params, 0x00, sizeof(params));
1155
1156         if (value) {
1157                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1158                                 (!list_empty(&dep->req_queued) ||
1159                                  !list_empty(&dep->request_list)))) {
1160                         dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1161                                         dep->name);
1162                         return -EAGAIN;
1163                 }
1164
1165                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1166                         DWC3_DEPCMD_SETSTALL, &params);
1167                 if (ret)
1168                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1169                                         dep->name);
1170                 else
1171                         dep->flags |= DWC3_EP_STALL;
1172         } else {
1173                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1174                         DWC3_DEPCMD_CLEARSTALL, &params);
1175                 if (ret)
1176                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1177                                         dep->name);
1178                 else
1179                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1180         }
1181
1182         return ret;
1183 }
1184
1185 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1186 {
1187         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1188
1189         unsigned long                   flags;
1190
1191         int                             ret;
1192
1193         spin_lock_irqsave(&dwc->lock, flags);
1194         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1195         spin_unlock_irqrestore(&dwc->lock, flags);
1196
1197         return ret;
1198 }
1199
1200 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1201 {
1202         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1203         unsigned long                   flags;
1204         int                             ret;
1205
1206         spin_lock_irqsave(&dwc->lock, flags);
1207         dep->flags |= DWC3_EP_WEDGE;
1208
1209         if (dep->number == 0 || dep->number == 1)
1210                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1211         else
1212                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1213         spin_unlock_irqrestore(&dwc->lock, flags);
1214
1215         return ret;
1216 }
1217
1218 /* -------------------------------------------------------------------------- */
1219
1220 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1221         .bLength        = USB_DT_ENDPOINT_SIZE,
1222         .bDescriptorType = USB_DT_ENDPOINT,
1223         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1224 };
1225
1226 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1227         .enable         = dwc3_gadget_ep0_enable,
1228         .disable        = dwc3_gadget_ep0_disable,
1229         .alloc_request  = dwc3_gadget_ep_alloc_request,
1230         .free_request   = dwc3_gadget_ep_free_request,
1231         .queue          = dwc3_gadget_ep0_queue,
1232         .dequeue        = dwc3_gadget_ep_dequeue,
1233         .set_halt       = dwc3_gadget_ep0_set_halt,
1234         .set_wedge      = dwc3_gadget_ep_set_wedge,
1235 };
1236
1237 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1238         .enable         = dwc3_gadget_ep_enable,
1239         .disable        = dwc3_gadget_ep_disable,
1240         .alloc_request  = dwc3_gadget_ep_alloc_request,
1241         .free_request   = dwc3_gadget_ep_free_request,
1242         .queue          = dwc3_gadget_ep_queue,
1243         .dequeue        = dwc3_gadget_ep_dequeue,
1244         .set_halt       = dwc3_gadget_ep_set_halt,
1245         .set_wedge      = dwc3_gadget_ep_set_wedge,
1246 };
1247
1248 /* -------------------------------------------------------------------------- */
1249
1250 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1251 {
1252         struct dwc3             *dwc = gadget_to_dwc(g);
1253         u32                     reg;
1254
1255         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1256         return DWC3_DSTS_SOFFN(reg);
1257 }
1258
1259 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1260 {
1261         struct dwc3             *dwc = gadget_to_dwc(g);
1262
1263         unsigned long           timeout;
1264         unsigned long           flags;
1265
1266         u32                     reg;
1267
1268         int                     ret = 0;
1269
1270         u8                      link_state;
1271         u8                      speed;
1272
1273         spin_lock_irqsave(&dwc->lock, flags);
1274
1275         /*
1276          * According to the Databook Remote wakeup request should
1277          * be issued only when the device is in early suspend state.
1278          *
1279          * We can check that via USB Link State bits in DSTS register.
1280          */
1281         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1282
1283         speed = reg & DWC3_DSTS_CONNECTSPD;
1284         if (speed == DWC3_DSTS_SUPERSPEED) {
1285                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1286                 ret = -EINVAL;
1287                 goto out;
1288         }
1289
1290         link_state = DWC3_DSTS_USBLNKST(reg);
1291
1292         switch (link_state) {
1293         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1294         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1295                 break;
1296         default:
1297                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1298                                 link_state);
1299                 ret = -EINVAL;
1300                 goto out;
1301         }
1302
1303         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1304         if (ret < 0) {
1305                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1306                 goto out;
1307         }
1308
1309         /* Recent versions do this automatically */
1310         if (dwc->revision < DWC3_REVISION_194A) {
1311                 /* write zeroes to Link Change Request */
1312                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1313                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1314                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1315         }
1316
1317         /* poll until Link State changes to ON */
1318         timeout = 1000;
1319
1320         while (timeout--) {
1321                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1322
1323                 /* in HS, means ON */
1324                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1325                         break;
1326         }
1327
1328         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1329                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1330                 ret = -EINVAL;
1331         }
1332
1333 out:
1334         spin_unlock_irqrestore(&dwc->lock, flags);
1335
1336         return ret;
1337 }
1338
1339 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1340                 int is_selfpowered)
1341 {
1342         struct dwc3             *dwc = gadget_to_dwc(g);
1343         unsigned long           flags;
1344
1345         spin_lock_irqsave(&dwc->lock, flags);
1346         dwc->is_selfpowered = !!is_selfpowered;
1347         spin_unlock_irqrestore(&dwc->lock, flags);
1348
1349         return 0;
1350 }
1351
1352 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1353 {
1354         u32                     reg;
1355         u32                     timeout = 500;
1356
1357         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1358         if (is_on) {
1359                 if (dwc->revision <= DWC3_REVISION_187A) {
1360                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1361                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1362                 }
1363
1364                 if (dwc->revision >= DWC3_REVISION_194A)
1365                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1366                 reg |= DWC3_DCTL_RUN_STOP;
1367
1368                 if (dwc->has_hibernation)
1369                         reg |= DWC3_DCTL_KEEP_CONNECT;
1370
1371                 dwc->pullups_connected = true;
1372         } else {
1373                 reg &= ~DWC3_DCTL_RUN_STOP;
1374
1375                 if (dwc->has_hibernation && !suspend)
1376                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1377
1378                 dwc->pullups_connected = false;
1379         }
1380
1381         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1382
1383         do {
1384                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1385                 if (is_on) {
1386                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1387                                 break;
1388                 } else {
1389                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1390                                 break;
1391                 }
1392                 timeout--;
1393                 if (!timeout)
1394                         return -ETIMEDOUT;
1395                 udelay(1);
1396         } while (1);
1397
1398         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1399                         dwc->gadget_driver
1400                         ? dwc->gadget_driver->function : "no-function",
1401                         is_on ? "connect" : "disconnect");
1402
1403         return 0;
1404 }
1405
1406 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1407 {
1408         struct dwc3             *dwc = gadget_to_dwc(g);
1409         unsigned long           flags;
1410         int                     ret;
1411
1412         is_on = !!is_on;
1413
1414         spin_lock_irqsave(&dwc->lock, flags);
1415         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1416         spin_unlock_irqrestore(&dwc->lock, flags);
1417
1418         return ret;
1419 }
1420
1421 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1422 {
1423         u32                     reg;
1424
1425         /* Enable all but Start and End of Frame IRQs */
1426         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1427                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1428                         DWC3_DEVTEN_CMDCMPLTEN |
1429                         DWC3_DEVTEN_ERRTICERREN |
1430                         DWC3_DEVTEN_WKUPEVTEN |
1431                         DWC3_DEVTEN_ULSTCNGEN |
1432                         DWC3_DEVTEN_CONNECTDONEEN |
1433                         DWC3_DEVTEN_USBRSTEN |
1434                         DWC3_DEVTEN_DISCONNEVTEN);
1435
1436         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1437 }
1438
1439 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1440 {
1441         /* mask all interrupts */
1442         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1443 }
1444
1445 static int dwc3_gadget_start(struct usb_gadget *g,
1446                 struct usb_gadget_driver *driver)
1447 {
1448         struct dwc3             *dwc = gadget_to_dwc(g);
1449         struct dwc3_ep          *dep;
1450         unsigned long           flags;
1451         int                     ret = 0;
1452         u32                     reg;
1453
1454         spin_lock_irqsave(&dwc->lock, flags);
1455
1456         if (dwc->gadget_driver) {
1457                 dev_err(dwc->dev, "%s is already bound to %s\n",
1458                                 dwc->gadget.name,
1459                                 dwc->gadget_driver->function);
1460                 ret = -EBUSY;
1461                 goto err1;
1462         }
1463
1464         dwc->gadget_driver      = driver;
1465
1466         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1467         reg &= ~(DWC3_DCFG_SPEED_MASK);
1468
1469         /**
1470          * WORKAROUND: DWC3 revision < 2.20a have an issue
1471          * which would cause metastability state on Run/Stop
1472          * bit if we try to force the IP to USB2-only mode.
1473          *
1474          * Because of that, we cannot configure the IP to any
1475          * speed other than the SuperSpeed
1476          *
1477          * Refers to:
1478          *
1479          * STAR#9000525659: Clock Domain Crossing on DCTL in
1480          * USB 2.0 Mode
1481          */
1482         if (dwc->revision < DWC3_REVISION_220A) {
1483                 reg |= DWC3_DCFG_SUPERSPEED;
1484         } else {
1485                 switch (dwc->maximum_speed) {
1486                 case USB_SPEED_LOW:
1487                         reg |= DWC3_DSTS_LOWSPEED;
1488                         break;
1489                 case USB_SPEED_FULL:
1490                         reg |= DWC3_DSTS_FULLSPEED1;
1491                         break;
1492                 case USB_SPEED_HIGH:
1493                         reg |= DWC3_DSTS_HIGHSPEED;
1494                         break;
1495                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1496                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1497                 default:
1498                         reg |= DWC3_DSTS_SUPERSPEED;
1499                 }
1500         }
1501         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1502
1503         dwc->start_config_issued = false;
1504
1505         /* Start with SuperSpeed Default */
1506         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1507
1508         dep = dwc->eps[0];
1509         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1510                         false);
1511         if (ret) {
1512                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1513                 goto err2;
1514         }
1515
1516         dep = dwc->eps[1];
1517         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1518                         false);
1519         if (ret) {
1520                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1521                 goto err3;
1522         }
1523
1524         /* begin to receive SETUP packets */
1525         dwc->ep0state = EP0_SETUP_PHASE;
1526         dwc3_ep0_out_start(dwc);
1527
1528         dwc3_gadget_enable_irq(dwc);
1529
1530         spin_unlock_irqrestore(&dwc->lock, flags);
1531
1532         return 0;
1533
1534 err3:
1535         __dwc3_gadget_ep_disable(dwc->eps[0]);
1536
1537 err2:
1538         dwc->gadget_driver = NULL;
1539
1540 err1:
1541         spin_unlock_irqrestore(&dwc->lock, flags);
1542
1543         return ret;
1544 }
1545
1546 static int dwc3_gadget_stop(struct usb_gadget *g)
1547 {
1548         struct dwc3             *dwc = gadget_to_dwc(g);
1549         unsigned long           flags;
1550
1551         spin_lock_irqsave(&dwc->lock, flags);
1552
1553         dwc3_gadget_disable_irq(dwc);
1554         __dwc3_gadget_ep_disable(dwc->eps[0]);
1555         __dwc3_gadget_ep_disable(dwc->eps[1]);
1556
1557         dwc->gadget_driver      = NULL;
1558
1559         spin_unlock_irqrestore(&dwc->lock, flags);
1560
1561         return 0;
1562 }
1563
1564 static const struct usb_gadget_ops dwc3_gadget_ops = {
1565         .get_frame              = dwc3_gadget_get_frame,
1566         .wakeup                 = dwc3_gadget_wakeup,
1567         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1568         .pullup                 = dwc3_gadget_pullup,
1569         .udc_start              = dwc3_gadget_start,
1570         .udc_stop               = dwc3_gadget_stop,
1571 };
1572
1573 /* -------------------------------------------------------------------------- */
1574
1575 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1576                 u8 num, u32 direction)
1577 {
1578         struct dwc3_ep                  *dep;
1579         u8                              i;
1580
1581         for (i = 0; i < num; i++) {
1582                 u8 epnum = (i << 1) | (!!direction);
1583
1584                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1585                 if (!dep)
1586                         return -ENOMEM;
1587
1588                 dep->dwc = dwc;
1589                 dep->number = epnum;
1590                 dep->direction = !!direction;
1591                 dwc->eps[epnum] = dep;
1592
1593                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1594                                 (epnum & 1) ? "in" : "out");
1595
1596                 dep->endpoint.name = dep->name;
1597
1598                 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1599
1600                 if (epnum == 0 || epnum == 1) {
1601                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1602                         dep->endpoint.maxburst = 1;
1603                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1604                         if (!epnum)
1605                                 dwc->gadget.ep0 = &dep->endpoint;
1606                 } else {
1607                         int             ret;
1608
1609                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1610                         dep->endpoint.max_streams = 15;
1611                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1612                         list_add_tail(&dep->endpoint.ep_list,
1613                                         &dwc->gadget.ep_list);
1614
1615                         ret = dwc3_alloc_trb_pool(dep);
1616                         if (ret)
1617                                 return ret;
1618                 }
1619
1620                 INIT_LIST_HEAD(&dep->request_list);
1621                 INIT_LIST_HEAD(&dep->req_queued);
1622         }
1623
1624         return 0;
1625 }
1626
1627 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1628 {
1629         int                             ret;
1630
1631         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1632
1633         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1634         if (ret < 0) {
1635                 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1636                 return ret;
1637         }
1638
1639         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1640         if (ret < 0) {
1641                 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1642                 return ret;
1643         }
1644
1645         return 0;
1646 }
1647
1648 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1649 {
1650         struct dwc3_ep                  *dep;
1651         u8                              epnum;
1652
1653         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1654                 dep = dwc->eps[epnum];
1655                 if (!dep)
1656                         continue;
1657                 /*
1658                  * Physical endpoints 0 and 1 are special; they form the
1659                  * bi-directional USB endpoint 0.
1660                  *
1661                  * For those two physical endpoints, we don't allocate a TRB
1662                  * pool nor do we add them the endpoints list. Due to that, we
1663                  * shouldn't do these two operations otherwise we would end up
1664                  * with all sorts of bugs when removing dwc3.ko.
1665                  */
1666                 if (epnum != 0 && epnum != 1) {
1667                         dwc3_free_trb_pool(dep);
1668                         list_del(&dep->endpoint.ep_list);
1669                 }
1670
1671                 kfree(dep);
1672         }
1673 }
1674
1675 /* -------------------------------------------------------------------------- */
1676
1677 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1678                 struct dwc3_request *req, struct dwc3_trb *trb,
1679                 const struct dwc3_event_depevt *event, int status)
1680 {
1681         unsigned int            count;
1682         unsigned int            s_pkt = 0;
1683         unsigned int            trb_status;
1684
1685         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1686                 /*
1687                  * We continue despite the error. There is not much we
1688                  * can do. If we don't clean it up we loop forever. If
1689                  * we skip the TRB then it gets overwritten after a
1690                  * while since we use them in a ring buffer. A BUG()
1691                  * would help. Lets hope that if this occurs, someone
1692                  * fixes the root cause instead of looking away :)
1693                  */
1694                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1695                                 dep->name, trb);
1696         count = trb->size & DWC3_TRB_SIZE_MASK;
1697
1698         if (dep->direction) {
1699                 if (count) {
1700                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1701                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1702                                 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1703                                                 dep->name);
1704                                 /*
1705                                  * If missed isoc occurred and there is
1706                                  * no request queued then issue END
1707                                  * TRANSFER, so that core generates
1708                                  * next xfernotready and we will issue
1709                                  * a fresh START TRANSFER.
1710                                  * If there are still queued request
1711                                  * then wait, do not issue either END
1712                                  * or UPDATE TRANSFER, just attach next
1713                                  * request in request_list during
1714                                  * giveback.If any future queued request
1715                                  * is successfully transferred then we
1716                                  * will issue UPDATE TRANSFER for all
1717                                  * request in the request_list.
1718                                  */
1719                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1720                         } else {
1721                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1722                                                 dep->name);
1723                                 status = -ECONNRESET;
1724                         }
1725                 } else {
1726                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1727                 }
1728         } else {
1729                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1730                         s_pkt = 1;
1731         }
1732
1733         /*
1734          * We assume here we will always receive the entire data block
1735          * which we should receive. Meaning, if we program RX to
1736          * receive 4K but we receive only 2K, we assume that's all we
1737          * should receive and we simply bounce the request back to the
1738          * gadget driver for further processing.
1739          */
1740         req->request.actual += req->request.length - count;
1741         if (s_pkt)
1742                 return 1;
1743         if ((event->status & DEPEVT_STATUS_LST) &&
1744                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1745                                 DWC3_TRB_CTRL_HWO)))
1746                 return 1;
1747         if ((event->status & DEPEVT_STATUS_IOC) &&
1748                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1749                 return 1;
1750         return 0;
1751 }
1752
1753 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1754                 const struct dwc3_event_depevt *event, int status)
1755 {
1756         struct dwc3_request     *req;
1757         struct dwc3_trb         *trb;
1758         unsigned int            slot;
1759
1760         req = next_request(&dep->req_queued);
1761         if (!req) {
1762                 WARN_ON_ONCE(1);
1763                 return 1;
1764         }
1765
1766         slot = req->start_slot;
1767         if ((slot == DWC3_TRB_NUM - 1) &&
1768             usb_endpoint_xfer_isoc(dep->endpoint.desc))
1769                 slot++;
1770         slot %= DWC3_TRB_NUM;
1771         trb = &dep->trb_pool[slot];
1772
1773         dwc3_flush_cache((long)trb, sizeof(*trb));
1774         __dwc3_cleanup_done_trbs(dwc, dep, req, trb, event, status);
1775         dwc3_gadget_giveback(dep, req, status);
1776
1777         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1778                         list_empty(&dep->req_queued)) {
1779                 if (list_empty(&dep->request_list)) {
1780                         /*
1781                          * If there is no entry in request list then do
1782                          * not issue END TRANSFER now. Just set PENDING
1783                          * flag, so that END TRANSFER is issued when an
1784                          * entry is added into request list.
1785                          */
1786                         dep->flags = DWC3_EP_PENDING_REQUEST;
1787                 } else {
1788                         dwc3_stop_active_transfer(dwc, dep->number, true);
1789                         dep->flags = DWC3_EP_ENABLED;
1790                 }
1791                 return 1;
1792         }
1793
1794         return 1;
1795 }
1796
1797 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1798                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1799 {
1800         unsigned                status = 0;
1801         int                     clean_busy;
1802
1803         if (event->status & DEPEVT_STATUS_BUSERR)
1804                 status = -ECONNRESET;
1805
1806         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1807         if (clean_busy)
1808                 dep->flags &= ~DWC3_EP_BUSY;
1809
1810         /*
1811          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1812          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1813          */
1814         if (dwc->revision < DWC3_REVISION_183A) {
1815                 u32             reg;
1816                 int             i;
1817
1818                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1819                         dep = dwc->eps[i];
1820
1821                         if (!(dep->flags & DWC3_EP_ENABLED))
1822                                 continue;
1823
1824                         if (!list_empty(&dep->req_queued))
1825                                 return;
1826                 }
1827
1828                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1829                 reg |= dwc->u1u2;
1830                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1831
1832                 dwc->u1u2 = 0;
1833         }
1834 }
1835
1836 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1837                 const struct dwc3_event_depevt *event)
1838 {
1839         struct dwc3_ep          *dep;
1840         u8                      epnum = event->endpoint_number;
1841
1842         dep = dwc->eps[epnum];
1843
1844         if (!(dep->flags & DWC3_EP_ENABLED))
1845                 return;
1846
1847         if (epnum == 0 || epnum == 1) {
1848                 dwc3_ep0_interrupt(dwc, event);
1849                 return;
1850         }
1851
1852         switch (event->endpoint_event) {
1853         case DWC3_DEPEVT_XFERCOMPLETE:
1854                 dep->resource_index = 0;
1855
1856                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1857                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1858                                         dep->name);
1859                         return;
1860                 }
1861
1862                 dwc3_endpoint_transfer_complete(dwc, dep, event);
1863                 break;
1864         case DWC3_DEPEVT_XFERINPROGRESS:
1865                 dwc3_endpoint_transfer_complete(dwc, dep, event);
1866                 break;
1867         case DWC3_DEPEVT_XFERNOTREADY:
1868                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1869                         dwc3_gadget_start_isoc(dwc, dep, event);
1870                 } else {
1871                         int ret;
1872
1873                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1874                                         dep->name, event->status &
1875                                         DEPEVT_STATUS_TRANSFER_ACTIVE
1876                                         ? "Transfer Active"
1877                                         : "Transfer Not Active");
1878
1879                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1880                         if (!ret || ret == -EBUSY)
1881                                 return;
1882
1883                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1884                                         dep->name);
1885                 }
1886
1887                 break;
1888         case DWC3_DEPEVT_STREAMEVT:
1889                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1890                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1891                                         dep->name);
1892                         return;
1893                 }
1894
1895                 switch (event->status) {
1896                 case DEPEVT_STREAMEVT_FOUND:
1897                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
1898                                         event->parameters);
1899
1900                         break;
1901                 case DEPEVT_STREAMEVT_NOTFOUND:
1902                         /* FALLTHROUGH */
1903                 default:
1904                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1905                 }
1906                 break;
1907         case DWC3_DEPEVT_RXTXFIFOEVT:
1908                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1909                 break;
1910         case DWC3_DEPEVT_EPCMDCMPLT:
1911                 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1912                 break;
1913         }
1914 }
1915
1916 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1917 {
1918         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1919                 spin_unlock(&dwc->lock);
1920                 dwc->gadget_driver->disconnect(&dwc->gadget);
1921                 spin_lock(&dwc->lock);
1922         }
1923 }
1924
1925 static void dwc3_suspend_gadget(struct dwc3 *dwc)
1926 {
1927         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
1928                 spin_unlock(&dwc->lock);
1929                 dwc->gadget_driver->suspend(&dwc->gadget);
1930                 spin_lock(&dwc->lock);
1931         }
1932 }
1933
1934 static void dwc3_resume_gadget(struct dwc3 *dwc)
1935 {
1936         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
1937                 spin_unlock(&dwc->lock);
1938                 dwc->gadget_driver->resume(&dwc->gadget);
1939         }
1940 }
1941
1942 static void dwc3_reset_gadget(struct dwc3 *dwc)
1943 {
1944         if (!dwc->gadget_driver)
1945                 return;
1946
1947         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
1948                 spin_unlock(&dwc->lock);
1949                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
1950                 spin_lock(&dwc->lock);
1951         }
1952 }
1953
1954 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
1955 {
1956         struct dwc3_ep *dep;
1957         struct dwc3_gadget_ep_cmd_params params;
1958         u32 cmd;
1959         int ret;
1960
1961         dep = dwc->eps[epnum];
1962
1963         if (!dep->resource_index)
1964                 return;
1965
1966         /*
1967          * NOTICE: We are violating what the Databook says about the
1968          * EndTransfer command. Ideally we would _always_ wait for the
1969          * EndTransfer Command Completion IRQ, but that's causing too
1970          * much trouble synchronizing between us and gadget driver.
1971          *
1972          * We have discussed this with the IP Provider and it was
1973          * suggested to giveback all requests here, but give HW some
1974          * extra time to synchronize with the interconnect. We're using
1975          * an arbitraty 100us delay for that.
1976          *
1977          * Note also that a similar handling was tested by Synopsys
1978          * (thanks a lot Paul) and nothing bad has come out of it.
1979          * In short, what we're doing is:
1980          *
1981          * - Issue EndTransfer WITH CMDIOC bit set
1982          * - Wait 100us
1983          */
1984
1985         cmd = DWC3_DEPCMD_ENDTRANSFER;
1986         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1987         cmd |= DWC3_DEPCMD_CMDIOC;
1988         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1989         memset(&params, 0, sizeof(params));
1990         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1991         WARN_ON_ONCE(ret);
1992         dep->resource_index = 0;
1993         dep->flags &= ~DWC3_EP_BUSY;
1994         udelay(100);
1995 }
1996
1997 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1998 {
1999         u32 epnum;
2000
2001         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2002                 struct dwc3_ep *dep;
2003
2004                 dep = dwc->eps[epnum];
2005                 if (!dep)
2006                         continue;
2007
2008                 if (!(dep->flags & DWC3_EP_ENABLED))
2009                         continue;
2010
2011                 dwc3_remove_requests(dwc, dep);
2012         }
2013 }
2014
2015 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2016 {
2017         u32 epnum;
2018
2019         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2020                 struct dwc3_ep *dep;
2021                 struct dwc3_gadget_ep_cmd_params params;
2022                 int ret;
2023
2024                 dep = dwc->eps[epnum];
2025                 if (!dep)
2026                         continue;
2027
2028                 if (!(dep->flags & DWC3_EP_STALL))
2029                         continue;
2030
2031                 dep->flags &= ~DWC3_EP_STALL;
2032
2033                 memset(&params, 0, sizeof(params));
2034                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2035                                 DWC3_DEPCMD_CLEARSTALL, &params);
2036                 WARN_ON_ONCE(ret);
2037         }
2038 }
2039
2040 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2041 {
2042         int                     reg;
2043
2044         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2045         reg &= ~DWC3_DCTL_INITU1ENA;
2046         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2047
2048         reg &= ~DWC3_DCTL_INITU2ENA;
2049         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2050
2051         dwc3_disconnect_gadget(dwc);
2052         dwc->start_config_issued = false;
2053
2054         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2055         dwc->setup_packet_pending = false;
2056         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2057 }
2058
2059 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2060 {
2061         u32                     reg;
2062
2063         /*
2064          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2065          * would cause a missing Disconnect Event if there's a
2066          * pending Setup Packet in the FIFO.
2067          *
2068          * There's no suggested workaround on the official Bug
2069          * report, which states that "unless the driver/application
2070          * is doing any special handling of a disconnect event,
2071          * there is no functional issue".
2072          *
2073          * Unfortunately, it turns out that we _do_ some special
2074          * handling of a disconnect event, namely complete all
2075          * pending transfers, notify gadget driver of the
2076          * disconnection, and so on.
2077          *
2078          * Our suggested workaround is to follow the Disconnect
2079          * Event steps here, instead, based on a setup_packet_pending
2080          * flag. Such flag gets set whenever we have a XferNotReady
2081          * event on EP0 and gets cleared on XferComplete for the
2082          * same endpoint.
2083          *
2084          * Refers to:
2085          *
2086          * STAR#9000466709: RTL: Device : Disconnect event not
2087          * generated if setup packet pending in FIFO
2088          */
2089         if (dwc->revision < DWC3_REVISION_188A) {
2090                 if (dwc->setup_packet_pending)
2091                         dwc3_gadget_disconnect_interrupt(dwc);
2092         }
2093
2094         dwc3_reset_gadget(dwc);
2095
2096         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2097         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2098         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2099         dwc->test_mode = false;
2100
2101         dwc3_stop_active_transfers(dwc);
2102         dwc3_clear_stall_all_ep(dwc);
2103         dwc->start_config_issued = false;
2104
2105         /* Reset device address to zero */
2106         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2107         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2108         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2109 }
2110
2111 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2112 {
2113         u32 reg;
2114         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2115
2116         /*
2117          * We change the clock only at SS but I dunno why I would want to do
2118          * this. Maybe it becomes part of the power saving plan.
2119          */
2120
2121         if (speed != DWC3_DSTS_SUPERSPEED)
2122                 return;
2123
2124         /*
2125          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2126          * each time on Connect Done.
2127          */
2128         if (!usb30_clock)
2129                 return;
2130
2131         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2132         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2133         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2134 }
2135
2136 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2137 {
2138         struct dwc3_ep          *dep;
2139         int                     ret;
2140         u32                     reg;
2141         u8                      speed;
2142
2143         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2144         speed = reg & DWC3_DSTS_CONNECTSPD;
2145         dwc->speed = speed;
2146
2147         dwc3_update_ram_clk_sel(dwc, speed);
2148
2149         switch (speed) {
2150         case DWC3_DCFG_SUPERSPEED:
2151                 /*
2152                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2153                  * would cause a missing USB3 Reset event.
2154                  *
2155                  * In such situations, we should force a USB3 Reset
2156                  * event by calling our dwc3_gadget_reset_interrupt()
2157                  * routine.
2158                  *
2159                  * Refers to:
2160                  *
2161                  * STAR#9000483510: RTL: SS : USB3 reset event may
2162                  * not be generated always when the link enters poll
2163                  */
2164                 if (dwc->revision < DWC3_REVISION_190A)
2165                         dwc3_gadget_reset_interrupt(dwc);
2166
2167                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2168                 dwc->gadget.ep0->maxpacket = 512;
2169                 dwc->gadget.speed = USB_SPEED_SUPER;
2170                 break;
2171         case DWC3_DCFG_HIGHSPEED:
2172                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2173                 dwc->gadget.ep0->maxpacket = 64;
2174                 dwc->gadget.speed = USB_SPEED_HIGH;
2175                 break;
2176         case DWC3_DCFG_FULLSPEED2:
2177         case DWC3_DCFG_FULLSPEED1:
2178                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2179                 dwc->gadget.ep0->maxpacket = 64;
2180                 dwc->gadget.speed = USB_SPEED_FULL;
2181                 break;
2182         case DWC3_DCFG_LOWSPEED:
2183                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2184                 dwc->gadget.ep0->maxpacket = 8;
2185                 dwc->gadget.speed = USB_SPEED_LOW;
2186                 break;
2187         }
2188
2189         /* Enable USB2 LPM Capability */
2190
2191         if ((dwc->revision > DWC3_REVISION_194A)
2192                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2193                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2194                 reg |= DWC3_DCFG_LPM_CAP;
2195                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2196
2197                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2198                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2199
2200                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2201
2202                 /*
2203                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2204                  * DCFG.LPMCap is set, core responses with an ACK and the
2205                  * BESL value in the LPM token is less than or equal to LPM
2206                  * NYET threshold.
2207                  */
2208                 if (dwc->revision < DWC3_REVISION_240A  && dwc->has_lpm_erratum)
2209                         WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2210
2211                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2212                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2213
2214                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2215         } else {
2216                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2217                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2218                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2219         }
2220
2221         dep = dwc->eps[0];
2222         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2223                         false);
2224         if (ret) {
2225                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2226                 return;
2227         }
2228
2229         dep = dwc->eps[1];
2230         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2231                         false);
2232         if (ret) {
2233                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2234                 return;
2235         }
2236
2237         /*
2238          * Configure PHY via GUSB3PIPECTLn if required.
2239          *
2240          * Update GTXFIFOSIZn
2241          *
2242          * In both cases reset values should be sufficient.
2243          */
2244 }
2245
2246 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2247 {
2248         /*
2249          * TODO take core out of low power mode when that's
2250          * implemented.
2251          */
2252
2253         dwc->gadget_driver->resume(&dwc->gadget);
2254 }
2255
2256 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2257                 unsigned int evtinfo)
2258 {
2259         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2260         unsigned int            pwropt;
2261
2262         /*
2263          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2264          * Hibernation mode enabled which would show up when device detects
2265          * host-initiated U3 exit.
2266          *
2267          * In that case, device will generate a Link State Change Interrupt
2268          * from U3 to RESUME which is only necessary if Hibernation is
2269          * configured in.
2270          *
2271          * There are no functional changes due to such spurious event and we
2272          * just need to ignore it.
2273          *
2274          * Refers to:
2275          *
2276          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2277          * operational mode
2278          */
2279         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2280         if ((dwc->revision < DWC3_REVISION_250A) &&
2281                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2282                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2283                                 (next == DWC3_LINK_STATE_RESUME)) {
2284                         dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2285                         return;
2286                 }
2287         }
2288
2289         /*
2290          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2291          * on the link partner, the USB session might do multiple entry/exit
2292          * of low power states before a transfer takes place.
2293          *
2294          * Due to this problem, we might experience lower throughput. The
2295          * suggested workaround is to disable DCTL[12:9] bits if we're
2296          * transitioning from U1/U2 to U0 and enable those bits again
2297          * after a transfer completes and there are no pending transfers
2298          * on any of the enabled endpoints.
2299          *
2300          * This is the first half of that workaround.
2301          *
2302          * Refers to:
2303          *
2304          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2305          * core send LGO_Ux entering U0
2306          */
2307         if (dwc->revision < DWC3_REVISION_183A) {
2308                 if (next == DWC3_LINK_STATE_U0) {
2309                         u32     u1u2;
2310                         u32     reg;
2311
2312                         switch (dwc->link_state) {
2313                         case DWC3_LINK_STATE_U1:
2314                         case DWC3_LINK_STATE_U2:
2315                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2316                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2317                                                 | DWC3_DCTL_ACCEPTU2ENA
2318                                                 | DWC3_DCTL_INITU1ENA
2319                                                 | DWC3_DCTL_ACCEPTU1ENA);
2320
2321                                 if (!dwc->u1u2)
2322                                         dwc->u1u2 = reg & u1u2;
2323
2324                                 reg &= ~u1u2;
2325
2326                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2327                                 break;
2328                         default:
2329                                 /* do nothing */
2330                                 break;
2331                         }
2332                 }
2333         }
2334
2335         switch (next) {
2336         case DWC3_LINK_STATE_U1:
2337                 if (dwc->speed == USB_SPEED_SUPER)
2338                         dwc3_suspend_gadget(dwc);
2339                 break;
2340         case DWC3_LINK_STATE_U2:
2341         case DWC3_LINK_STATE_U3:
2342                 dwc3_suspend_gadget(dwc);
2343                 break;
2344         case DWC3_LINK_STATE_RESUME:
2345                 dwc3_resume_gadget(dwc);
2346                 break;
2347         default:
2348                 /* do nothing */
2349                 break;
2350         }
2351
2352         dwc->link_state = next;
2353 }
2354
2355 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2356                 unsigned int evtinfo)
2357 {
2358         unsigned int is_ss = evtinfo & (1UL << 4);
2359
2360         /**
2361          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2362          * have a known issue which can cause USB CV TD.9.23 to fail
2363          * randomly.
2364          *
2365          * Because of this issue, core could generate bogus hibernation
2366          * events which SW needs to ignore.
2367          *
2368          * Refers to:
2369          *
2370          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2371          * Device Fallback from SuperSpeed
2372          */
2373         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2374                 return;
2375
2376         /* enter hibernation here */
2377 }
2378
2379 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2380                 const struct dwc3_event_devt *event)
2381 {
2382         switch (event->type) {
2383         case DWC3_DEVICE_EVENT_DISCONNECT:
2384                 dwc3_gadget_disconnect_interrupt(dwc);
2385                 break;
2386         case DWC3_DEVICE_EVENT_RESET:
2387                 dwc3_gadget_reset_interrupt(dwc);
2388                 break;
2389         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2390                 dwc3_gadget_conndone_interrupt(dwc);
2391                 break;
2392         case DWC3_DEVICE_EVENT_WAKEUP:
2393                 dwc3_gadget_wakeup_interrupt(dwc);
2394                 break;
2395         case DWC3_DEVICE_EVENT_HIBER_REQ:
2396                 if (!dwc->has_hibernation) {
2397                         WARN(1 ,"unexpected hibernation event\n");
2398                         break;
2399                 }
2400                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2401                 break;
2402         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2403                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2404                 break;
2405         case DWC3_DEVICE_EVENT_EOPF:
2406                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2407                 break;
2408         case DWC3_DEVICE_EVENT_SOF:
2409                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2410                 break;
2411         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2412                 dev_vdbg(dwc->dev, "Erratic Error\n");
2413                 break;
2414         case DWC3_DEVICE_EVENT_CMD_CMPL:
2415                 dev_vdbg(dwc->dev, "Command Complete\n");
2416                 break;
2417         case DWC3_DEVICE_EVENT_OVERFLOW:
2418                 dev_vdbg(dwc->dev, "Overflow\n");
2419                 break;
2420         default:
2421                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2422         }
2423 }
2424
2425 static void dwc3_process_event_entry(struct dwc3 *dwc,
2426                 const union dwc3_event *event)
2427 {
2428         /* Endpoint IRQ, handle it and return early */
2429         if (event->type.is_devspec == 0) {
2430                 /* depevt */
2431                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2432         }
2433
2434         switch (event->type.type) {
2435         case DWC3_EVENT_TYPE_DEV:
2436                 dwc3_gadget_interrupt(dwc, &event->devt);
2437                 break;
2438         /* REVISIT what to do with Carkit and I2C events ? */
2439         default:
2440                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2441         }
2442 }
2443
2444 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2445 {
2446         struct dwc3_event_buffer *evt;
2447         irqreturn_t ret = IRQ_NONE;
2448         int left;
2449         u32 reg;
2450
2451         evt = dwc->ev_buffs[buf];
2452         left = evt->count;
2453
2454         if (!(evt->flags & DWC3_EVENT_PENDING))
2455                 return IRQ_NONE;
2456
2457         while (left > 0) {
2458                 union dwc3_event event;
2459
2460                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2461
2462                 dwc3_process_event_entry(dwc, &event);
2463
2464                 /*
2465                  * FIXME we wrap around correctly to the next entry as
2466                  * almost all entries are 4 bytes in size. There is one
2467                  * entry which has 12 bytes which is a regular entry
2468                  * followed by 8 bytes data. ATM I don't know how
2469                  * things are organized if we get next to the a
2470                  * boundary so I worry about that once we try to handle
2471                  * that.
2472                  */
2473                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2474                 left -= 4;
2475
2476                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2477         }
2478
2479         evt->count = 0;
2480         evt->flags &= ~DWC3_EVENT_PENDING;
2481         ret = IRQ_HANDLED;
2482
2483         /* Unmask interrupt */
2484         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2485         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2486         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2487
2488         return ret;
2489 }
2490
2491 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2492 {
2493         struct dwc3 *dwc = _dwc;
2494         unsigned long flags;
2495         irqreturn_t ret = IRQ_NONE;
2496         int i;
2497
2498         spin_lock_irqsave(&dwc->lock, flags);
2499
2500         for (i = 0; i < dwc->num_event_buffers; i++)
2501                 ret |= dwc3_process_event_buf(dwc, i);
2502
2503         spin_unlock_irqrestore(&dwc->lock, flags);
2504
2505         return ret;
2506 }
2507
2508 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2509 {
2510         struct dwc3_event_buffer *evt;
2511         u32 count;
2512         u32 reg;
2513
2514         evt = dwc->ev_buffs[buf];
2515
2516         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2517         count &= DWC3_GEVNTCOUNT_MASK;
2518         if (!count)
2519                 return IRQ_NONE;
2520
2521         evt->count = count;
2522         evt->flags |= DWC3_EVENT_PENDING;
2523
2524         /* Mask interrupt */
2525         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2526         reg |= DWC3_GEVNTSIZ_INTMASK;
2527         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2528
2529         return IRQ_WAKE_THREAD;
2530 }
2531
2532 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2533 {
2534         struct dwc3                     *dwc = _dwc;
2535         int                             i;
2536         irqreturn_t                     ret = IRQ_NONE;
2537
2538         spin_lock(&dwc->lock);
2539
2540         for (i = 0; i < dwc->num_event_buffers; i++) {
2541                 irqreturn_t status;
2542
2543                 status = dwc3_check_event_buf(dwc, i);
2544                 if (status == IRQ_WAKE_THREAD)
2545                         ret = status;
2546         }
2547
2548         spin_unlock(&dwc->lock);
2549
2550         return ret;
2551 }
2552
2553 /**
2554  * dwc3_gadget_init - Initializes gadget related registers
2555  * @dwc: pointer to our controller context structure
2556  *
2557  * Returns 0 on success otherwise negative errno.
2558  */
2559 int dwc3_gadget_init(struct dwc3 *dwc)
2560 {
2561         int                                     ret;
2562
2563         dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req),
2564                                         (unsigned long *)&dwc->ctrl_req_addr);
2565         if (!dwc->ctrl_req) {
2566                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2567                 ret = -ENOMEM;
2568                 goto err0;
2569         }
2570
2571         dwc->ep0_trb = dma_alloc_coherent(sizeof(*dwc->ep0_trb) * 2,
2572                                           (unsigned long *)&dwc->ep0_trb_addr);
2573         if (!dwc->ep0_trb) {
2574                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2575                 ret = -ENOMEM;
2576                 goto err1;
2577         }
2578
2579         dwc->setup_buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
2580                                   DWC3_EP0_BOUNCE_SIZE);
2581         if (!dwc->setup_buf) {
2582                 ret = -ENOMEM;
2583                 goto err2;
2584         }
2585
2586         dwc->ep0_bounce = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE,
2587                                         (unsigned long *)&dwc->ep0_bounce_addr);
2588         if (!dwc->ep0_bounce) {
2589                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2590                 ret = -ENOMEM;
2591                 goto err3;
2592         }
2593
2594         dwc->gadget.ops                 = &dwc3_gadget_ops;
2595         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2596         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2597         dwc->gadget.name                = "dwc3-gadget";
2598
2599         /*
2600          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2601          * on ep out.
2602          */
2603         dwc->gadget.quirk_ep_out_aligned_size = true;
2604
2605         /*
2606          * REVISIT: Here we should clear all pending IRQs to be
2607          * sure we're starting from a well known location.
2608          */
2609
2610         ret = dwc3_gadget_init_endpoints(dwc);
2611         if (ret)
2612                 goto err4;
2613
2614         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2615         if (ret) {
2616                 dev_err(dwc->dev, "failed to register udc\n");
2617                 goto err4;
2618         }
2619
2620         return 0;
2621
2622 err4:
2623         dwc3_gadget_free_endpoints(dwc);
2624         dma_free_coherent(dwc->ep0_bounce);
2625
2626 err3:
2627         kfree(dwc->setup_buf);
2628
2629 err2:
2630         dma_free_coherent(dwc->ep0_trb);
2631
2632 err1:
2633         dma_free_coherent(dwc->ctrl_req);
2634
2635 err0:
2636         return ret;
2637 }
2638
2639 /* -------------------------------------------------------------------------- */
2640
2641 void dwc3_gadget_exit(struct dwc3 *dwc)
2642 {
2643         usb_del_gadget_udc(&dwc->gadget);
2644
2645         dwc3_gadget_free_endpoints(dwc);
2646
2647         dma_free_coherent(dwc->ep0_bounce);
2648
2649         kfree(dwc->setup_buf);
2650
2651         dma_free_coherent(dwc->ep0_trb);
2652
2653         dma_free_coherent(dwc->ctrl_req);
2654 }
2655
2656 /**
2657  * dwc3_gadget_uboot_handle_interrupt - handle dwc3 gadget interrupt
2658  * @dwc: struct dwce *
2659  *
2660  * Handles ep0 and gadget interrupt
2661  *
2662  * Should be called from dwc3 core.
2663  */
2664 void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
2665 {
2666         int ret = dwc3_interrupt(0, dwc);
2667
2668         if (ret == IRQ_WAKE_THREAD) {
2669                 int i;
2670                 struct dwc3_event_buffer *evt;
2671
2672                 for (i = 0; i < dwc->num_event_buffers; i++) {
2673                         evt = dwc->ev_buffs[i];
2674                         dwc3_flush_cache((long)evt->buf, evt->length);
2675                 }
2676
2677                 dwc3_thread_interrupt(0, dwc);
2678         }
2679 }