drivers/spi/fsl_qspi.c

   1 /*
   2  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   3  *
   4  * Freescale Quad Serial Peripheral Interface (QSPI) driver
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <malloc.h>
  11 #include <spi.h>
  12 #include <asm/io.h>
  13 #include <linux/sizes.h>
  14 #include <dm.h>
  15 #include <errno.h>
  16 #include <watchdog.h>
  17 #include "fsl_qspi.h"
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #define RX_BUFFER_SIZE          0x80
  22 #ifdef CONFIG_MX6SX
  23 #define TX_BUFFER_SIZE          0x200
  24 #else
  25 #define TX_BUFFER_SIZE          0x40
  26 #endif
  27
  28 #define OFFSET_BITS_MASK        GENMASK(23, 0)
  29
  30 #define FLASH_STATUS_WEL        0x02
  31
  32 /* SEQID */
  33 #define SEQID_WREN              1
  34 #define SEQID_FAST_READ         2
  35 #define SEQID_RDSR              3
  36 #define SEQID_SE                4
  37 #define SEQID_CHIP_ERASE        5
  38 #define SEQID_PP                6
  39 #define SEQID_RDID              7
  40 #define SEQID_BE_4K             8
  41 #ifdef CONFIG_SPI_FLASH_BAR
  42 #define SEQID_BRRD              9
  43 #define SEQID_BRWR              10
  44 #define SEQID_RDEAR             11
  45 #define SEQID_WREAR             12
  46 #endif
  47 #define SEQID_WRAR              13
  48 #define SEQID_RDAR              14
  49
  50 /* QSPI CMD */
  51 #define QSPI_CMD_PP             0x02    /* Page program (up to 256 bytes) */
  52 #define QSPI_CMD_RDSR           0x05    /* Read status register */
  53 #define QSPI_CMD_WREN           0x06    /* Write enable */
  54 #define QSPI_CMD_FAST_READ      0x0b    /* Read data bytes (high frequency) */
  55 #define QSPI_CMD_BE_4K          0x20    /* 4K erase */
  56 #define QSPI_CMD_CHIP_ERASE     0xc7    /* Erase whole flash chip */
  57 #define QSPI_CMD_SE             0xd8    /* Sector erase (usually 64KiB) */
  58 #define QSPI_CMD_RDID           0x9f    /* Read JEDEC ID */
  59
  60 /* Used for Micron, winbond and Macronix flashes */
  61 #define QSPI_CMD_WREAR          0xc5    /* EAR register write */
  62 #define QSPI_CMD_RDEAR          0xc8    /* EAR reigster read */
  63
  64 /* Used for Spansion flashes only. */
  65 #define QSPI_CMD_BRRD           0x16    /* Bank register read */
  66 #define QSPI_CMD_BRWR           0x17    /* Bank register write */
  67
  68 /* Used for Spansion S25FS-S family flash only. */
  69 #define QSPI_CMD_RDAR           0x65    /* Read any device register */
  70 #define QSPI_CMD_WRAR           0x71    /* Write any device register */
  71
  72 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
  73 #define QSPI_CMD_FAST_READ_4B   0x0c    /* Read data bytes (high frequency) */
  74 #define QSPI_CMD_PP_4B          0x12    /* Page program (up to 256 bytes) */
  75 #define QSPI_CMD_SE_4B          0xdc    /* Sector erase (usually 64KiB) */
  76
  77 /* fsl_qspi_platdata flags */
  78 #define QSPI_FLAG_REGMAP_ENDIAN_BIG     BIT(0)
  79
  80 /* default SCK frequency, unit: HZ */
  81 #define FSL_QSPI_DEFAULT_SCK_FREQ       50000000
  82
  83 /* QSPI max chipselect signals number */
  84 #define FSL_QSPI_MAX_CHIPSELECT_NUM     4
  85
  86 #ifdef CONFIG_DM_SPI
  87 /**
  88  * struct fsl_qspi_platdata - platform data for Freescale QSPI
  89  *
  90  * @flags: Flags for QSPI QSPI_FLAG_...
  91  * @speed_hz: Default SCK frequency
  92  * @reg_base: Base address of QSPI registers
  93  * @amba_base: Base address of QSPI memory mapping
  94  * @amba_total_size: size of QSPI memory mapping
  95  * @flash_num: Number of active slave devices
  96  * @num_chipselect: Number of QSPI chipselect signals
  97  */
  98 struct fsl_qspi_platdata {
  99         u32 flags;
 100         u32 speed_hz;
 101         fdt_addr_t reg_base;
 102         fdt_addr_t amba_base;
 103         fdt_size_t amba_total_size;
 104         u32 flash_num;
 105         u32 num_chipselect;
 106 };
 107 #endif
 108
 109 /**
 110  * struct fsl_qspi_priv - private data for Freescale QSPI
 111  *
 112  * @flags: Flags for QSPI QSPI_FLAG_...
 113  * @bus_clk: QSPI input clk frequency
 114  * @speed_hz: Default SCK frequency
 115  * @cur_seqid: current LUT table sequence id
 116  * @sf_addr: flash access offset
 117  * @amba_base: Base address of QSPI memory mapping of every CS
 118  * @amba_total_size: size of QSPI memory mapping
 119  * @cur_amba_base: Base address of QSPI memory mapping of current CS
 120  * @flash_num: Number of active slave devices
 121  * @num_chipselect: Number of QSPI chipselect signals
 122  * @regs: Point to QSPI register structure for I/O access
 123  */
 124 struct fsl_qspi_priv {
 125         u32 flags;
 126         u32 bus_clk;
 127         u32 speed_hz;
 128         u32 cur_seqid;
 129         u32 sf_addr;
 130         u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
 131         u32 amba_total_size;
 132         u32 cur_amba_base;
 133         u32 flash_num;
 134         u32 num_chipselect;
 135         struct fsl_qspi_regs *regs;
 136 };
 137
 138 #ifndef CONFIG_DM_SPI
 139 struct fsl_qspi {
 140         struct spi_slave slave;
 141         struct fsl_qspi_priv priv;
 142 };
 143 #endif
 144
 145 static u32 qspi_read32(u32 flags, u32 *addr)
 146 {
 147         return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 148                 in_be32(addr) : in_le32(addr);
 149 }
 150
 151 static void qspi_write32(u32 flags, u32 *addr, u32 val)
 152 {
 153         flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 154                 out_be32(addr, val) : out_le32(addr, val);
 155 }
 156
 157 /* QSPI support swapping the flash read/write data
 158  * in hardware for LS102xA, but not for VF610 */
 159 static inline u32 qspi_endian_xchg(u32 data)
 160 {
 161 #ifdef CONFIG_VF610
 162         return swab32(data);
 163 #else
 164         return data;
 165 #endif
 166 }
 167
 168 static void qspi_set_lut(struct fsl_qspi_priv *priv)
 169 {
 170         struct fsl_qspi_regs *regs = priv->regs;
 171         u32 lut_base;
 172
 173         /* Unlock the LUT */
 174         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 175         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
 176
 177         /* Write Enable */
 178         lut_base = SEQID_WREN * 4;
 179         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
 180                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 181         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 182         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 183         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 184
 185         /* Fast Read */
 186         lut_base = SEQID_FAST_READ * 4;
 187 #ifdef CONFIG_SPI_FLASH_BAR
 188         qspi_write32(priv->flags, &regs->lut[lut_base],
 189                      OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 190                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 191                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 192 #else
 193         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 194                 qspi_write32(priv->flags, &regs->lut[lut_base],
 195                              OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 196                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 197                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 198         else
 199                 qspi_write32(priv->flags, &regs->lut[lut_base],
 200                              OPRND0(QSPI_CMD_FAST_READ_4B) |
 201                              PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
 202                              OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
 203                              INSTR1(LUT_ADDR));
 204 #endif
 205         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 206                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 207                      OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
 208                      INSTR1(LUT_READ));
 209         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 210         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 211
 212         /* Read Status */
 213         lut_base = SEQID_RDSR * 4;
 214         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
 215                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 216                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 217         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 218         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 219         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 220
 221         /* Erase a sector */
 222         lut_base = SEQID_SE * 4;
 223 #ifdef CONFIG_SPI_FLASH_BAR
 224         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
 225                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 226                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 227 #else
 228         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 229                 qspi_write32(priv->flags, &regs->lut[lut_base],
 230                              OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
 231                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 232                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 233         else
 234                 qspi_write32(priv->flags, &regs->lut[lut_base],
 235                              OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
 236                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 237                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 238 #endif
 239         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 240         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 241         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 242
 243         /* Erase the whole chip */
 244         lut_base = SEQID_CHIP_ERASE * 4;
 245         qspi_write32(priv->flags, &regs->lut[lut_base],
 246                      OPRND0(QSPI_CMD_CHIP_ERASE) |
 247                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 248         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 249         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 250         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 251
 252         /* Page Program */
 253         lut_base = SEQID_PP * 4;
 254 #ifdef CONFIG_SPI_FLASH_BAR
 255         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
 256                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 257                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 258 #else
 259         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 260                 qspi_write32(priv->flags, &regs->lut[lut_base],
 261                              OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
 262                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 263                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 264         else
 265                 qspi_write32(priv->flags, &regs->lut[lut_base],
 266                              OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
 267                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 268                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 269 #endif
 270 #ifdef CONFIG_MX6SX
 271         /*
 272          * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
 273          * So, Use IDATSZ in IPCR to determine the size and here set 0.
 274          */
 275         qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
 276                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 277 #else
 278         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 279                      OPRND0(TX_BUFFER_SIZE) |
 280                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 281 #endif
 282         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 283         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 284
 285         /* READ ID */
 286         lut_base = SEQID_RDID * 4;
 287         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
 288                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
 289                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 290         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 291         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 292         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 293
 294         /* SUB SECTOR 4K ERASE */
 295         lut_base = SEQID_BE_4K * 4;
 296         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
 297                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 298                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 299
 300 #ifdef CONFIG_SPI_FLASH_BAR
 301         /*
 302          * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
 303          * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
 304          * initialization.
 305          */
 306         lut_base = SEQID_BRRD * 4;
 307         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
 308                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 309                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 310
 311         lut_base = SEQID_BRWR * 4;
 312         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
 313                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 314                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 315
 316         lut_base = SEQID_RDEAR * 4;
 317         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
 318                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 319                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 320
 321         lut_base = SEQID_WREAR * 4;
 322         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
 323                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 324                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 325 #endif
 326
 327         /*
 328          * Read any device register.
 329          * Used for Spansion S25FS-S family flash only.
 330          */
 331         lut_base = SEQID_RDAR * 4;
 332         qspi_write32(priv->flags, &regs->lut[lut_base],
 333                      OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
 334                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 335                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 336         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 337                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 338                      OPRND1(1) | PAD1(LUT_PAD1) |
 339                      INSTR1(LUT_READ));
 340
 341         /*
 342          * Write any device register.
 343          * Used for Spansion S25FS-S family flash only.
 344          */
 345         lut_base = SEQID_WRAR * 4;
 346         qspi_write32(priv->flags, &regs->lut[lut_base],
 347                      OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
 348                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 349                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 350         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 351                      OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 352
 353         /* Lock the LUT */
 354         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 355         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
 356 }
 357
 358 #if defined(CONFIG_SYS_FSL_QSPI_AHB)
 359 /*
 360  * If we have changed the content of the flash by writing or erasing,
 361  * we need to invalidate the AHB buffer. If we do not do so, we may read out
 362  * the wrong data. The spec tells us reset the AHB domain and Serial Flash
 363  * domain at the same time.
 364  */
 365 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
 366 {
 367         struct fsl_qspi_regs *regs = priv->regs;
 368         u32 reg;
 369
 370         reg = qspi_read32(priv->flags, &regs->mcr);
 371         reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
 372         qspi_write32(priv->flags, &regs->mcr, reg);
 373
 374         /*
 375          * The minimum delay : 1 AHB + 2 SFCK clocks.
 376          * Delay 1 us is enough.
 377          */
 378         udelay(1);
 379
 380         reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
 381         qspi_write32(priv->flags, &regs->mcr, reg);
 382 }
 383
 384 /* Read out the data from the AHB buffer. */
 385 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
 386 {
 387         struct fsl_qspi_regs *regs = priv->regs;
 388         u32 mcr_reg;
 389
 390         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 391
 392         qspi_write32(priv->flags, &regs->mcr,
 393                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 394                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 395
 396         /* Read out the data directly from the AHB buffer. */
 397         memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
 398
 399         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 400 }
 401
 402 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
 403 {
 404         u32 reg, reg2;
 405         struct fsl_qspi_regs *regs = priv->regs;
 406
 407         reg = qspi_read32(priv->flags, &regs->mcr);
 408         /* Disable the module */
 409         qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
 410
 411         /* Set the Sampling Register for DDR */
 412         reg2 = qspi_read32(priv->flags, &regs->smpr);
 413         reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
 414         reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
 415         qspi_write32(priv->flags, &regs->smpr, reg2);
 416
 417         /* Enable the module again (enable the DDR too) */
 418         reg |= QSPI_MCR_DDR_EN_MASK;
 419         /* Enable bit 29 for imx6sx */
 420         reg |= BIT(29);
 421
 422         qspi_write32(priv->flags, &regs->mcr, reg);
 423 }
 424
 425 /*
 426  * There are two different ways to read out the data from the flash:
 427  *  the "IP Command Read" and the "AHB Command Read".
 428  *
 429  * The IC guy suggests we use the "AHB Command Read" which is faster
 430  * then the "IP Command Read". (What's more is that there is a bug in
 431  * the "IP Command Read" in the Vybrid.)
 432  *
 433  * After we set up the registers for the "AHB Command Read", we can use
 434  * the memcpy to read the data directly. A "missed" access to the buffer
 435  * causes the controller to clear the buffer, and use the sequence pointed
 436  * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
 437  */
 438 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
 439 {
 440         struct fsl_qspi_regs *regs = priv->regs;
 441
 442         /* AHB configuration for access buffer 0/1/2 .*/
 443         qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
 444         qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
 445         qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
 446         qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
 447                      (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
 448
 449         /* We only use the buffer3 */
 450         qspi_write32(priv->flags, &regs->buf0ind, 0);
 451         qspi_write32(priv->flags, &regs->buf1ind, 0);
 452         qspi_write32(priv->flags, &regs->buf2ind, 0);
 453
 454         /*
 455          * Set the default lut sequence for AHB Read.
 456          * Parallel mode is disabled.
 457          */
 458         qspi_write32(priv->flags, &regs->bfgencr,
 459                      SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
 460
 461         /*Enable DDR Mode*/
 462         qspi_enable_ddr_mode(priv);
 463 }
 464 #endif
 465
 466 #ifdef CONFIG_SPI_FLASH_BAR
 467 /* Bank register read/write, EAR register read/write */
 468 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
 469 {
 470         struct fsl_qspi_regs *regs = priv->regs;
 471         u32 reg, mcr_reg, data, seqid;
 472
 473         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 474         qspi_write32(priv->flags, &regs->mcr,
 475                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 476                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 477         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 478
 479         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 480
 481         if (priv->cur_seqid == QSPI_CMD_BRRD)
 482                 seqid = SEQID_BRRD;
 483         else
 484                 seqid = SEQID_RDEAR;
 485
 486         qspi_write32(priv->flags, &regs->ipcr,
 487                      (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
 488
 489         /* Wait previous command complete */
 490         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 491                 ;
 492
 493         while (1) {
 494                 reg = qspi_read32(priv->flags, &regs->rbsr);
 495                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 496                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 497                         data = qspi_endian_xchg(data);
 498                         memcpy(rxbuf, &data, len);
 499                         qspi_write32(priv->flags, &regs->mcr,
 500                                      qspi_read32(priv->flags, &regs->mcr) |
 501                                      QSPI_MCR_CLR_RXF_MASK);
 502                         break;
 503                 }
 504         }
 505
 506         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 507 }
 508 #endif
 509
 510 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 511 {
 512         struct fsl_qspi_regs *regs = priv->regs;
 513         u32 mcr_reg, rbsr_reg, data, size;
 514         int i;
 515
 516         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 517         qspi_write32(priv->flags, &regs->mcr,
 518                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 519                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 520         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 521
 522         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 523
 524         qspi_write32(priv->flags, &regs->ipcr,
 525                      (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
 526         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 527                 ;
 528
 529         i = 0;
 530         while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
 531                 rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
 532                 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
 533                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 534                         data = qspi_endian_xchg(data);
 535                         size = (len < 4) ? len : 4;
 536                         memcpy(rxbuf, &data, size);
 537                         len -= size;
 538                         rxbuf++;
 539                         i++;
 540                 }
 541         }
 542
 543         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 544 }
 545
 546 /* If not use AHB read, read data from ip interface */
 547 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 548 {
 549         struct fsl_qspi_regs *regs = priv->regs;
 550         u32 mcr_reg, data;
 551         int i, size;
 552         u32 to_or_from;
 553         u32 seqid;
 554
 555         if (priv->cur_seqid == QSPI_CMD_RDAR)
 556                 seqid = SEQID_RDAR;
 557         else
 558                 seqid = SEQID_FAST_READ;
 559
 560         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 561         qspi_write32(priv->flags, &regs->mcr,
 562                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 563                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 564         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 565
 566         to_or_from = priv->sf_addr + priv->cur_amba_base;
 567
 568         while (len > 0) {
 569                 WATCHDOG_RESET();
 570
 571                 qspi_write32(priv->flags, &regs->sfar, to_or_from);
 572
 573                 size = (len > RX_BUFFER_SIZE) ?
 574                         RX_BUFFER_SIZE : len;
 575
 576                 qspi_write32(priv->flags, &regs->ipcr,
 577                              (seqid << QSPI_IPCR_SEQID_SHIFT) |
 578                              size);
 579                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 580                         ;
 581
 582                 to_or_from += size;
 583                 len -= size;
 584
 585                 i = 0;
 586                 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
 587                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 588                         data = qspi_endian_xchg(data);
 589                         if (size < 4)
 590                                 memcpy(rxbuf, &data, size);
 591                         else
 592                                 memcpy(rxbuf, &data, 4);
 593                         rxbuf++;
 594                         size -= 4;
 595                         i++;
 596                 }
 597                 qspi_write32(priv->flags, &regs->mcr,
 598                              qspi_read32(priv->flags, &regs->mcr) |
 599                              QSPI_MCR_CLR_RXF_MASK);
 600         }
 601
 602         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 603 }
 604
 605 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
 606 {
 607         struct fsl_qspi_regs *regs = priv->regs;
 608         u32 mcr_reg, data, reg, status_reg, seqid;
 609         int i, size, tx_size;
 610         u32 to_or_from = 0;
 611
 612         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 613         qspi_write32(priv->flags, &regs->mcr,
 614                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 615                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 616         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 617
 618         status_reg = 0;
 619         while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
 620                 WATCHDOG_RESET();
 621
 622                 qspi_write32(priv->flags, &regs->ipcr,
 623                              (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 624                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 625                         ;
 626
 627                 qspi_write32(priv->flags, &regs->ipcr,
 628                              (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
 629                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 630                         ;
 631
 632                 reg = qspi_read32(priv->flags, &regs->rbsr);
 633                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 634                         status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
 635                         status_reg = qspi_endian_xchg(status_reg);
 636                 }
 637                 qspi_write32(priv->flags, &regs->mcr,
 638                              qspi_read32(priv->flags, &regs->mcr) |
 639                              QSPI_MCR_CLR_RXF_MASK);
 640         }
 641
 642         /* Default is page programming */
 643         seqid = SEQID_PP;
 644         if (priv->cur_seqid == QSPI_CMD_WRAR)
 645                 seqid = SEQID_WRAR;
 646 #ifdef CONFIG_SPI_FLASH_BAR
 647         if (priv->cur_seqid == QSPI_CMD_BRWR)
 648                 seqid = SEQID_BRWR;
 649         else if (priv->cur_seqid == QSPI_CMD_WREAR)
 650                 seqid = SEQID_WREAR;
 651 #endif
 652
 653         to_or_from = priv->sf_addr + priv->cur_amba_base;
 654
 655         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 656
 657         tx_size = (len > TX_BUFFER_SIZE) ?
 658                 TX_BUFFER_SIZE : len;
 659
 660         size = tx_size / 4;
 661         for (i = 0; i < size; i++) {
 662                 memcpy(&data, txbuf, 4);
 663                 data = qspi_endian_xchg(data);
 664                 qspi_write32(priv->flags, &regs->tbdr, data);
 665                 txbuf += 4;
 666         }
 667
 668         size = tx_size % 4;
 669         if (size) {
 670                 data = 0;
 671                 memcpy(&data, txbuf, size);
 672                 data = qspi_endian_xchg(data);
 673                 qspi_write32(priv->flags, &regs->tbdr, data);
 674         }
 675
 676         qspi_write32(priv->flags, &regs->ipcr,
 677                      (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
 678         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 679                 ;
 680
 681         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 682 }
 683
 684 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
 685 {
 686         struct fsl_qspi_regs *regs = priv->regs;
 687         u32 mcr_reg, reg, data;
 688
 689         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 690         qspi_write32(priv->flags, &regs->mcr,
 691                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 692                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 693         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 694
 695         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 696
 697         qspi_write32(priv->flags, &regs->ipcr,
 698                      (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
 699         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 700                 ;
 701
 702         while (1) {
 703                 reg = qspi_read32(priv->flags, &regs->rbsr);
 704                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 705                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 706                         data = qspi_endian_xchg(data);
 707                         memcpy(rxbuf, &data, len);
 708                         qspi_write32(priv->flags, &regs->mcr,
 709                                      qspi_read32(priv->flags, &regs->mcr) |
 710                                      QSPI_MCR_CLR_RXF_MASK);
 711                         break;
 712                 }
 713         }
 714
 715         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 716 }
 717
 718 static void qspi_op_erase(struct fsl_qspi_priv *priv)
 719 {
 720         struct fsl_qspi_regs *regs = priv->regs;
 721         u32 mcr_reg;
 722         u32 to_or_from = 0;
 723
 724         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 725         qspi_write32(priv->flags, &regs->mcr,
 726                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 727                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 728         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 729
 730         to_or_from = priv->sf_addr + priv->cur_amba_base;
 731         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 732
 733         qspi_write32(priv->flags, &regs->ipcr,
 734                      (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 735         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 736                 ;
 737
 738         if (priv->cur_seqid == QSPI_CMD_SE) {
 739                 qspi_write32(priv->flags, &regs->ipcr,
 740                              (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
 741         } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
 742                 qspi_write32(priv->flags, &regs->ipcr,
 743                              (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
 744         }
 745         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 746                 ;
 747
 748         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 749 }
 750
 751 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
 752                 const void *dout, void *din, unsigned long flags)
 753 {
 754         u32 bytes = DIV_ROUND_UP(bitlen, 8);
 755         static u32 wr_sfaddr;
 756         u32 txbuf;
 757
 758         if (dout) {
 759                 if (flags & SPI_XFER_BEGIN) {
 760                         priv->cur_seqid = *(u8 *)dout;
 761                         memcpy(&txbuf, dout, 4);
 762                 }
 763
 764                 if (flags == SPI_XFER_END) {
 765                         priv->sf_addr = wr_sfaddr;
 766                         qspi_op_write(priv, (u8 *)dout, bytes);
 767                         return 0;
 768                 }
 769
 770                 if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
 771                     priv->cur_seqid == QSPI_CMD_RDAR) {
 772                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 773                 } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
 774                            (priv->cur_seqid == QSPI_CMD_BE_4K)) {
 775                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 776                         qspi_op_erase(priv);
 777                 } else if (priv->cur_seqid == QSPI_CMD_PP ||
 778                            priv->cur_seqid == QSPI_CMD_WRAR) {
 779                         wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
 780                 } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
 781                          (priv->cur_seqid == QSPI_CMD_WREAR)) {
 782 #ifdef CONFIG_SPI_FLASH_BAR
 783                         wr_sfaddr = 0;
 784 #endif
 785                 }
 786         }
 787
 788         if (din) {
 789                 if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
 790 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 791                         qspi_ahb_read(priv, din, bytes);
 792 #else
 793                         qspi_op_read(priv, din, bytes);
 794 #endif
 795                 } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
 796                         qspi_op_read(priv, din, bytes);
 797                 } else if (priv->cur_seqid == QSPI_CMD_RDID)
 798                         qspi_op_rdid(priv, din, bytes);
 799                 else if (priv->cur_seqid == QSPI_CMD_RDSR)
 800                         qspi_op_rdsr(priv, din, bytes);
 801 #ifdef CONFIG_SPI_FLASH_BAR
 802                 else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
 803                          (priv->cur_seqid == QSPI_CMD_RDEAR)) {
 804                         priv->sf_addr = 0;
 805                         qspi_op_rdbank(priv, din, bytes);
 806                 }
 807 #endif
 808         }
 809
 810 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 811         if ((priv->cur_seqid == QSPI_CMD_SE) ||
 812             (priv->cur_seqid == QSPI_CMD_PP) ||
 813             (priv->cur_seqid == QSPI_CMD_BE_4K) ||
 814             (priv->cur_seqid == QSPI_CMD_WREAR) ||
 815             (priv->cur_seqid == QSPI_CMD_BRWR))
 816                 qspi_ahb_invalid(priv);
 817 #endif
 818
 819         return 0;
 820 }
 821
 822 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
 823 {
 824         u32 mcr_val;
 825
 826         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
 827         if (disable)
 828                 mcr_val |= QSPI_MCR_MDIS_MASK;
 829         else
 830                 mcr_val &= ~QSPI_MCR_MDIS_MASK;
 831         qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
 832 }
 833
 834 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
 835 {
 836         u32 smpr_val;
 837
 838         smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
 839         smpr_val &= ~clear_bits;
 840         smpr_val |= set_bits;
 841         qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
 842 }
 843 #ifndef CONFIG_DM_SPI
 844 static unsigned long spi_bases[] = {
 845         QSPI0_BASE_ADDR,
 846 #ifdef CONFIG_MX6SX
 847         QSPI1_BASE_ADDR,
 848 #endif
 849 };
 850
 851 static unsigned long amba_bases[] = {
 852         QSPI0_AMBA_BASE,
 853 #ifdef CONFIG_MX6SX
 854         QSPI1_AMBA_BASE,
 855 #endif
 856 };
 857
 858 static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
 859 {
 860         return container_of(slave, struct fsl_qspi, slave);
 861 }
 862
 863 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 864                 unsigned int max_hz, unsigned int mode)
 865 {
 866         struct fsl_qspi *qspi;
 867         struct fsl_qspi_regs *regs;
 868         u32 total_size;
 869
 870         if (bus >= ARRAY_SIZE(spi_bases))
 871                 return NULL;
 872
 873         if (cs >= FSL_QSPI_FLASH_NUM)
 874                 return NULL;
 875
 876         qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
 877         if (!qspi)
 878                 return NULL;
 879
 880 #ifdef CONFIG_SYS_FSL_QSPI_BE
 881         qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
 882 #endif
 883
 884         regs = (struct fsl_qspi_regs *)spi_bases[bus];
 885         qspi->priv.regs = regs;
 886         /*
 887          * According cs, use different amba_base to choose the
 888          * corresponding flash devices.
 889          *
 890          * If not, only one flash device is used even if passing
 891          * different cs using `sf probe`
 892          */
 893         qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
 894
 895         qspi->slave.max_write_size = TX_BUFFER_SIZE;
 896
 897         qspi_write32(qspi->priv.flags, &regs->mcr,
 898                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
 899
 900         qspi_cfg_smpr(&qspi->priv,
 901                       ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
 902                       QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
 903
 904         total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
 905         /*
 906          * Any read access to non-implemented addresses will provide
 907          * undefined results.
 908          *
 909          * In case single die flash devices, TOP_ADDR_MEMA2 and
 910          * TOP_ADDR_MEMB2 should be initialized/programmed to
 911          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
 912          * setting the size of these devices to 0.  This would ensure
 913          * that the complete memory map is assigned to only one flash device.
 914          */
 915         qspi_write32(qspi->priv.flags, &regs->sfa1ad,
 916                      FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
 917         qspi_write32(qspi->priv.flags, &regs->sfa2ad,
 918                      FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
 919         qspi_write32(qspi->priv.flags, &regs->sfb1ad,
 920                      total_size | amba_bases[bus]);
 921         qspi_write32(qspi->priv.flags, &regs->sfb2ad,
 922                      total_size | amba_bases[bus]);
 923
 924         qspi_set_lut(&qspi->priv);
 925
 926 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 927         qspi_init_ahb_read(&qspi->priv);
 928 #endif
 929
 930         qspi_module_disable(&qspi->priv, 0);
 931
 932         return &qspi->slave;
 933 }
 934
 935 void spi_free_slave(struct spi_slave *slave)
 936 {
 937         struct fsl_qspi *qspi = to_qspi_spi(slave);
 938
 939         free(qspi);
 940 }
 941
 942 int spi_claim_bus(struct spi_slave *slave)
 943 {
 944         return 0;
 945 }
 946
 947 void spi_release_bus(struct spi_slave *slave)
 948 {
 949         /* Nothing to do */
 950 }
 951
 952 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 953                 const void *dout, void *din, unsigned long flags)
 954 {
 955         struct fsl_qspi *qspi = to_qspi_spi(slave);
 956
 957         return qspi_xfer(&qspi->priv, bitlen, dout, din, flags);
 958 }
 959
 960 void spi_init(void)
 961 {
 962         /* Nothing to do */
 963 }
 964 #else
 965 static int fsl_qspi_child_pre_probe(struct udevice *dev)
 966 {
 967         struct spi_slave *slave = dev_get_parent_priv(dev);
 968
 969         slave->max_write_size = TX_BUFFER_SIZE;
 970
 971         return 0;
 972 }
 973
 974 static int fsl_qspi_probe(struct udevice *bus)
 975 {
 976         u32 amba_size_per_chip;
 977         struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
 978         struct fsl_qspi_priv *priv = dev_get_priv(bus);
 979         struct dm_spi_bus *dm_spi_bus;
 980         int i;
 981
 982         dm_spi_bus = bus->uclass_priv;
 983
 984         dm_spi_bus->max_hz = plat->speed_hz;
 985
 986         priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
 987         priv->flags = plat->flags;
 988
 989         priv->speed_hz = plat->speed_hz;
 990         /*
 991          * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
 992          * AMBA memory zone should be located on the 0~4GB space
 993          * even on a 64bits cpu.
 994          */
 995         priv->amba_base[0] = (u32)plat->amba_base;
 996         priv->amba_total_size = (u32)plat->amba_total_size;
 997         priv->flash_num = plat->flash_num;
 998         priv->num_chipselect = plat->num_chipselect;
 999
1000         qspi_write32(priv->flags, &priv->regs->mcr,
1001                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
1002
1003         qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
1004                 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
1005
1006         /*
1007          * Assign AMBA memory zone for every chipselect
1008          * QuadSPI has two channels, every channel has two chipselects.
1009          * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
1010          * into two parts and assign to every channel. This indicate that every
1011          * channel only has one valid chipselect.
1012          * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
1013          * into four parts and assign to every chipselect.
1014          * Every channel will has two valid chipselects.
1015          */
1016         amba_size_per_chip = priv->amba_total_size >>
1017                              (priv->num_chipselect >> 1);
1018         for (i = 1 ; i < priv->num_chipselect ; i++)
1019                 priv->amba_base[i] =
1020                         amba_size_per_chip + priv->amba_base[i - 1];
1021
1022         /*
1023          * Any read access to non-implemented addresses will provide
1024          * undefined results.
1025          *
1026          * In case single die flash devices, TOP_ADDR_MEMA2 and
1027          * TOP_ADDR_MEMB2 should be initialized/programmed to
1028          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
1029          * setting the size of these devices to 0.  This would ensure
1030          * that the complete memory map is assigned to only one flash device.
1031          */
1032         qspi_write32(priv->flags, &priv->regs->sfa1ad, priv->amba_base[1]);
1033         switch (priv->num_chipselect) {
1034         case 2:
1035                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1036                              priv->amba_base[1]);
1037                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1038                              priv->amba_base[1] + amba_size_per_chip);
1039                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1040                              priv->amba_base[1] + amba_size_per_chip);
1041                 break;
1042         case 4:
1043                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1044                              priv->amba_base[2]);
1045                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1046                              priv->amba_base[3]);
1047                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1048                              priv->amba_base[3] + amba_size_per_chip);
1049                 break;
1050         default:
1051                 debug("Error: Unsupported chipselect number %u!\n",
1052                       priv->num_chipselect);
1053                 qspi_module_disable(priv, 1);
1054                 return -EINVAL;
1055         }
1056
1057         qspi_set_lut(priv);
1058
1059 #ifdef CONFIG_SYS_FSL_QSPI_AHB
1060         qspi_init_ahb_read(priv);
1061 #endif
1062
1063         qspi_module_disable(priv, 0);
1064
1065         return 0;
1066 }
1067
1068 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
1069 {
1070         struct fdt_resource res_regs, res_mem;
1071         struct fsl_qspi_platdata *plat = bus->platdata;
1072         const void *blob = gd->fdt_blob;
1073         int node = bus->of_offset;
1074         int ret, flash_num = 0, subnode;
1075
1076         if (fdtdec_get_bool(blob, node, "big-endian"))
1077                 plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
1078
1079         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1080                                      "QuadSPI", &res_regs);
1081         if (ret) {
1082                 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
1083                 return -ENOMEM;
1084         }
1085         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1086                                      "QuadSPI-memory", &res_mem);
1087         if (ret) {
1088                 debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
1089                 return -ENOMEM;
1090         }
1091
1092         /* Count flash numbers */
1093         fdt_for_each_subnode(blob, subnode, node)
1094                 ++flash_num;
1095
1096         if (flash_num == 0) {
1097                 debug("Error: Missing flashes!\n");
1098                 return -ENODEV;
1099         }
1100
1101         plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1102                                         FSL_QSPI_DEFAULT_SCK_FREQ);
1103         plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1104                                               FSL_QSPI_MAX_CHIPSELECT_NUM);
1105
1106         plat->reg_base = res_regs.start;
1107         plat->amba_base = res_mem.start;
1108         plat->amba_total_size = res_mem.end - res_mem.start + 1;
1109         plat->flash_num = flash_num;
1110
1111         debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
1112               __func__,
1113               (u64)plat->reg_base,
1114               (u64)plat->amba_base,
1115               (u64)plat->amba_total_size,
1116               plat->speed_hz,
1117               plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1118               );
1119
1120         return 0;
1121 }
1122
1123 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1124                 const void *dout, void *din, unsigned long flags)
1125 {
1126         struct fsl_qspi_priv *priv;
1127         struct udevice *bus;
1128
1129         bus = dev->parent;
1130         priv = dev_get_priv(bus);
1131
1132         return qspi_xfer(priv, bitlen, dout, din, flags);
1133 }
1134
1135 static int fsl_qspi_claim_bus(struct udevice *dev)
1136 {
1137         struct fsl_qspi_priv *priv;
1138         struct udevice *bus;
1139         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1140
1141         bus = dev->parent;
1142         priv = dev_get_priv(bus);
1143
1144         priv->cur_amba_base = priv->amba_base[slave_plat->cs];
1145
1146         qspi_module_disable(priv, 0);
1147
1148         return 0;
1149 }
1150
1151 static int fsl_qspi_release_bus(struct udevice *dev)
1152 {
1153         struct fsl_qspi_priv *priv;
1154         struct udevice *bus;
1155
1156         bus = dev->parent;
1157         priv = dev_get_priv(bus);
1158
1159         qspi_module_disable(priv, 1);
1160
1161         return 0;
1162 }
1163
1164 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
1165 {
1166         /* Nothing to do */
1167         return 0;
1168 }
1169
1170 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1171 {
1172         /* Nothing to do */
1173         return 0;
1174 }
1175
1176 static const struct dm_spi_ops fsl_qspi_ops = {
1177         .claim_bus      = fsl_qspi_claim_bus,
1178         .release_bus    = fsl_qspi_release_bus,
1179         .xfer           = fsl_qspi_xfer,
1180         .set_speed      = fsl_qspi_set_speed,
1181         .set_mode       = fsl_qspi_set_mode,
1182 };
1183
1184 static const struct udevice_id fsl_qspi_ids[] = {
1185         { .compatible = "fsl,vf610-qspi" },
1186         { .compatible = "fsl,imx6sx-qspi" },
1187         { }
1188 };
1189
1190 U_BOOT_DRIVER(fsl_qspi) = {
1191         .name   = "fsl_qspi",
1192         .id     = UCLASS_SPI,
1193         .of_match = fsl_qspi_ids,
1194         .ops    = &fsl_qspi_ops,
1195         .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1196         .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1197         .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
1198         .probe  = fsl_qspi_probe,
1199         .child_pre_probe = fsl_qspi_child_pre_probe,
1200 };
1201 #endif