drivers/pinctrl/rockchip/pinctrl_rk3188.c

   1 /*
   2  * Pinctrl driver for Rockchip RK3188 SoCs
   3  * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <syscon.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/grf_rk3188.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/periph.h>
  17 #include <asm/arch/pmu_rk3188.h>
  18 #include <dm/pinctrl.h>
  19 #include <dm/root.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 /* GRF_GPIO0D_IOMUX */
  24 enum {
  25         GPIO0D7_SHIFT           = 14,
  26         GPIO0D7_MASK            = 1,
  27         GPIO0D7_GPIO            = 0,
  28         GPIO0D7_SPI1_CSN0,
  29
  30         GPIO0D6_SHIFT           = 12,
  31         GPIO0D6_MASK            = 1,
  32         GPIO0D6_GPIO            = 0,
  33         GPIO0D6_SPI1_CLK,
  34
  35         GPIO0D5_SHIFT           = 10,
  36         GPIO0D5_MASK            = 1,
  37         GPIO0D5_GPIO            = 0,
  38         GPIO0D5_SPI1_TXD,
  39
  40         GPIO0D4_SHIFT           = 8,
  41         GPIO0D4_MASK            = 1,
  42         GPIO0D4_GPIO            = 0,
  43         GPIO0D4_SPI0_RXD,
  44
  45         GPIO0D3_SHIFT           = 6,
  46         GPIO0D3_MASK            = 3,
  47         GPIO0D3_GPIO            = 0,
  48         GPIO0D3_FLASH_CSN3,
  49         GPIO0D3_EMMC_RSTN_OUT,
  50
  51         GPIO0D2_SHIFT           = 4,
  52         GPIO0D2_MASK            = 3,
  53         GPIO0D2_GPIO            = 0,
  54         GPIO0D2_FLASH_CSN2,
  55         GPIO0D2_EMMC_CMD,
  56
  57         GPIO0D1_SHIFT           = 2,
  58         GPIO0D1_MASK            = 1,
  59         GPIO0D1_GPIO            = 0,
  60         GPIO0D1_FLASH_CSN1,
  61
  62         GPIO0D0_SHIFT           = 0,
  63         GPIO0D0_MASK            = 3,
  64         GPIO0D0_GPIO            = 0,
  65         GPIO0D0_FLASH_DQS,
  66         GPIO0D0_EMMC_CLKOUT
  67 };
  68
  69 /* GRF_GPIO1A_IOMUX */
  70 enum {
  71         GPIO1A7_SHIFT           = 14,
  72         GPIO1A7_MASK            = 3,
  73         GPIO1A7_GPIO            = 0,
  74         GPIO1A7_UART1_RTS_N,
  75         GPIO1A7_SPI0_CSN0,
  76
  77         GPIO1A6_SHIFT           = 12,
  78         GPIO1A6_MASK            = 3,
  79         GPIO1A6_GPIO            = 0,
  80         GPIO1A6_UART1_CTS_N,
  81         GPIO1A6_SPI0_CLK,
  82
  83         GPIO1A5_SHIFT           = 10,
  84         GPIO1A5_MASK            = 3,
  85         GPIO1A5_GPIO            = 0,
  86         GPIO1A5_UART1_SOUT,
  87         GPIO1A5_SPI0_TXD,
  88
  89         GPIO1A4_SHIFT           = 8,
  90         GPIO1A4_MASK            = 3,
  91         GPIO1A4_GPIO            = 0,
  92         GPIO1A4_UART1_SIN,
  93         GPIO1A4_SPI0_RXD,
  94
  95         GPIO1A3_SHIFT           = 6,
  96         GPIO1A3_MASK            = 1,
  97         GPIO1A3_GPIO            = 0,
  98         GPIO1A3_UART0_RTS_N,
  99
 100         GPIO1A2_SHIFT           = 4,
 101         GPIO1A2_MASK            = 1,
 102         GPIO1A2_GPIO            = 0,
 103         GPIO1A2_UART0_CTS_N,
 104
 105         GPIO1A1_SHIFT           = 2,
 106         GPIO1A1_MASK            = 1,
 107         GPIO1A1_GPIO            = 0,
 108         GPIO1A1_UART0_SOUT,
 109
 110         GPIO1A0_SHIFT           = 0,
 111         GPIO1A0_MASK            = 1,
 112         GPIO1A0_GPIO            = 0,
 113         GPIO1A0_UART0_SIN,
 114 };
 115
 116 /* GRF_GPIO1B_IOMUX */
 117 enum {
 118         GPIO1B7_SHIFT           = 14,
 119         GPIO1B7_MASK            = 1,
 120         GPIO1B7_GPIO            = 0,
 121         GPIO1B7_SPI0_CSN1,
 122
 123         GPIO1B6_SHIFT           = 12,
 124         GPIO1B6_MASK            = 3,
 125         GPIO1B6_GPIO            = 0,
 126         GPIO1B6_SPDIF_TX,
 127         GPIO1B6_SPI1_CSN1,
 128
 129         GPIO1B5_SHIFT           = 10,
 130         GPIO1B5_MASK            = 3,
 131         GPIO1B5_GPIO            = 0,
 132         GPIO1B5_UART3_RTS_N,
 133         GPIO1B5_RESERVED,
 134
 135         GPIO1B4_SHIFT           = 8,
 136         GPIO1B4_MASK            = 3,
 137         GPIO1B4_GPIO            = 0,
 138         GPIO1B4_UART3_CTS_N,
 139         GPIO1B4_GPS_RFCLK,
 140
 141         GPIO1B3_SHIFT           = 6,
 142         GPIO1B3_MASK            = 3,
 143         GPIO1B3_GPIO            = 0,
 144         GPIO1B3_UART3_SOUT,
 145         GPIO1B3_GPS_SIG,
 146
 147         GPIO1B2_SHIFT           = 4,
 148         GPIO1B2_MASK            = 3,
 149         GPIO1B2_GPIO            = 0,
 150         GPIO1B2_UART3_SIN,
 151         GPIO1B2_GPS_MAG,
 152
 153         GPIO1B1_SHIFT           = 2,
 154         GPIO1B1_MASK            = 3,
 155         GPIO1B1_GPIO            = 0,
 156         GPIO1B1_UART2_SOUT,
 157         GPIO1B1_JTAG_TDO,
 158
 159         GPIO1B0_SHIFT           = 0,
 160         GPIO1B0_MASK            = 3,
 161         GPIO1B0_GPIO            = 0,
 162         GPIO1B0_UART2_SIN,
 163         GPIO1B0_JTAG_TDI,
 164 };
 165
 166 /* GRF_GPIO1D_IOMUX */
 167 enum {
 168         GPIO1D7_SHIFT           = 14,
 169         GPIO1D7_MASK            = 1,
 170         GPIO1D7_GPIO            = 0,
 171         GPIO1D7_I2C4_SCL,
 172
 173         GPIO1D6_SHIFT           = 12,
 174         GPIO1D6_MASK            = 1,
 175         GPIO1D6_GPIO            = 0,
 176         GPIO1D6_I2C4_SDA,
 177
 178         GPIO1D5_SHIFT           = 10,
 179         GPIO1D5_MASK            = 1,
 180         GPIO1D5_GPIO            = 0,
 181         GPIO1D5_I2C2_SCL,
 182
 183         GPIO1D4_SHIFT           = 8,
 184         GPIO1D4_MASK            = 1,
 185         GPIO1D4_GPIO            = 0,
 186         GPIO1D4_I2C2_SDA,
 187
 188         GPIO1D3_SHIFT           = 6,
 189         GPIO1D3_MASK            = 1,
 190         GPIO1D3_GPIO            = 0,
 191         GPIO1D3_I2C1_SCL,
 192
 193         GPIO1D2_SHIFT           = 4,
 194         GPIO1D2_MASK            = 1,
 195         GPIO1D2_GPIO            = 0,
 196         GPIO1D2_I2C1_SDA,
 197
 198         GPIO1D1_SHIFT           = 2,
 199         GPIO1D1_MASK            = 1,
 200         GPIO1D1_GPIO            = 0,
 201         GPIO1D1_I2C0_SCL,
 202
 203         GPIO1D0_SHIFT           = 0,
 204         GPIO1D0_MASK            = 1,
 205         GPIO1D0_GPIO            = 0,
 206         GPIO1D0_I2C0_SDA,
 207 };
 208
 209 /* GRF_GPIO3A_IOMUX */
 210 enum {
 211         GPIO3A7_SHIFT           = 14,
 212         GPIO3A7_MASK            = 1,
 213         GPIO3A7_GPIO            = 0,
 214         GPIO3A7_SDMMC0_DATA3,
 215
 216         GPIO3A6_SHIFT           = 12,
 217         GPIO3A6_MASK            = 1,
 218         GPIO3A6_GPIO            = 0,
 219         GPIO3A6_SDMMC0_DATA2,
 220
 221         GPIO3A5_SHIFT           = 10,
 222         GPIO3A5_MASK            = 1,
 223         GPIO3A5_GPIO            = 0,
 224         GPIO3A5_SDMMC0_DATA1,
 225
 226         GPIO3A4_SHIFT           = 8,
 227         GPIO3A4_MASK            = 1,
 228         GPIO3A4_GPIO            = 0,
 229         GPIO3A4_SDMMC0_DATA0,
 230
 231         GPIO3A3_SHIFT           = 6,
 232         GPIO3A3_MASK            = 1,
 233         GPIO3A3_GPIO            = 0,
 234         GPIO3A3_SDMMC0_CMD,
 235
 236         GPIO3A2_SHIFT           = 4,
 237         GPIO3A2_MASK            = 1,
 238         GPIO3A2_GPIO            = 0,
 239         GPIO3A2_SDMMC0_CLKOUT,
 240
 241         GPIO3A1_SHIFT           = 2,
 242         GPIO3A1_MASK            = 1,
 243         GPIO3A1_GPIO            = 0,
 244         GPIO3A1_SDMMC0_PWREN,
 245
 246         GPIO3A0_SHIFT           = 0,
 247         GPIO3A0_MASK            = 1,
 248         GPIO3A0_GPIO            = 0,
 249         GPIO3A0_SDMMC0_RSTN,
 250 };
 251
 252 /* GRF_GPIO3B_IOMUX */
 253 enum {
 254         GPIO3B7_SHIFT           = 14,
 255         GPIO3B7_MASK            = 3,
 256         GPIO3B7_GPIO            = 0,
 257         GPIO3B7_CIF_DATA11,
 258         GPIO3B7_I2C3_SCL,
 259
 260         GPIO3B6_SHIFT           = 12,
 261         GPIO3B6_MASK            = 3,
 262         GPIO3B6_GPIO            = 0,
 263         GPIO3B6_CIF_DATA10,
 264         GPIO3B6_I2C3_SDA,
 265
 266         GPIO3B5_SHIFT           = 10,
 267         GPIO3B5_MASK            = 3,
 268         GPIO3B5_GPIO            = 0,
 269         GPIO3B5_CIF_DATA1,
 270         GPIO3B5_HSADC_DATA9,
 271
 272         GPIO3B4_SHIFT           = 8,
 273         GPIO3B4_MASK            = 3,
 274         GPIO3B4_GPIO            = 0,
 275         GPIO3B4_CIF_DATA0,
 276         GPIO3B4_HSADC_DATA8,
 277
 278         GPIO3B3_SHIFT           = 6,
 279         GPIO3B3_MASK            = 1,
 280         GPIO3B3_GPIO            = 0,
 281         GPIO3B3_CIF_CLKOUT,
 282
 283         GPIO3B2_SHIFT           = 4,
 284         GPIO3B2_MASK            = 1,
 285         GPIO3B2_GPIO            = 0,
 286         /* no muxes */
 287
 288         GPIO3B1_SHIFT           = 2,
 289         GPIO3B1_MASK            = 1,
 290         GPIO3B1_GPIO            = 0,
 291         GPIO3B1_SDMMC0_WRITE_PRT,
 292
 293         GPIO3B0_SHIFT           = 0,
 294         GPIO3B0_MASK            = 1,
 295         GPIO3B0_GPIO            = 0,
 296         GPIO3B0_SDMMC_DETECT_N,
 297 };
 298
 299 /* GRF_GPIO3C_IOMUX */
 300 enum {
 301         GPIO3C7_SHIFT           = 14,
 302         GPIO3C7_MASK            = 3,
 303         GPIO3C7_GPIO            = 0,
 304         GPIO3C7_SDMMC1_WRITE_PRT,
 305         GPIO3C7_RMII_CRS_DVALID,
 306         GPIO3C7_RESERVED,
 307
 308         GPIO3C6_SHIFT           = 12,
 309         GPIO3C6_MASK            = 3,
 310         GPIO3C6_GPIO            = 0,
 311         GPIO3C6_SDMMC1_DECTN,
 312         GPIO3C6_RMII_RX_ERR,
 313         GPIO3C6_RESERVED,
 314
 315         GPIO3C5_SHIFT           = 10,
 316         GPIO3C5_MASK            = 3,
 317         GPIO3C5_GPIO            = 0,
 318         GPIO3C5_SDMMC1_CLKOUT,
 319         GPIO3C5_RMII_CLKOUT,
 320         GPIO3C5_RMII_CLKIN,
 321
 322         GPIO3C4_SHIFT           = 8,
 323         GPIO3C4_MASK            = 3,
 324         GPIO3C4_GPIO            = 0,
 325         GPIO3C4_SDMMC1_DATA3,
 326         GPIO3C4_RMII_RXD1,
 327         GPIO3C4_RESERVED,
 328
 329         GPIO3C3_SHIFT           = 6,
 330         GPIO3C3_MASK            = 3,
 331         GPIO3C3_GPIO            = 0,
 332         GPIO3C3_SDMMC1_DATA2,
 333         GPIO3C3_RMII_RXD0,
 334         GPIO3C3_RESERVED,
 335
 336         GPIO3C2_SHIFT           = 4,
 337         GPIO3C2_MASK            = 3,
 338         GPIO3C2_GPIO            = 0,
 339         GPIO3C2_SDMMC1_DATA1,
 340         GPIO3C2_RMII_TXD0,
 341         GPIO3C2_RESERVED,
 342
 343         GPIO3C1_SHIFT           = 2,
 344         GPIO3C1_MASK            = 3,
 345         GPIO3C1_GPIO            = 0,
 346         GPIO3C1_SDMMC1_DATA0,
 347         GPIO3C1_RMII_TXD1,
 348         GPIO3C1_RESERVED,
 349
 350         GPIO3C0_SHIFT           = 0,
 351         GPIO3C0_MASK            = 3,
 352         GPIO3C0_GPIO            = 0,
 353         GPIO3C0_SDMMC1_CMD,
 354         GPIO3C0_RMII_TX_EN,
 355         GPIO3C0_RESERVED,
 356 };
 357
 358 /* GRF_GPIO3D_IOMUX */
 359 enum {
 360         GPIO3D6_SHIFT           = 12,
 361         GPIO3D6_MASK            = 3,
 362         GPIO3D6_GPIO            = 0,
 363         GPIO3D6_PWM_3,
 364         GPIO3D6_JTAG_TMS,
 365         GPIO3D6_HOST_DRV_VBUS,
 366
 367         GPIO3D5_SHIFT           = 10,
 368         GPIO3D5_MASK            = 3,
 369         GPIO3D5_GPIO            = 0,
 370         GPIO3D5_PWM_2,
 371         GPIO3D5_JTAG_TCK,
 372         GPIO3D5_OTG_DRV_VBUS,
 373
 374         GPIO3D4_SHIFT           = 8,
 375         GPIO3D4_MASK            = 3,
 376         GPIO3D4_GPIO            = 0,
 377         GPIO3D4_PWM_1,
 378         GPIO3D4_JTAG_TRSTN,
 379
 380         GPIO3D3_SHIFT           = 6,
 381         GPIO3D3_MASK            = 3,
 382         GPIO3D3_GPIO            = 0,
 383         GPIO3D3_PWM_0,
 384
 385         GPIO3D2_SHIFT           = 4,
 386         GPIO3D2_MASK            = 3,
 387         GPIO3D2_GPIO            = 0,
 388         GPIO3D2_SDMMC1_INT_N,
 389
 390         GPIO3D1_SHIFT           = 2,
 391         GPIO3D1_MASK            = 3,
 392         GPIO3D1_GPIO            = 0,
 393         GPIO3D1_SDMMC1_BACKEND_PWR,
 394         GPIO3D1_MII_MDCLK,
 395
 396         GPIO3D0_SHIFT           = 0,
 397         GPIO3D0_MASK            = 3,
 398         GPIO3D0_GPIO            = 0,
 399         GPIO3D0_SDMMC1_PWR_EN,
 400         GPIO3D0_MII_MD,
 401 };
 402
 403 struct rk3188_pinctrl_priv {
 404         struct rk3188_grf *grf;
 405         struct rk3188_pmu *pmu;
 406         int num_banks;
 407 };
 408
 409 /**
 410  * Encode variants of iomux registers into a type variable
 411  */
 412 #define IOMUX_GPIO_ONLY         BIT(0)
 413
 414 /**
 415  * @type: iomux variant using IOMUX_* constants
 416  * @offset: if initialized to -1 it will be autocalculated, by specifying
 417  *          an initial offset value the relevant source offset can be reset
 418  *          to a new value for autocalculating the following iomux registers.
 419  */
 420 struct rockchip_iomux {
 421         u8 type;
 422         s16 offset;
 423 };
 424
 425 /**
 426  * @reg: register offset of the gpio bank
 427  * @nr_pins: number of pins in this bank
 428  * @bank_num: number of the bank, to account for holes
 429  * @name: name of the bank
 430  * @iomux: array describing the 4 iomux sources of the bank
 431  */
 432 struct rockchip_pin_bank {
 433         u16 reg;
 434         u8 nr_pins;
 435         u8 bank_num;
 436         char *name;
 437         struct rockchip_iomux iomux[4];
 438 };
 439
 440 #define PIN_BANK(id, pins, label)                       \
 441         {                                               \
 442                 .bank_num       = id,                   \
 443                 .nr_pins        = pins,                 \
 444                 .name           = label,                \
 445                 .iomux          = {                     \
 446                         { .offset = -1 },               \
 447                         { .offset = -1 },               \
 448                         { .offset = -1 },               \
 449                         { .offset = -1 },               \
 450                 },                                      \
 451         }
 452
 453 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 454         {                                                               \
 455                 .bank_num       = id,                                   \
 456                 .nr_pins        = pins,                                 \
 457                 .name           = label,                                \
 458                 .iomux          = {                                     \
 459                         { .type = iom0, .offset = -1 },                 \
 460                         { .type = iom1, .offset = -1 },                 \
 461                         { .type = iom2, .offset = -1 },                 \
 462                         { .type = iom3, .offset = -1 },                 \
 463                 },                                                      \
 464         }
 465
 466 #ifndef CONFIG_SPL_BUILD
 467 static struct rockchip_pin_bank rk3188_pin_banks[] = {
 468         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
 469         PIN_BANK(1, 32, "gpio1"),
 470         PIN_BANK(2, 32, "gpio2"),
 471         PIN_BANK(3, 32, "gpio3"),
 472 };
 473 #endif
 474
 475 static void pinctrl_rk3188_pwm_config(struct rk3188_grf *grf, int pwm_id)
 476 {
 477         switch (pwm_id) {
 478         case PERIPH_ID_PWM0:
 479                 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D3_MASK << GPIO3D3_SHIFT,
 480                              GPIO3D3_PWM_0 << GPIO3D3_SHIFT);
 481                 break;
 482         case PERIPH_ID_PWM1:
 483                 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D4_MASK << GPIO3D4_SHIFT,
 484                              GPIO3D4_PWM_1 << GPIO3D4_SHIFT);
 485                 break;
 486         case PERIPH_ID_PWM2:
 487                 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D5_MASK << GPIO3D5_SHIFT,
 488                              GPIO3D5_PWM_2 << GPIO3D5_SHIFT);
 489                 break;
 490         case PERIPH_ID_PWM3:
 491                 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D6_MASK << GPIO3D6_SHIFT,
 492                              GPIO3D6_PWM_3 << GPIO3D6_SHIFT);
 493                 break;
 494         default:
 495                 debug("pwm id = %d iomux error!\n", pwm_id);
 496                 break;
 497         }
 498 }
 499
 500 static void pinctrl_rk3188_i2c_config(struct rk3188_grf *grf,
 501                                       struct rk3188_pmu *pmu, int i2c_id)
 502 {
 503         switch (i2c_id) {
 504         case PERIPH_ID_I2C0:
 505                 rk_clrsetreg(&grf->gpio1d_iomux,
 506                                 GPIO1D1_MASK << GPIO1D1_SHIFT |
 507                                 GPIO1D0_MASK << GPIO1D0_SHIFT,
 508                                 GPIO1D1_I2C0_SCL << GPIO1D1_SHIFT |
 509                                 GPIO1D0_I2C0_SDA << GPIO1D0_SHIFT);
 510                 /* enable new i2c controller */
 511                 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT,
 512                                              1 << RKI2C0_SEL_SHIFT);
 513                 break;
 514         case PERIPH_ID_I2C1:
 515                 rk_clrsetreg(&grf->gpio1d_iomux,
 516                                 GPIO1D3_MASK << GPIO1D3_SHIFT |
 517                                 GPIO1D2_MASK << GPIO1D2_SHIFT,
 518                                 GPIO1D3_I2C1_SCL << GPIO1D2_SHIFT |
 519                                 GPIO1D2_I2C1_SDA << GPIO1D2_SHIFT);
 520                 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C1_SEL_SHIFT,
 521                                              1 << RKI2C1_SEL_SHIFT);
 522                 break;
 523         case PERIPH_ID_I2C2:
 524                 rk_clrsetreg(&grf->gpio1d_iomux,
 525                                 GPIO1D5_MASK << GPIO1D5_SHIFT |
 526                                 GPIO1D4_MASK << GPIO1D4_SHIFT,
 527                                 GPIO1D5_I2C2_SCL << GPIO1D5_SHIFT |
 528                                 GPIO1D4_I2C2_SDA << GPIO1D4_SHIFT);
 529                 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C2_SEL_SHIFT,
 530                                              1 << RKI2C2_SEL_SHIFT);
 531                 break;
 532         case PERIPH_ID_I2C3:
 533                 rk_clrsetreg(&grf->gpio3b_iomux,
 534                                 GPIO3B7_MASK << GPIO3B7_SHIFT |
 535                                 GPIO3B6_MASK << GPIO3B6_SHIFT,
 536                                 GPIO3B7_I2C3_SCL << GPIO3B7_SHIFT |
 537                                 GPIO3B6_I2C3_SDA << GPIO3B6_SHIFT);
 538                 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C3_SEL_SHIFT,
 539                                              1 << RKI2C3_SEL_SHIFT);
 540                 break;
 541         case PERIPH_ID_I2C4:
 542                 rk_clrsetreg(&grf->gpio1d_iomux,
 543                                 GPIO1D7_MASK << GPIO1D7_SHIFT |
 544                                 GPIO1D6_MASK << GPIO1D6_SHIFT,
 545                                 GPIO1D7_I2C4_SCL << GPIO1D7_SHIFT |
 546                                 GPIO1D6_I2C4_SDA << GPIO1D6_SHIFT);
 547                 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C4_SEL_SHIFT,
 548                                              1 << RKI2C4_SEL_SHIFT);
 549                 break;
 550         default:
 551                 debug("i2c id = %d iomux error!\n", i2c_id);
 552                 break;
 553         }
 554 }
 555
 556 static int pinctrl_rk3188_spi_config(struct rk3188_grf *grf,
 557                                      enum periph_id spi_id, int cs)
 558 {
 559         switch (spi_id) {
 560         case PERIPH_ID_SPI0:
 561                 switch (cs) {
 562                 case 0:
 563                         rk_clrsetreg(&grf->gpio1a_iomux,
 564                                      GPIO1A7_MASK << GPIO1A7_SHIFT,
 565                                      GPIO1A7_SPI0_CSN0 << GPIO1A7_SHIFT);
 566                         break;
 567                 case 1:
 568                         rk_clrsetreg(&grf->gpio1b_iomux,
 569                                      GPIO1B7_MASK << GPIO1B7_SHIFT,
 570                                      GPIO1B7_SPI0_CSN1 << GPIO1B7_SHIFT);
 571                         break;
 572                 default:
 573                         goto err;
 574                 }
 575                 rk_clrsetreg(&grf->gpio1a_iomux,
 576                              GPIO1A4_MASK << GPIO1A4_SHIFT |
 577                              GPIO1A5_MASK << GPIO1A5_SHIFT |
 578                              GPIO1A6_MASK << GPIO1A6_SHIFT,
 579                              GPIO1A4_SPI0_RXD << GPIO1A4_SHIFT |
 580                              GPIO1A5_SPI0_TXD << GPIO1A5_SHIFT |
 581                              GPIO1A6_SPI0_CLK << GPIO1A6_SHIFT);
 582                 break;
 583         case PERIPH_ID_SPI1:
 584                 switch (cs) {
 585                 case 0:
 586                         rk_clrsetreg(&grf->gpio0d_iomux,
 587                                      GPIO0D7_MASK << GPIO0D7_SHIFT,
 588                                      GPIO0D7_SPI1_CSN0 << GPIO0D7_SHIFT);
 589                         break;
 590                 case 1:
 591                         rk_clrsetreg(&grf->gpio1b_iomux,
 592                                      GPIO1B6_MASK << GPIO1B6_SHIFT,
 593                                      GPIO1B6_SPI1_CSN1 << GPIO1B6_SHIFT);
 594                         break;
 595                 default:
 596                         goto err;
 597                 }
 598                 rk_clrsetreg(&grf->gpio0d_iomux,
 599                              GPIO0D4_MASK << GPIO0D4_SHIFT |
 600                              GPIO0D5_MASK << GPIO0D5_SHIFT |
 601                              GPIO0D6_MASK << GPIO0D6_SHIFT,
 602                              GPIO0D4_SPI0_RXD << GPIO0D4_SHIFT |
 603                              GPIO0D5_SPI1_TXD << GPIO0D5_SHIFT |
 604                              GPIO0D6_SPI1_CLK << GPIO0D6_SHIFT);
 605                 break;
 606         default:
 607                 goto err;
 608         }
 609
 610         return 0;
 611 err:
 612         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 613         return -ENOENT;
 614 }
 615
 616 static void pinctrl_rk3188_uart_config(struct rk3188_grf *grf, int uart_id)
 617 {
 618         switch (uart_id) {
 619         case PERIPH_ID_UART0:
 620                 rk_clrsetreg(&grf->gpio1a_iomux,
 621                              GPIO1A3_MASK << GPIO1A3_SHIFT |
 622                              GPIO1A2_MASK << GPIO1A2_SHIFT |
 623                              GPIO1A1_MASK << GPIO1A1_SHIFT |
 624                              GPIO1A0_MASK << GPIO1A0_SHIFT,
 625                              GPIO1A3_UART0_RTS_N << GPIO1A3_SHIFT |
 626                              GPIO1A2_UART0_CTS_N << GPIO1A2_SHIFT |
 627                              GPIO1A1_UART0_SOUT << GPIO1A1_SHIFT |
 628                              GPIO1A0_UART0_SIN << GPIO1A0_SHIFT);
 629                 break;
 630         case PERIPH_ID_UART1:
 631                 rk_clrsetreg(&grf->gpio1a_iomux,
 632                              GPIO1A7_MASK << GPIO1A7_SHIFT |
 633                              GPIO1A6_MASK << GPIO1A6_SHIFT |
 634                              GPIO1A5_MASK << GPIO1A5_SHIFT |
 635                              GPIO1A4_MASK << GPIO1A4_SHIFT,
 636                              GPIO1A7_UART1_RTS_N << GPIO1A7_SHIFT |
 637                              GPIO1A6_UART1_CTS_N << GPIO1A6_SHIFT |
 638                              GPIO1A5_UART1_SOUT << GPIO1A5_SHIFT |
 639                              GPIO1A4_UART1_SIN << GPIO1A4_SHIFT);
 640                 break;
 641         case PERIPH_ID_UART2:
 642                 rk_clrsetreg(&grf->gpio1b_iomux,
 643                              GPIO1B1_MASK << GPIO1B1_SHIFT |
 644                              GPIO1B0_MASK << GPIO1B0_SHIFT,
 645                              GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
 646                              GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
 647                 break;
 648         case PERIPH_ID_UART3:
 649                 rk_clrsetreg(&grf->gpio1b_iomux,
 650                              GPIO1B5_MASK << GPIO1B5_SHIFT |
 651                              GPIO1B4_MASK << GPIO1B4_SHIFT |
 652                              GPIO1B3_MASK << GPIO1B3_SHIFT |
 653                              GPIO1B2_MASK << GPIO1B2_SHIFT,
 654                              GPIO1B5_UART3_RTS_N << GPIO1B5_SHIFT |
 655                              GPIO1B4_UART3_CTS_N << GPIO1B4_SHIFT |
 656                              GPIO1B3_UART3_SOUT << GPIO1B3_SHIFT |
 657                              GPIO1B2_UART3_SIN << GPIO1B2_SHIFT);
 658                 break;
 659         default:
 660                 debug("uart id = %d iomux error!\n", uart_id);
 661                 break;
 662         }
 663 }
 664
 665 static void pinctrl_rk3188_sdmmc_config(struct rk3188_grf *grf, int mmc_id)
 666 {
 667         switch (mmc_id) {
 668         case PERIPH_ID_EMMC:
 669                 rk_clrsetreg(&grf->soc_con0, 1 << EMMC_FLASH_SEL_SHIFT,
 670                                              1 << EMMC_FLASH_SEL_SHIFT);
 671                 rk_clrsetreg(&grf->gpio0d_iomux,
 672                              GPIO0D2_MASK << GPIO0D2_SHIFT |
 673                              GPIO0D0_MASK << GPIO0D0_SHIFT,
 674                              GPIO0D2_EMMC_CMD << GPIO0D2_SHIFT |
 675                              GPIO0D0_EMMC_CLKOUT << GPIO0D0_SHIFT);
 676                 break;
 677         case PERIPH_ID_SDCARD:
 678                 rk_clrsetreg(&grf->gpio3b_iomux,
 679                              GPIO3B0_MASK << GPIO3B0_SHIFT,
 680                              GPIO3B0_SDMMC_DETECT_N << GPIO3B0_SHIFT);
 681                 rk_clrsetreg(&grf->gpio3a_iomux,
 682                              GPIO3A7_MASK << GPIO3A7_SHIFT |
 683                              GPIO3A6_MASK << GPIO3A6_SHIFT |
 684                              GPIO3A5_MASK << GPIO3A5_SHIFT |
 685                              GPIO3A4_MASK << GPIO3A4_SHIFT |
 686                              GPIO3A3_MASK << GPIO3A3_SHIFT |
 687                              GPIO3A3_MASK << GPIO3A2_SHIFT,
 688                              GPIO3A7_SDMMC0_DATA3 << GPIO3A7_SHIFT |
 689                              GPIO3A6_SDMMC0_DATA2 << GPIO3A6_SHIFT |
 690                              GPIO3A5_SDMMC0_DATA1 << GPIO3A5_SHIFT |
 691                              GPIO3A4_SDMMC0_DATA0 << GPIO3A4_SHIFT |
 692                              GPIO3A3_SDMMC0_CMD << GPIO3A3_SHIFT |
 693                              GPIO3A2_SDMMC0_CLKOUT << GPIO3A2_SHIFT);
 694                 break;
 695         default:
 696                 debug("mmc id = %d iomux error!\n", mmc_id);
 697                 break;
 698         }
 699 }
 700
 701 static int rk3188_pinctrl_request(struct udevice *dev, int func, int flags)
 702 {
 703         struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
 704
 705         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 706         switch (func) {
 707         case PERIPH_ID_PWM0:
 708         case PERIPH_ID_PWM1:
 709         case PERIPH_ID_PWM2:
 710         case PERIPH_ID_PWM3:
 711         case PERIPH_ID_PWM4:
 712                 pinctrl_rk3188_pwm_config(priv->grf, func);
 713                 break;
 714         case PERIPH_ID_I2C0:
 715         case PERIPH_ID_I2C1:
 716         case PERIPH_ID_I2C2:
 717         case PERIPH_ID_I2C3:
 718         case PERIPH_ID_I2C4:
 719         case PERIPH_ID_I2C5:
 720                 pinctrl_rk3188_i2c_config(priv->grf, priv->pmu, func);
 721                 break;
 722         case PERIPH_ID_SPI0:
 723         case PERIPH_ID_SPI1:
 724         case PERIPH_ID_SPI2:
 725                 pinctrl_rk3188_spi_config(priv->grf, func, flags);
 726                 break;
 727         case PERIPH_ID_UART0:
 728         case PERIPH_ID_UART1:
 729         case PERIPH_ID_UART2:
 730         case PERIPH_ID_UART3:
 731         case PERIPH_ID_UART4:
 732                 pinctrl_rk3188_uart_config(priv->grf, func);
 733                 break;
 734                 break;
 735         case PERIPH_ID_SDMMC0:
 736         case PERIPH_ID_SDMMC1:
 737                 pinctrl_rk3188_sdmmc_config(priv->grf, func);
 738                 break;
 739         default:
 740                 return -EINVAL;
 741         }
 742
 743         return 0;
 744 }
 745
 746 static int rk3188_pinctrl_get_periph_id(struct udevice *dev,
 747                                         struct udevice *periph)
 748 {
 749 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 750         u32 cell[3];
 751         int ret;
 752
 753         ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
 754         if (ret < 0)
 755                 return -EINVAL;
 756
 757         switch (cell[1]) {
 758         case 44:
 759                 return PERIPH_ID_SPI0;
 760         case 45:
 761                 return PERIPH_ID_SPI1;
 762         case 46:
 763                 return PERIPH_ID_SPI2;
 764         case 60:
 765                 return PERIPH_ID_I2C0;
 766         case 62: /* Note strange order */
 767                 return PERIPH_ID_I2C1;
 768         case 61:
 769                 return PERIPH_ID_I2C2;
 770         case 63:
 771                 return PERIPH_ID_I2C3;
 772         case 64:
 773                 return PERIPH_ID_I2C4;
 774         case 65:
 775                 return PERIPH_ID_I2C5;
 776         }
 777 #endif
 778
 779         return -ENOENT;
 780 }
 781
 782 static int rk3188_pinctrl_set_state_simple(struct udevice *dev,
 783                                            struct udevice *periph)
 784 {
 785         int func;
 786
 787         func = rk3188_pinctrl_get_periph_id(dev, periph);
 788         if (func < 0)
 789                 return func;
 790         return rk3188_pinctrl_request(dev, func, 0);
 791 }
 792
 793 #ifndef CONFIG_SPL_BUILD
 794 int rk3188_pinctrl_get_pin_info(struct rk3188_pinctrl_priv *priv,
 795                                 int banknum, int ind, u32 **addrp, uint *shiftp,
 796                                 uint *maskp)
 797 {
 798         struct rockchip_pin_bank *bank = &rk3188_pin_banks[banknum];
 799         uint muxnum;
 800         u32 *addr;
 801
 802         for (muxnum = 0; muxnum < 4; muxnum++) {
 803                 struct rockchip_iomux *mux = &bank->iomux[muxnum];
 804
 805                 if (ind >= 8) {
 806                         ind -= 8;
 807                         continue;
 808                 }
 809
 810                 addr = &priv->grf->gpio0c_iomux - 2;
 811                 addr += mux->offset;
 812                 *shiftp = ind & 7;
 813                 *maskp = 3;
 814                 *shiftp *= 2;
 815
 816                 debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
 817                       *maskp, *shiftp);
 818                 *addrp = addr;
 819                 return 0;
 820         }
 821
 822         return -EINVAL;
 823 }
 824
 825 static int rk3188_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
 826                                        int index)
 827 {
 828         struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
 829         uint shift;
 830         uint mask;
 831         u32 *addr;
 832         int ret;
 833
 834         ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
 835                                           &mask);
 836         if (ret)
 837                 return ret;
 838         return (readl(addr) & mask) >> shift;
 839 }
 840
 841 static int rk3188_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
 842                                    int muxval, int flags)
 843 {
 844         struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
 845         uint shift, ind = index;
 846         uint mask;
 847         u32 *addr;
 848         int ret;
 849
 850         debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
 851         ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
 852                                           &mask);
 853         if (ret)
 854                 return ret;
 855         rk_clrsetreg(addr, mask << shift, muxval << shift);
 856
 857         /* Handle pullup/pulldown */
 858         if (flags) {
 859                 uint val = 0;
 860
 861                 if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
 862                         val = 1;
 863                 else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
 864                         val = 2;
 865
 866                 ind = index >> 3;
 867
 868                 if (banknum == 0 && index < 12) {
 869                         addr = &priv->pmu->gpio0_p[ind];
 870                         shift = (index & 7) * 2;
 871                 } else if (banknum == 0 && index >= 12) {
 872                         addr = &priv->grf->gpio0_p[ind - 1];
 873                         /*
 874                          * The bits in the grf-registers have an inverse
 875                          * ordering with the lowest pin being in bits 15:14
 876                          * and the highest pin in bits 1:0 .
 877                          */
 878                         shift = (7 - (index & 7)) * 2;
 879                 } else {
 880                         addr = &priv->grf->gpio1_p[banknum - 1][ind];
 881                         shift = (7 - (index & 7)) * 2;
 882                 }
 883                 debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
 884                       shift);
 885                 rk_clrsetreg(addr, 3 << shift, val << shift);
 886         }
 887
 888         return 0;
 889 }
 890
 891 static int rk3188_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 892 {
 893         const void *blob = gd->fdt_blob;
 894         int pcfg_node, ret, flags, count, i;
 895         u32 cell[60], *ptr;
 896
 897         debug("%s: %s %s\n", __func__, dev->name, config->name);
 898         ret = fdtdec_get_int_array_count(blob, dev_of_offset(config),
 899                                          "rockchip,pins", cell,
 900                                          ARRAY_SIZE(cell));
 901         if (ret < 0) {
 902                 debug("%s: bad array %d\n", __func__, ret);
 903                 return -EINVAL;
 904         }
 905         count = ret;
 906         for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
 907                 pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
 908                 if (pcfg_node < 0)
 909                         return -EINVAL;
 910                 flags = pinctrl_decode_pin_config(blob, pcfg_node);
 911                 if (flags < 0)
 912                         return flags;
 913
 914                 ret = rk3188_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
 915                                               flags);
 916                 if (ret)
 917                         return ret;
 918         }
 919
 920         return 0;
 921 }
 922 #endif
 923
 924 static struct pinctrl_ops rk3188_pinctrl_ops = {
 925 #ifndef CONFIG_SPL_BUILD
 926         .set_state      = rk3188_pinctrl_set_state,
 927         .get_gpio_mux   = rk3188_pinctrl_get_gpio_mux,
 928 #endif
 929         .set_state_simple       = rk3188_pinctrl_set_state_simple,
 930         .request        = rk3188_pinctrl_request,
 931         .get_periph_id  = rk3188_pinctrl_get_periph_id,
 932 };
 933
 934 #ifndef CONFIG_SPL_BUILD
 935 static int rk3188_pinctrl_parse_tables(struct rk3188_pinctrl_priv *priv,
 936                                        struct rockchip_pin_bank *banks,
 937                                        int count)
 938 {
 939         struct rockchip_pin_bank *bank;
 940         uint reg, muxnum, banknum;
 941
 942         reg = 0;
 943         for (banknum = 0; banknum < count; banknum++) {
 944                 bank = &banks[banknum];
 945                 bank->reg = reg;
 946                 debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
 947                 for (muxnum = 0; muxnum < 4; muxnum++) {
 948                         struct rockchip_iomux *mux = &bank->iomux[muxnum];
 949
 950                         mux->offset = reg;
 951                         reg += 1;
 952                 }
 953         }
 954
 955         return 0;
 956 }
 957 #endif
 958
 959 static int rk3188_pinctrl_probe(struct udevice *dev)
 960 {
 961         struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
 962         int ret = 0;
 963
 964         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 965         priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 966         debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
 967 #ifndef CONFIG_SPL_BUILD
 968         ret = rk3188_pinctrl_parse_tables(priv, rk3188_pin_banks,
 969                                           ARRAY_SIZE(rk3188_pin_banks));
 970 #endif
 971
 972         return ret;
 973 }
 974
 975 static const struct udevice_id rk3188_pinctrl_ids[] = {
 976         { .compatible = "rockchip,rk3188-pinctrl" },
 977         { }
 978 };
 979
 980 U_BOOT_DRIVER(pinctrl_rk3188) = {
 981         .name           = "rockchip_rk3188_pinctrl",
 982         .id             = UCLASS_PINCTRL,
 983         .of_match       = rk3188_pinctrl_ids,
 984         .priv_auto_alloc_size = sizeof(struct rk3188_pinctrl_priv),
 985         .ops            = &rk3188_pinctrl_ops,
 986 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 987         .bind           = dm_scan_fdt_dev,
 988 #endif
 989         .probe          = rk3188_pinctrl_probe,
 990 };