drivers/net/ldpaa_eth/ls1088a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  */
   5 #include <common.h>
   6 #include <phy.h>
   7 #include <fsl-mc/ldpaa_wriop.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/fsl_serdes.h>
  10 #include <asm/arch/soc.h>
  11
  12 u32 dpmac_to_devdisr[] = {
  13         [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
  14         [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
  15         [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
  16         [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
  17         [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
  18         [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
  19         [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
  20         [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
  21         [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
  22         [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
  23 };
  24
  25 static int is_device_disabled(int dpmac_id)
  26 {
  27         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  28         u32 devdisr2 = in_le32(&gur->devdisr2);
  29
  30         return dpmac_to_devdisr[dpmac_id] & devdisr2;
  31 }
  32
  33 void wriop_dpmac_disable(int dpmac_id)
  34 {
  35         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  36
  37         setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
  38 }
  39
  40 void wriop_dpmac_enable(int dpmac_id)
  41 {
  42         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  43
  44         clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
  45 }
  46
  47 phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
  48 {
  49         enum srds_prtcl;
  50
  51         if (is_device_disabled(dpmac_id + 1))
  52                 return PHY_INTERFACE_MODE_NONE;
  53
  54         switch (lane_prtcl) {
  55         case SGMII1:
  56         case SGMII2:
  57         case SGMII3:
  58         case SGMII7:
  59                 return PHY_INTERFACE_MODE_SGMII;
  60         }
  61
  62         if (lane_prtcl >= XFI1 && lane_prtcl <= XFI2)
  63                 return PHY_INTERFACE_MODE_XGMII;
  64
  65         if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_B)
  66                 return PHY_INTERFACE_MODE_QSGMII;
  67
  68         return PHY_INTERFACE_MODE_NONE;
  69 }
  70
  71 void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
  72 {
  73         switch (lane_prtcl) {
  74         case QSGMII_A:
  75                 wriop_init_dpmac(sd, 3, (int)lane_prtcl);
  76                 wriop_init_dpmac(sd, 4, (int)lane_prtcl);
  77                 wriop_init_dpmac(sd, 5, (int)lane_prtcl);
  78                 wriop_init_dpmac(sd, 6, (int)lane_prtcl);
  79                 break;
  80         case QSGMII_B:
  81                 wriop_init_dpmac(sd, 7, (int)lane_prtcl);
  82                 wriop_init_dpmac(sd, 8, (int)lane_prtcl);
  83                 wriop_init_dpmac(sd, 9, (int)lane_prtcl);
  84                 wriop_init_dpmac(sd, 10, (int)lane_prtcl);
  85                 break;
  86         }
  87 }
  88
  89 #ifdef CONFIG_SYS_FSL_HAS_RGMII
  90 void fsl_rgmii_init(void)
  91 {
  92         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  93         u32 ec;
  94
  95 #ifdef CONFIG_SYS_FSL_EC1
  96         ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])
  97                 & FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK;
  98         ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
  99
 100         if (!ec)
 101                 wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII_ID);
 102 #endif
 103
 104 #ifdef CONFIG_SYS_FSL_EC2
 105         ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])
 106                 & FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK;
 107         ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;
 108
 109         if (!ec)
 110                 wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII_ID);
 111 #endif
 112 }
 113 #endif