1 // SPDX-License-Identifier: GPL-2.0+
3 * NAND driver for TI DaVinci based boards.
5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
7 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
12 * linux/drivers/mtd/nand/raw/nand_davinci.c
16 * Copyright (C) 2006 Texas Instruments.
18 * ----------------------------------------------------------------------------
20 * ----------------------------------------------------------------------------
23 * This is a device driver for the NAND flash device found on the
24 * DaVinci board which utilizes the Samsung k9k2g08 part.
27 ver. 1.0: Feb 2005, Vinod/Sudhakar
33 #include <linux/mtd/rawnand.h>
36 #include <dm/uclass.h>
37 #include <asm/ti-common/davinci_nand.h>
39 /* Definitions for 4-bit hardware ECC */
40 #define NAND_TIMEOUT 10240
41 #define NAND_ECC_BUSY 0xC
42 #define NAND_4BITECC_MASK 0x03FF03FF
43 #define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
44 #define ECC_STATE_NO_ERR 0x0
45 #define ECC_STATE_TOO_MANY_ERRS 0x1
46 #define ECC_STATE_ERR_CORR_COMP_P 0x2
47 #define ECC_STATE_ERR_CORR_COMP_N 0x3
50 * Exploit the little endianness of the ARM to do multi-byte transfers
51 * per device read. This can perform over twice as quickly as individual
52 * byte transfers when buffer alignment is conducive.
54 * NOTE: This only works if the NAND is not connected to the 2 LSBs of
55 * the address bus. On Davinci EVM platforms this has always been true.
57 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
59 struct nand_chip *chip = mtd_to_nand(mtd);
60 const u32 *nand = chip->IO_ADDR_R;
62 /* Make sure that buf is 32 bit aligned */
63 if (((int)buf & 0x3) != 0) {
64 if (((int)buf & 0x1) != 0) {
72 if (((int)buf & 0x3) != 0) {
74 *(u16 *)buf = readw(nand);
81 /* copy aligned data */
83 *(u32 *)buf = __raw_readl(nand);
88 /* mop up any remaining bytes */
91 *(u16 *)buf = readw(nand);
101 static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
104 struct nand_chip *chip = mtd_to_nand(mtd);
105 const u32 *nand = chip->IO_ADDR_W;
107 /* Make sure that buf is 32 bit aligned */
108 if (((int)buf & 0x3) != 0) {
109 if (((int)buf & 0x1) != 0) {
117 if (((int)buf & 0x3) != 0) {
119 writew(*(u16 *)buf, nand);
126 /* copy aligned data */
128 __raw_writel(*(u32 *)buf, nand);
133 /* mop up any remaining bytes */
136 writew(*(u16 *)buf, nand);
146 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
149 struct nand_chip *this = mtd_to_nand(mtd);
150 u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
152 if (ctrl & NAND_CTRL_CHANGE) {
153 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
156 IO_ADDR_W |= MASK_CLE;
158 IO_ADDR_W |= MASK_ALE;
159 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
162 if (cmd != NAND_CMD_NONE)
163 writeb(cmd, IO_ADDR_W);
166 #ifdef CONFIG_SYS_NAND_HW_ECC
168 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
172 ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
173 CFG_SYS_NAND_CS - 2]));
178 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
182 /* reading the ECC result register resets the ECC calculation */
183 nand_davinci_readecc(mtd);
185 val = __raw_readl(&davinci_emif_regs->nandfcr);
186 val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS);
187 val |= DAVINCI_NANDFCR_1BIT_ECC_START(CFG_SYS_NAND_CS);
188 __raw_writel(val, &davinci_emif_regs->nandfcr);
191 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
196 tmp = nand_davinci_readecc(mtd);
198 /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
199 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
200 tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
202 /* Invert so that erased block ECC is correct */
206 *ecc_code++ = tmp >> 8;
207 *ecc_code++ = tmp >> 16;
209 /* NOTE: the above code matches mainline Linux:
210 * .PQR.stu ==> ~PQRstu
212 * MontaVista/TI kernels encode those bytes differently, use
213 * complicated (and allegedly sometimes-wrong) correction code,
214 * and usually shipped with U-Boot that uses software ECC:
215 * .PQR.stu ==> PsQRtu
217 * If you need MV/TI compatible NAND I/O in U-Boot, it should
218 * be possible to (a) change the mangling above, (b) reverse
219 * that mangling in nand_davinci_correct_data() below.
225 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
226 u_char *read_ecc, u_char *calc_ecc)
228 struct nand_chip *this = mtd_to_nand(mtd);
229 u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
231 u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
233 u_int32_t diff = ecc_calc ^ ecc_nand;
236 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
237 /* Correctable error */
238 if ((diff >> (12 + 3)) < this->ecc.size) {
239 uint8_t find_bit = 1 << ((diff >> 12) & 7);
240 uint32_t find_byte = diff >> (12 + 3);
242 dat[find_byte] ^= find_bit;
243 pr_debug("Correcting single "
244 "bit ECC error at offset: %d, bit: "
245 "%d\n", find_byte, find_bit);
250 } else if (!(diff & (diff - 1))) {
251 /* Single bit ECC error in the ECC itself,
253 pr_debug("Single bit ECC error in " "ECC.\n");
256 /* Uncorrectable error */
257 pr_debug("ECC UNCORRECTED_ERROR 1\n");
263 #endif /* CONFIG_SYS_NAND_HW_ECC */
265 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
266 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
267 #if defined(CONFIG_SYS_NAND_PAGE_2K)
269 #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
271 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
272 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
273 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
274 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
277 {2, 4}, {16, 6}, {32, 6}, {48, 6},
282 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
283 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
284 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
288 {.offset = 2, .length = 22, },
290 #endif /* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */
291 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
294 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
295 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
296 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
297 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
298 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
299 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
300 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
301 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
304 {.offset = 2, .length = 46, },
309 #if defined CONFIG_KEYSTONE_RBL_NAND
310 static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
311 #if defined(CONFIG_SYS_NAND_PAGE_2K)
314 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
315 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
316 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
317 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
320 {.offset = 2, .length = 4, },
321 {.offset = 16, .length = 6, },
322 {.offset = 32, .length = 6, },
323 {.offset = 48, .length = 6, },
325 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
328 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
329 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
330 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
331 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
332 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
333 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
334 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
335 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
338 {.offset = 2, .length = 4, },
339 {.offset = 16, .length = 6, },
340 {.offset = 32, .length = 6, },
341 {.offset = 48, .length = 6, },
342 {.offset = 64, .length = 6, },
343 {.offset = 80, .length = 6, },
344 {.offset = 96, .length = 6, },
345 {.offset = 112, .length = 6, },
350 #ifdef CONFIG_SYS_NAND_PAGE_2K
351 #define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 11)
352 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
353 #define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 12)
357 * nand_davinci_write_page - write one page
358 * @mtd: MTD device structure
359 * @chip: NAND chip descriptor
360 * @buf: the data to write
361 * @oob_required: must write chip->oob_poi to OOB
362 * @page: page number to write
363 * @raw: use _raw version of write_page
365 static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
366 uint32_t offset, int data_len,
367 const uint8_t *buf, int oob_required,
372 struct nand_ecclayout *saved_ecc_layout;
374 /* save current ECC layout and assign Keystone RBL ECC layout */
375 if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
376 saved_ecc_layout = chip->ecc.layout;
377 chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
378 mtd->oobavail = chip->ecc.layout->oobavail;
381 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
384 status = chip->ecc.write_page_raw(mtd, chip, buf,
387 status = chip->ecc.write_page(mtd, chip, buf,
396 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
397 status = chip->waitfunc(mtd, chip);
399 if (status & NAND_STATUS_FAIL) {
405 /* restore ECC layout */
406 if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
407 chip->ecc.layout = saved_ecc_layout;
408 mtd->oobavail = saved_ecc_layout->oobavail;
415 * nand_davinci_read_page_hwecc - hardware ECC based page read function
416 * @mtd: mtd info structure
417 * @chip: nand chip info structure
418 * @buf: buffer to store read data
419 * @oob_required: caller requires OOB data read to chip->oob_poi
420 * @page: page number to read
422 * Not for syndrome calculating ECC controllers which need a special oob layout.
424 static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
425 uint8_t *buf, int oob_required, int page)
427 int i, eccsize = chip->ecc.size;
428 int eccbytes = chip->ecc.bytes;
429 int eccsteps = chip->ecc.steps;
432 uint8_t *ecc_code = chip->buffers->ecccode;
433 uint8_t *ecc_calc = chip->buffers->ecccalc;
434 struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
436 /* save current ECC layout and assign Keystone RBL ECC layout */
437 if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
438 chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
439 mtd->oobavail = chip->ecc.layout->oobavail;
442 eccpos = chip->ecc.layout->eccpos;
444 /* Read the OOB area first */
445 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
446 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
447 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
449 for (i = 0; i < chip->ecc.total; i++)
450 ecc_code[i] = chip->oob_poi[eccpos[i]];
452 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
455 chip->ecc.hwctl(mtd, NAND_ECC_READ);
456 chip->read_buf(mtd, p, eccsize);
457 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
459 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
461 mtd->ecc_stats.failed++;
463 mtd->ecc_stats.corrected += stat;
466 /* restore ECC layout */
467 if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
468 chip->ecc.layout = saved_ecc_layout;
469 mtd->oobavail = saved_ecc_layout->oobavail;
474 #endif /* CONFIG_KEYSTONE_RBL_NAND */
476 static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
484 * Start a new ECC calculation for reading or writing 512 bytes
487 val = __raw_readl(&davinci_emif_regs->nandfcr);
488 val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
489 val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS);
490 val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CFG_SYS_NAND_CS);
491 val |= DAVINCI_NANDFCR_4BIT_ECC_START;
492 __raw_writel(val, &davinci_emif_regs->nandfcr);
494 case NAND_ECC_READSYN:
495 val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
502 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
506 for (i = 0; i < 4; i++) {
507 ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
514 static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
518 unsigned int hw_4ecc[4];
521 nand_davinci_4bit_readecc(mtd, hw_4ecc);
523 /*Convert 10 bit ecc value to 8 bit */
524 for (i = 0; i < 2; i++) {
525 unsigned int hw_ecc_low = hw_4ecc[i * 2];
526 unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
528 /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
529 *ecc_code++ = hw_ecc_low & 0xFF;
532 * Take 2 bits as LSB bits from val1 (count1=0) or val5
533 * (count1=1) and 6 bits from val2 (count1=0) or
537 ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
540 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
541 * 4 bits from val3 (count1=0) or val6 (count1=1)
544 ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
547 * Take 6 bits from val3(count1=0) or val6 (count1=1) and
548 * 2 bits from val4 (count1=0) or val7 (count1=1)
551 ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
553 /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
554 *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
560 static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
561 uint8_t *read_ecc, uint8_t *calc_ecc)
564 unsigned int hw_4ecc[4];
565 unsigned int iserror;
566 unsigned short *ecc16;
567 unsigned int numerrors, erroraddress, errorvalue;
571 * Check for an ECC where all bytes are 0xFF. If this is the case, we
572 * will assume we are looking at an erased page and we should ignore
575 for (i = 0; i < 10; i++) {
576 if (read_ecc[i] != 0xFF)
582 /* Convert 8 bit in to 10 bit */
583 ecc16 = (unsigned short *)&read_ecc[0];
586 * Write the parity values in the NAND Flash 4-bit ECC Load register.
587 * Write each parity value one at a time starting from 4bit_ecc_val8
591 /*Take 2 bits from 8th byte and 8 bits from 9th byte */
592 __raw_writel(((ecc16[4]) >> 6) & 0x3FF,
593 &davinci_emif_regs->nand4biteccload);
595 /* Take 4 bits from 7th byte and 6 bits from 8th byte */
596 __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
597 &davinci_emif_regs->nand4biteccload);
599 /* Take 6 bits from 6th byte and 4 bits from 7th byte */
600 __raw_writel((ecc16[3] >> 2) & 0x3FF,
601 &davinci_emif_regs->nand4biteccload);
603 /* Take 8 bits from 5th byte and 2 bits from 6th byte */
604 __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
605 &davinci_emif_regs->nand4biteccload);
607 /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
608 __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
609 &davinci_emif_regs->nand4biteccload);
611 /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
612 __raw_writel(((ecc16[1]) >> 4) & 0x3FF,
613 &davinci_emif_regs->nand4biteccload);
615 /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
616 __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
617 &davinci_emif_regs->nand4biteccload);
619 /* Take 10 bits from 0th and 1st bytes */
620 __raw_writel((ecc16[0]) & 0x3FF,
621 &davinci_emif_regs->nand4biteccload);
624 * Perform a dummy read to the EMIF Revision Code and Status register.
625 * This is required to ensure time for syndrome calculation after
626 * writing the ECC values in previous step.
629 val = __raw_readl(&davinci_emif_regs->nandfsr);
632 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
633 * A syndrome value of 0 means no bit errors. If the syndrome is
634 * non-zero then go further otherwise return.
636 nand_davinci_4bit_readecc(mtd, hw_4ecc);
638 if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
642 * Clear any previous address calculation by doing a dummy read of an
643 * error address register.
645 val = __raw_readl(&davinci_emif_regs->nanderradd1);
648 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
651 __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
652 &davinci_emif_regs->nandfcr);
655 * Wait for the corr_state field (bits 8 to 11) in the
656 * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
657 * Otherwise ECC calculation has not even begun and the next loop might
658 * fail because of a false positive!
662 val = __raw_readl(&davinci_emif_regs->nandfsr);
665 } while ((i > 0) && !val);
668 * Wait for the corr_state field (bits 8 to 11) in the
669 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
673 val = __raw_readl(&davinci_emif_regs->nandfsr);
676 } while ((i > 0) && val);
678 iserror = __raw_readl(&davinci_emif_regs->nandfsr);
679 iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
680 iserror = iserror >> 8;
683 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
684 * corrected (five or more errors). The number of errors
685 * calculated (err_num field) differs from the number of errors
686 * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
687 * correction complete (errors on bit 8 or 9).
688 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
689 * complete (error exists).
692 if (iserror == ECC_STATE_NO_ERR) {
693 val = __raw_readl(&davinci_emif_regs->nanderrval1);
695 } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
696 val = __raw_readl(&davinci_emif_regs->nanderrval1);
700 numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
703 /* Read the error address, error value and correct */
704 for (i = 0; i < numerrors; i++) {
707 ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
708 (16 * (i & 1))) & 0x3FF);
709 erroraddress = ((512 + 7) - erroraddress);
711 ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
712 (16 * (i & 1))) & 0xFF);
715 ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
716 (16 * (i & 1))) & 0x3FF);
717 erroraddress = ((512 + 7) - erroraddress);
719 ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
720 (16 * (i & 1))) & 0xFF);
722 /* xor the corrupt data with error value */
723 if (erroraddress < 512)
724 dat[erroraddress] ^= errorvalue;
729 #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
731 static int nand_davinci_dev_ready(struct mtd_info *mtd)
733 return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
736 static void davinci_nand_init(struct nand_chip *nand)
738 #if defined CONFIG_KEYSTONE_RBL_NAND
740 struct nand_ecclayout *layout;
742 layout = &nand_keystone_rbl_4bit_layout_oobfirst;
743 layout->oobavail = 0;
744 for (i = 0; i < ARRAY_SIZE(layout->oobfree) &&
745 layout->oobfree[i].length; i++)
746 layout->oobavail += layout->oobfree[i].length;
748 nand->write_page = nand_davinci_write_page;
749 nand->ecc.read_page = nand_davinci_read_page_hwecc;
751 nand->chip_delay = 0;
752 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
753 nand->bbt_options |= NAND_BBT_USE_FLASH;
755 #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
756 nand->options |= NAND_NO_SUBPAGE_WRITE;
758 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
759 nand->options |= NAND_BUSWIDTH_16;
761 #ifdef CONFIG_SYS_NAND_HW_ECC
762 nand->ecc.mode = NAND_ECC_HW;
763 nand->ecc.size = 512;
765 nand->ecc.strength = 1;
766 nand->ecc.calculate = nand_davinci_calculate_ecc;
767 nand->ecc.correct = nand_davinci_correct_data;
768 nand->ecc.hwctl = nand_davinci_enable_hwecc;
769 #elif defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST)
770 nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
771 nand->ecc.size = 512;
772 nand->ecc.bytes = 10;
773 nand->ecc.strength = 4;
774 nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
775 nand->ecc.correct = nand_davinci_4bit_correct_data;
776 nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
777 nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
778 #elif defined(CONFIG_SYS_NAND_SOFT_ECC)
779 nand->ecc.mode = NAND_ECC_SOFT;
781 /* Set address of hardware control function */
782 nand->cmd_ctrl = nand_davinci_hwcontrol;
784 nand->read_buf = nand_davinci_read_buf;
785 nand->write_buf = nand_davinci_write_buf;
787 nand->dev_ready = nand_davinci_dev_ready;
790 #if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
791 static int davinci_nand_probe(struct udevice *dev)
793 struct nand_chip *nand = dev_get_priv(dev);
794 struct mtd_info *mtd = nand_to_mtd(nand);
797 nand->IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE;
798 nand->IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE;
800 davinci_nand_init(nand);
802 ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
806 return nand_register(0, mtd);
809 static const struct udevice_id davinci_nand_ids[] = {
810 { .compatible = "ti,davinci-nand" },
814 U_BOOT_DRIVER(davinci_nand) = {
815 .name = "davinci-nand",
817 .of_match = davinci_nand_ids,
818 .probe = davinci_nand_probe,
819 .priv_auto = sizeof(struct nand_chip),
822 void board_nand_init(void)
827 ret = uclass_get_device_by_driver(UCLASS_MTD,
828 DM_DRIVER_GET(davinci_nand), &dev);
829 if (ret && ret != -ENODEV)
830 pr_err("Failed to initialize %s: %d\n", dev->name, ret);
833 int board_nand_init(struct nand_chip *chip) __attribute__((weak));
834 int board_nand_init(struct nand_chip *chip)
836 davinci_nand_init(chip);
839 #endif /* CONFIG_SYS_NAND_SELF_INIT */