1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2017 Free Electrons
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
8 * Derived from the atmel_nand.c driver which contained the following
11 * Copyright 2003 Rick Bronson
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
14 * Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
16 * Derived from drivers/mtd/spia.c (removed in v3.8)
17 * Copyright 2000 Steven J. Hill (sjhill@cotw.com)
20 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
21 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
25 * Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
27 * Add Programmable Multibit ECC support for various AT91 SoC
28 * Copyright 2012 ATMEL, Hong Xu
30 * Add Nand Flash Controller support for SAMA5 SoC
31 * Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
34 * Balamanikandan Gunasundar(balamanikandan.gunasundar@microchip.com)
35 * Copyright (C) 2022 Microchip Technology Inc.
37 * A few words about the naming convention in this file. This convention
38 * applies to structure and function names.
42 * - atmel_nand_: all generic structures/functions
43 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
44 * (at91sam9 and avr32 SoCs)
45 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
46 * (sama5 SoCs and later)
47 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
48 * that is available in the HSMC block
49 * - <soc>_nand_: all SoC specific structures/functions
52 #include <asm-generic/gpio.h>
54 #include <dm/device_compat.h>
55 #include <dm/devres.h>
56 #include <dm/of_addr.h>
57 #include <dm/of_access.h>
58 #include <dm/uclass.h>
59 #include <linux/completion.h>
61 #include <linux/iopoll.h>
62 #include <linux/ioport.h>
63 #include <linux/mfd/syscon/atmel-matrix.h>
64 #include <linux/mfd/syscon/atmel-smc.h>
65 #include <linux/mtd/rawnand.h>
66 #include <linux/mtd/mtd.h>
67 #include <mach/at91_sfr.h>
74 #define NSEC_PER_SEC 1000000000L
76 #define ATMEL_HSMC_NFC_CFG 0x0
77 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x) (((x) / 4) << 24)
78 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK GENMASK(30, 24)
79 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul) (((cyc) << 16) | ((mul) << 20))
80 #define ATMEL_HSMC_NFC_CFG_DTO_MAX GENMASK(22, 16)
81 #define ATMEL_HSMC_NFC_CFG_RBEDGE BIT(13)
82 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE BIT(12)
83 #define ATMEL_HSMC_NFC_CFG_RSPARE BIT(9)
84 #define ATMEL_HSMC_NFC_CFG_WSPARE BIT(8)
85 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK GENMASK(2, 0)
86 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x) (fls((x) / 512) - 1)
88 #define ATMEL_HSMC_NFC_CTRL 0x4
89 #define ATMEL_HSMC_NFC_CTRL_EN BIT(0)
90 #define ATMEL_HSMC_NFC_CTRL_DIS BIT(1)
92 #define ATMEL_HSMC_NFC_SR 0x8
93 #define ATMEL_HSMC_NFC_IER 0xc
94 #define ATMEL_HSMC_NFC_IDR 0x10
95 #define ATMEL_HSMC_NFC_IMR 0x14
96 #define ATMEL_HSMC_NFC_SR_ENABLED BIT(1)
97 #define ATMEL_HSMC_NFC_SR_RB_RISE BIT(4)
98 #define ATMEL_HSMC_NFC_SR_RB_FALL BIT(5)
99 #define ATMEL_HSMC_NFC_SR_BUSY BIT(8)
100 #define ATMEL_HSMC_NFC_SR_WR BIT(11)
101 #define ATMEL_HSMC_NFC_SR_CSID GENMASK(14, 12)
102 #define ATMEL_HSMC_NFC_SR_XFRDONE BIT(16)
103 #define ATMEL_HSMC_NFC_SR_CMDDONE BIT(17)
104 #define ATMEL_HSMC_NFC_SR_DTOE BIT(20)
105 #define ATMEL_HSMC_NFC_SR_UNDEF BIT(21)
106 #define ATMEL_HSMC_NFC_SR_AWB BIT(22)
107 #define ATMEL_HSMC_NFC_SR_NFCASE BIT(23)
108 #define ATMEL_HSMC_NFC_SR_ERRORS (ATMEL_HSMC_NFC_SR_DTOE | \
109 ATMEL_HSMC_NFC_SR_UNDEF | \
110 ATMEL_HSMC_NFC_SR_AWB | \
111 ATMEL_HSMC_NFC_SR_NFCASE)
112 #define ATMEL_HSMC_NFC_SR_RBEDGE(x) BIT((x) + 24)
114 #define ATMEL_HSMC_NFC_ADDR 0x18
115 #define ATMEL_HSMC_NFC_BANK 0x1c
117 #define ATMEL_NFC_MAX_RB_ID 7
119 #define ATMEL_NFC_SRAM_SIZE 0x2400
121 #define ATMEL_NFC_CMD(pos, cmd) ((cmd) << (((pos) * 8) + 2))
122 #define ATMEL_NFC_VCMD2 BIT(18)
123 #define ATMEL_NFC_ACYCLE(naddrs) ((naddrs) << 19)
124 #define ATMEL_NFC_CSID(cs) ((cs) << 22)
125 #define ATMEL_NFC_DATAEN BIT(25)
126 #define ATMEL_NFC_NFCWR BIT(26)
128 #define ATMEL_NFC_MAX_ADDR_CYCLES 5
130 #define ATMEL_NAND_ALE_OFFSET BIT(21)
131 #define ATMEL_NAND_CLE_OFFSET BIT(22)
133 #define DEFAULT_TIMEOUT_MS 1000
134 #define MIN_DMA_LEN 128
136 static struct nand_ecclayout atmel_pmecc_oobinfo;
138 struct nand_controller_ops {
139 int (*attach_chip)(struct nand_chip *chip);
140 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
141 const struct nand_data_interface *conf);
144 struct nand_controller {
145 const struct nand_controller_ops *ops;
148 enum atmel_nand_rb_type {
150 ATMEL_NAND_NATIVE_RB,
154 struct atmel_nand_rb {
155 enum atmel_nand_rb_type type;
157 struct gpio_desc gpio;
162 struct atmel_nand_cs {
164 struct atmel_nand_rb rb;
165 struct gpio_desc csgpio;
171 struct atmel_smc_cs_conf smcconf;
175 struct list_head node;
177 struct nand_chip base;
178 struct atmel_nand_cs *activecs;
179 struct atmel_pmecc_user *pmecc;
180 struct gpio_desc cdgpio;
182 struct nand_controller *controller;
183 struct atmel_nand_cs cs[];
186 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
188 return container_of(chip, struct atmel_nand, base);
191 enum atmel_nfc_data_xfer {
194 ATMEL_NFC_WRITE_DATA,
197 struct atmel_nfc_op {
203 enum atmel_nfc_data_xfer data;
208 struct atmel_nand_controller;
209 struct atmel_nand_controller_caps;
211 struct atmel_nand_controller_ops {
212 int (*probe)(struct udevice *udev,
213 const struct atmel_nand_controller_caps *caps);
214 int (*remove)(struct atmel_nand_controller *nc);
215 void (*nand_init)(struct atmel_nand_controller *nc,
216 struct atmel_nand *nand);
217 int (*ecc_init)(struct nand_chip *chip);
218 int (*setup_data_interface)(struct atmel_nand *nand, int csline,
219 const struct nand_data_interface *conf);
222 struct atmel_nand_controller_caps {
224 bool legacy_of_bindings;
227 const char *ebi_csa_regmap_name;
228 const struct atmel_nand_controller_ops *ops;
231 struct atmel_nand_controller {
232 struct nand_controller base;
233 const struct atmel_nand_controller_caps *caps;
236 struct dma_chan *dmac;
237 struct atmel_pmecc *pmecc;
238 struct list_head chips;
242 static inline struct atmel_nand_controller *
243 to_nand_controller(struct nand_controller *ctl)
245 return container_of(ctl, struct atmel_nand_controller, base);
248 struct atmel_smc_nand_ebi_csa_cfg {
253 struct atmel_smc_nand_controller {
254 struct atmel_nand_controller base;
255 struct regmap *ebi_csa_regmap;
256 struct atmel_smc_nand_ebi_csa_cfg *ebi_csa;
259 static inline struct atmel_smc_nand_controller *
260 to_smc_nand_controller(struct nand_controller *ctl)
262 return container_of(to_nand_controller(ctl),
263 struct atmel_smc_nand_controller, base);
266 struct atmel_hsmc_nand_controller {
267 struct atmel_nand_controller base;
269 struct gen_pool *pool;
273 const struct atmel_hsmc_reg_layout *hsmc_layout;
275 struct atmel_nfc_op op;
276 struct completion complete;
279 /* Only used when instantiating from legacy DT bindings. */
283 static inline struct atmel_hsmc_nand_controller *
284 to_hsmc_nand_controller(struct nand_controller *ctl)
286 return container_of(to_nand_controller(ctl),
287 struct atmel_hsmc_nand_controller, base);
290 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
291 int oobsize, int ecc_len)
295 layout->eccbytes = ecc_len;
297 /* ECC will occupy the last ecc_len bytes continuously */
298 for (i = 0; i < ecc_len; i++)
299 layout->eccpos[i] = oobsize - ecc_len + i;
301 layout->oobfree[0].offset = 2;
302 layout->oobfree[0].length =
303 oobsize - ecc_len - layout->oobfree[0].offset;
306 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
308 op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
309 op->wait ^= status & op->wait;
311 return !op->wait || op->errors;
314 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
315 unsigned int timeout_ms)
321 timeout_ms = DEFAULT_TIMEOUT_MS;
324 ret = regmap_read_poll_timeout(nc->base.smc,
325 ATMEL_HSMC_NFC_SR, status,
326 atmel_nfc_op_done(&nc->op,
332 if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
333 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
337 if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
338 dev_err(nc->base.dev, "Access to an undefined area\n");
342 if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
343 dev_err(nc->base.dev, "Access while busy\n");
347 if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
348 dev_err(nc->base.dev, "Wrong access size\n");
355 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
359 for (i = 0; i < len; i++)
360 writeb(buf[i], addr);
363 static void ioread8_rep(void *addr, uint8_t *buf, int len)
367 for (i = 0; i < len; i++)
368 buf[i] = readb(addr);
371 static void ioread16_rep(void *addr, void *buf, int len)
376 for (i = 0; i < len; i++)
380 static void iowrite16_rep(void *addr, const void *buf, int len)
385 for (i = 0; i < len; i++)
389 static u8 atmel_nand_read_byte(struct mtd_info *mtd)
391 struct nand_chip *chip = mtd_to_nand(mtd);
392 struct atmel_nand *nand = to_atmel_nand(chip);
394 return ioread8(nand->activecs->io.virt);
397 static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
399 struct nand_chip *chip = mtd_to_nand(mtd);
400 struct atmel_nand *nand = to_atmel_nand(chip);
402 if (chip->options & NAND_BUSWIDTH_16)
403 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
405 iowrite8(byte, nand->activecs->io.virt);
408 static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
410 struct nand_chip *chip = mtd_to_nand(mtd);
411 struct atmel_nand *nand = to_atmel_nand(chip);
413 if (chip->options & NAND_BUSWIDTH_16)
414 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
416 ioread8_rep(nand->activecs->io.virt, buf, len);
419 static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
421 struct nand_chip *chip = mtd_to_nand(mtd);
422 struct atmel_nand *nand = to_atmel_nand(chip);
424 if (chip->options & NAND_BUSWIDTH_16)
425 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
427 iowrite8_rep(nand->activecs->io.virt, buf, len);
430 static int atmel_nand_dev_ready(struct mtd_info *mtd)
432 struct nand_chip *chip = mtd_to_nand(mtd);
433 struct atmel_nand *nand = to_atmel_nand(chip);
435 return dm_gpio_get_value(&nand->activecs->rb.gpio);
438 static void atmel_nand_select_chip(struct mtd_info *mtd, int cs)
440 struct nand_chip *chip = mtd_to_nand(mtd);
441 struct atmel_nand *nand = to_atmel_nand(chip);
443 if (cs < 0 || cs >= nand->numcs) {
444 nand->activecs = NULL;
445 chip->dev_ready = NULL;
449 nand->activecs = &nand->cs[cs];
451 if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
452 chip->dev_ready = atmel_nand_dev_ready;
455 static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
457 struct nand_chip *chip = mtd_to_nand(mtd);
458 struct atmel_nand *nand = to_atmel_nand(chip);
459 struct atmel_hsmc_nand_controller *nc;
462 nc = to_hsmc_nand_controller(nand->controller);
464 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
466 return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
469 static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
471 struct nand_chip *chip = mtd_to_nand(mtd);
472 struct atmel_nand *nand = to_atmel_nand(chip);
473 struct atmel_hsmc_nand_controller *nc;
475 nc = to_hsmc_nand_controller(nand->controller);
477 atmel_nand_select_chip(mtd, cs);
479 if (!nand->activecs) {
480 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
481 ATMEL_HSMC_NFC_CTRL_DIS);
485 if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
486 chip->dev_ready = atmel_hsmc_nand_dev_ready;
488 regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
489 ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
490 ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
491 ATMEL_HSMC_NFC_CFG_RSPARE |
492 ATMEL_HSMC_NFC_CFG_WSPARE,
493 ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
494 ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
495 ATMEL_HSMC_NFC_CFG_RSPARE);
496 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
497 ATMEL_HSMC_NFC_CTRL_EN);
500 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
502 u8 *addrs = nc->op.addrs;
507 nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
509 for (i = 0; i < nc->op.ncmds; i++)
510 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
512 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
513 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
515 op |= ATMEL_NFC_CSID(nc->op.cs) |
516 ATMEL_NFC_ACYCLE(nc->op.naddrs);
518 if (nc->op.ncmds > 1)
519 op |= ATMEL_NFC_VCMD2;
521 addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
524 if (nc->op.data != ATMEL_NFC_NO_DATA) {
525 op |= ATMEL_NFC_DATAEN;
526 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
528 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
529 op |= ATMEL_NFC_NFCWR;
532 /* Clear all flags. */
533 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
535 /* Send the command. */
536 regmap_write(nc->io, op, addr);
538 ret = atmel_nfc_wait(nc, poll, 0);
540 dev_err(nc->base.dev,
541 "Failed to send NAND command (err = %d)!",
544 /* Reset the op state. */
545 memset(&nc->op, 0, sizeof(nc->op));
550 static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
553 struct nand_chip *chip = mtd_to_nand(mtd);
554 struct atmel_nand *nand = to_atmel_nand(chip);
555 struct atmel_hsmc_nand_controller *nc;
557 nc = to_hsmc_nand_controller(nand->controller);
559 if (ctrl & NAND_ALE) {
560 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
563 nc->op.addrs[nc->op.naddrs++] = dat;
564 } else if (ctrl & NAND_CLE) {
565 if (nc->op.ncmds > 1)
568 nc->op.cmds[nc->op.ncmds++] = dat;
571 if (dat == NAND_CMD_NONE) {
572 nc->op.cs = nand->activecs->id;
573 atmel_nfc_exec_op(nc, true);
577 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
580 struct nand_chip *chip = mtd_to_nand(mtd);
581 struct atmel_nand *nand = to_atmel_nand(chip);
582 struct atmel_nand_controller *nc;
584 nc = to_nand_controller(nand->controller);
586 if ((ctrl & NAND_CTRL_CHANGE) &&
587 dm_gpio_is_valid(&nand->activecs->csgpio)) {
589 dm_gpio_set_value(&nand->activecs->csgpio, 0);
591 dm_gpio_set_value(&nand->activecs->csgpio, 1);
595 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
596 else if (ctrl & NAND_CLE)
597 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
600 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
603 struct mtd_info *mtd = nand_to_mtd(chip);
604 struct atmel_nand *nand = to_atmel_nand(chip);
605 struct atmel_hsmc_nand_controller *nc;
608 nc = to_hsmc_nand_controller(nand->controller);
611 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
614 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
618 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
621 struct mtd_info *mtd = nand_to_mtd(chip);
622 struct atmel_nand *nand = to_atmel_nand(chip);
623 struct atmel_hsmc_nand_controller *nc;
626 nc = to_hsmc_nand_controller(nand->controller);
629 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
632 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
636 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
638 struct mtd_info *mtd = nand_to_mtd(chip);
639 struct atmel_nand *nand = to_atmel_nand(chip);
640 struct atmel_hsmc_nand_controller *nc;
642 nc = to_hsmc_nand_controller(nand->controller);
645 nc->op.addrs[nc->op.naddrs++] = column;
648 * 2 address cycles for the column offset on large page NANDs.
650 if (mtd->writesize > 512)
651 nc->op.addrs[nc->op.naddrs++] = column >> 8;
655 nc->op.addrs[nc->op.naddrs++] = page;
656 nc->op.addrs[nc->op.naddrs++] = page >> 8;
658 if (chip->options & NAND_ROW_ADDR_3)
659 nc->op.addrs[nc->op.naddrs++] = page >> 16;
663 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
665 struct atmel_nand *nand = to_atmel_nand(chip);
666 struct atmel_nand_controller *nc;
669 nc = to_nand_controller(nand->controller);
674 ret = atmel_pmecc_enable(nand->pmecc, op);
677 "Failed to enable ECC engine (err = %d)\n", ret);
682 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
684 struct atmel_nand *nand = to_atmel_nand(chip);
687 atmel_pmecc_disable(nand->pmecc);
690 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
692 struct atmel_nand *nand = to_atmel_nand(chip);
693 struct mtd_info *mtd = nand_to_mtd(chip);
694 struct atmel_nand_controller *nc;
695 struct mtd_oob_region oobregion;
699 nc = to_nand_controller(nand->controller);
704 ret = atmel_pmecc_wait_rdy(nand->pmecc);
707 "Failed to transfer NAND page data (err = %d)\n",
712 mtd_ooblayout_ecc(mtd, 0, &oobregion);
713 eccbuf = chip->oob_poi + oobregion.offset;
715 for (i = 0; i < chip->ecc.steps; i++) {
716 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
718 eccbuf += chip->ecc.bytes;
724 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
727 struct atmel_nand *nand = to_atmel_nand(chip);
728 struct mtd_info *mtd = nand_to_mtd(chip);
729 struct atmel_nand_controller *nc;
730 struct mtd_oob_region oobregion;
731 int ret, i, max_bitflips = 0;
732 void *databuf, *eccbuf;
734 nc = to_nand_controller(nand->controller);
739 ret = atmel_pmecc_wait_rdy(nand->pmecc);
742 "Failed to read NAND page data (err = %d)\n", ret);
746 mtd_ooblayout_ecc(mtd, 0, &oobregion);
747 eccbuf = chip->oob_poi + oobregion.offset;
750 for (i = 0; i < chip->ecc.steps; i++) {
751 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
753 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
754 ret = nand_check_erased_ecc_chunk(databuf,
762 max_bitflips = max(ret, max_bitflips);
764 mtd->ecc_stats.failed++;
766 databuf += chip->ecc.size;
767 eccbuf += chip->ecc.bytes;
773 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
774 bool oob_required, int page, bool raw)
776 struct mtd_info *mtd = nand_to_mtd(chip);
777 struct atmel_nand *nand = to_atmel_nand(chip);
780 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
782 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
786 atmel_nand_write_buf(mtd, buf, mtd->writesize);
788 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
790 atmel_pmecc_disable(nand->pmecc);
794 atmel_nand_pmecc_disable(chip, raw);
796 atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
798 return nand_prog_page_end_op(chip);
801 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
802 struct nand_chip *chip, const u8 *buf,
803 int oob_required, int page)
805 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
808 static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd,
809 struct nand_chip *chip,
810 const u8 *buf, int oob_required,
813 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
816 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
817 bool oob_required, int page, bool raw)
819 struct mtd_info *mtd = nand_to_mtd(chip);
822 nand_read_page_op(chip, page, 0, NULL, 0);
824 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
828 atmel_nand_read_buf(mtd, buf, mtd->writesize);
829 atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
831 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
833 atmel_nand_pmecc_disable(chip, raw);
838 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
839 struct nand_chip *chip, u8 *buf,
840 int oob_required, int page)
842 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
845 static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd,
846 struct nand_chip *chip, u8 *buf,
847 int oob_required, int page)
849 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
852 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
853 const u8 *buf, bool oob_required,
856 struct mtd_info *mtd = nand_to_mtd(chip);
857 struct atmel_nand *nand = to_atmel_nand(chip);
858 struct atmel_hsmc_nand_controller *nc;
861 nc = to_hsmc_nand_controller(nand->controller);
863 atmel_nfc_copy_to_sram(chip, buf, false);
865 nc->op.cmds[0] = NAND_CMD_SEQIN;
867 atmel_nfc_set_op_addr(chip, page, 0x0);
868 nc->op.cs = nand->activecs->id;
869 nc->op.data = ATMEL_NFC_WRITE_DATA;
871 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
875 ret = atmel_nfc_exec_op(nc, true);
877 atmel_nand_pmecc_disable(chip, raw);
878 dev_err(nc->base.dev,
879 "Failed to transfer NAND page data (err = %d)\n",
884 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
886 atmel_nand_pmecc_disable(chip, raw);
891 atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
893 nc->op.cmds[0] = NAND_CMD_PAGEPROG;
895 nc->op.cs = nand->activecs->id;
896 ret = atmel_nfc_exec_op(nc, true);
898 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
901 status = chip->waitfunc(mtd, chip);
902 if (status & NAND_STATUS_FAIL)
909 atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
910 const u8 *buf, int oob_required,
913 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
918 atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
920 int oob_required, int page)
922 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
926 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
927 bool oob_required, int page,
930 struct mtd_info *mtd = nand_to_mtd(chip);
931 struct atmel_nand *nand = to_atmel_nand(chip);
932 struct atmel_hsmc_nand_controller *nc;
935 nc = to_hsmc_nand_controller(nand->controller);
938 * Optimized read page accessors only work when the NAND R/B pin is
939 * connected to a native SoC R/B pin. If that's not the case, fallback
940 * to the non-optimized one.
942 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
943 nand_read_page_op(chip, page, 0, NULL, 0);
945 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
949 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
951 if (mtd->writesize > 512)
952 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
954 atmel_nfc_set_op_addr(chip, page, 0x0);
955 nc->op.cs = nand->activecs->id;
956 nc->op.data = ATMEL_NFC_READ_DATA;
958 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
962 ret = atmel_nfc_exec_op(nc, true);
964 atmel_nand_pmecc_disable(chip, raw);
965 dev_err(nc->base.dev,
966 "Failed to load NAND page data (err = %d)\n",
971 atmel_nfc_copy_from_sram(chip, buf, true);
973 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
975 atmel_nand_pmecc_disable(chip, raw);
980 static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd,
981 struct nand_chip *chip, u8 *buf,
982 int oob_required, int page)
984 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
988 static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd,
989 struct nand_chip *chip,
990 u8 *buf, int oob_required,
993 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
997 static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section,
998 struct mtd_oob_region *oobregion)
1000 struct nand_chip *chip = mtd_to_nand(mtd);
1001 struct nand_ecc_ctrl *ecc = &chip->ecc;
1003 if (section || !ecc->total)
1006 oobregion->length = ecc->total;
1007 oobregion->offset = mtd->oobsize - oobregion->length;
1012 static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section,
1013 struct mtd_oob_region *oobregion)
1015 struct nand_chip *chip = mtd_to_nand(mtd);
1016 struct nand_ecc_ctrl *ecc = &chip->ecc;
1021 oobregion->length = mtd->oobsize - ecc->total - 2;
1022 oobregion->offset = 2;
1027 static const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = {
1028 .ecc = nand_ooblayout_ecc_lp,
1029 .rfree = nand_ooblayout_free_lp,
1032 const struct mtd_ooblayout_ops *nand_get_large_page_ooblayout(void)
1034 return &nand_ooblayout_lp_ops;
1037 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1039 struct mtd_info *mtd = nand_to_mtd(chip);
1040 struct atmel_nand *nand = to_atmel_nand(chip);
1041 struct atmel_nand_controller *nc;
1042 struct atmel_pmecc_user_req req;
1044 nc = to_nand_controller(nand->controller);
1047 dev_err(nc->dev, "HW ECC not supported\n");
1051 if (nc->caps->legacy_of_bindings) {
1054 if (!ofnode_read_u32(nc->dev->node_, "atmel,pmecc-cap", &val))
1055 chip->ecc.strength = val;
1057 if (!ofnode_read_u32(nc->dev->node_,
1058 "atmel,pmecc-sector-size",
1060 chip->ecc.size = val;
1063 if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1064 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1065 else if (chip->ecc.strength)
1066 req.ecc.strength = chip->ecc.strength;
1068 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1071 req.ecc.sectorsize = chip->ecc.size;
1073 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1075 req.pagesize = mtd->writesize;
1076 req.oobsize = mtd->oobsize;
1078 if (mtd->writesize <= 512) {
1080 req.ecc.ooboffset = 0;
1082 req.ecc.bytes = mtd->oobsize - 2;
1083 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1086 nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1087 if (IS_ERR(nand->pmecc))
1088 return PTR_ERR(nand->pmecc);
1090 chip->ecc.algo = NAND_ECC_BCH;
1091 chip->ecc.size = req.ecc.sectorsize;
1092 chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1093 chip->ecc.strength = req.ecc.strength;
1095 chip->options |= NAND_NO_SUBPAGE_WRITE;
1097 mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
1098 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1101 chip->ecc.layout = &atmel_pmecc_oobinfo;
1106 static int atmel_nand_ecc_init(struct nand_chip *chip)
1108 struct atmel_nand_controller *nc;
1109 struct atmel_nand *nand = to_atmel_nand(chip);
1112 nc = to_nand_controller(nand->controller);
1114 switch (chip->ecc.mode) {
1118 * Nothing to do, the core will initialize everything for us.
1123 ret = atmel_nand_pmecc_init(chip);
1127 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1128 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1129 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1130 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1134 /* Other modes are not supported. */
1135 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1143 static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
1147 ret = atmel_nand_ecc_init(chip);
1151 if (chip->ecc.mode != NAND_ECC_HW)
1154 /* Adjust the ECC operations for the HSMC IP. */
1155 chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1156 chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1157 chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1158 chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1163 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1164 const struct nand_data_interface *conf,
1165 struct atmel_smc_cs_conf *smcconf)
1167 u32 ncycles, totalcycles, timeps, mckperiodps;
1168 struct atmel_nand_controller *nc;
1171 nc = to_nand_controller(nand->controller);
1173 /* DDR interface not supported. */
1174 if (conf->type != NAND_SDR_IFACE)
1178 * tRC < 30ns implies EDO mode. This controller does not support this
1181 if (conf->timings.sdr.tRC_min < 30000)
1184 atmel_smc_cs_conf_init(smcconf);
1186 mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1187 mckperiodps *= 1000;
1190 * Set write pulse timing. This one is easy to extract:
1194 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1195 totalcycles = ncycles;
1196 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1202 * The write setup timing depends on the operation done on the NAND.
1203 * All operations goes through the same data bus, but the operation
1204 * type depends on the address we are writing to (ALE/CLE address
1206 * Since we have no way to differentiate the different operations at
1207 * the SMC level, we must consider the worst case (the biggest setup
1208 * time among all operation types):
1210 * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1212 timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1213 conf->timings.sdr.tALS_min);
1214 timeps = max(timeps, conf->timings.sdr.tDS_min);
1215 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1216 ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1217 totalcycles += ncycles;
1218 ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1224 * As for the write setup timing, the write hold timing depends on the
1225 * operation done on the NAND:
1227 * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1229 timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1230 conf->timings.sdr.tALH_min);
1231 timeps = max3(timeps, conf->timings.sdr.tDH_min,
1232 conf->timings.sdr.tWH_min);
1233 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1234 totalcycles += ncycles;
1237 * The write cycle timing is directly matching tWC, but is also
1238 * dependent on the other timings on the setup and hold timings we
1239 * calculated earlier, which gives:
1241 * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1243 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1244 ncycles = max(totalcycles, ncycles);
1245 ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1251 * We don't want the CS line to be toggled between each byte/word
1252 * transfer to the NAND. The only way to guarantee that is to have the
1253 * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1255 * NCS_WR_PULSE = NWE_CYCLE
1257 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1263 * As for the write setup timing, the read hold timing depends on the
1264 * operation done on the NAND:
1266 * NRD_HOLD = max(tREH, tRHOH)
1268 timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1269 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1270 totalcycles = ncycles;
1273 * TDF = tRHZ - NRD_HOLD
1275 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1276 ncycles -= totalcycles;
1279 * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1280 * we might end up with a config that does not fit in the TDF field.
1281 * Just take the max value in this case and hope that the NAND is more
1282 * tolerant than advertised.
1284 if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1285 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1286 else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1287 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1289 smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1290 ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1293 * Read pulse timing directly matches tRP:
1297 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1298 totalcycles += ncycles;
1299 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1305 * The write cycle timing is directly matching tWC, but is also
1306 * dependent on the setup and hold timings we calculated earlier,
1309 * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1311 * NRD_SETUP is always 0.
1313 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1314 ncycles = max(totalcycles, ncycles);
1315 ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1321 * We don't want the CS line to be toggled between each byte/word
1322 * transfer from the NAND. The only way to guarantee that is to have
1323 * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1325 * NCS_RD_PULSE = NRD_CYCLE
1327 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1332 /* Txxx timings are directly matching tXXX ones. */
1333 ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1334 ret = atmel_smc_cs_conf_set_timing(smcconf,
1335 ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1340 ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1341 ret = atmel_smc_cs_conf_set_timing(smcconf,
1342 ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1345 * Version 4 of the ONFI spec mandates that tADL be at least 400
1346 * nanoseconds, but, depending on the master clock rate, 400 ns may not
1347 * fit in the tADL field of the SMC reg. We need to relax the check and
1348 * accept the -ERANGE return code.
1350 * Note that previous versions of the ONFI spec had a lower tADL_min
1351 * (100 or 200 ns). It's not clear why this timing constraint got
1352 * increased but it seems most NANDs are fine with values lower than
1353 * 400ns, so we should be safe.
1355 if (ret && ret != -ERANGE)
1358 ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1359 ret = atmel_smc_cs_conf_set_timing(smcconf,
1360 ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1365 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1366 ret = atmel_smc_cs_conf_set_timing(smcconf,
1367 ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1372 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1373 ret = atmel_smc_cs_conf_set_timing(smcconf,
1374 ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1379 /* Attach the CS line to the NFC logic. */
1380 smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1382 /* Set the appropriate data bus width. */
1383 if (nand->base.options & NAND_BUSWIDTH_16)
1384 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1386 /* Operate in NRD/NWE READ/WRITEMODE. */
1387 smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1388 ATMEL_SMC_MODE_WRITEMODE_NWE;
1394 atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
1396 const struct nand_data_interface *conf)
1398 struct atmel_nand_controller *nc;
1399 struct atmel_smc_cs_conf smcconf;
1400 struct atmel_nand_cs *cs;
1403 nc = to_nand_controller(nand->controller);
1405 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1409 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1412 cs = &nand->cs[csline];
1413 cs->smcconf = smcconf;
1415 atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1421 atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
1423 const struct nand_data_interface *conf)
1425 struct atmel_hsmc_nand_controller *nc;
1426 struct atmel_smc_cs_conf smcconf;
1427 struct atmel_nand_cs *cs;
1430 nc = to_hsmc_nand_controller(nand->controller);
1432 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1436 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1439 cs = &nand->cs[csline];
1440 cs->smcconf = smcconf;
1442 if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1443 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1445 atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1451 static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline,
1452 const struct nand_data_interface *conf)
1454 struct nand_chip *chip = mtd_to_nand(mtd);
1455 struct atmel_nand *nand = to_atmel_nand(chip);
1456 struct atmel_nand_controller *nc;
1458 nc = to_nand_controller(nand->controller);
1460 if (csline >= nand->numcs ||
1461 (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1464 return nc->caps->ops->setup_data_interface(nand, csline, conf);
1467 #define NAND_KEEP_TIMINGS 0x00800000
1469 static void atmel_nand_init(struct atmel_nand_controller *nc,
1470 struct atmel_nand *nand)
1472 struct nand_chip *chip = &nand->base;
1473 struct mtd_info *mtd = nand_to_mtd(chip);
1475 mtd->dev->parent = nc->dev;
1476 nand->controller = &nc->base;
1477 nand->controller = &nc->base;
1479 chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1480 chip->read_byte = atmel_nand_read_byte;
1481 chip->write_byte = atmel_nand_write_byte;
1482 chip->read_buf = atmel_nand_read_buf;
1483 chip->write_buf = atmel_nand_write_buf;
1484 chip->select_chip = atmel_nand_select_chip;
1485 chip->setup_data_interface = atmel_nand_setup_data_interface;
1487 if (!nc->mck || !nc->caps->ops->setup_data_interface)
1488 chip->options |= NAND_KEEP_TIMINGS;
1490 /* Some NANDs require a longer delay than the default one (20us). */
1491 chip->chip_delay = 40;
1493 /* Default to HW ECC if pmecc is available. */
1495 chip->ecc.mode = NAND_ECC_HW;
1498 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1499 struct atmel_nand *nand)
1501 struct atmel_smc_nand_controller *smc_nc;
1504 atmel_nand_init(nc, nand);
1506 smc_nc = to_smc_nand_controller(nand->controller);
1507 if (!smc_nc->ebi_csa_regmap)
1510 /* Attach the CS to the NAND Flash logic. */
1511 for (i = 0; i < nand->numcs; i++)
1512 regmap_update_bits(smc_nc->ebi_csa_regmap,
1513 smc_nc->ebi_csa->offs,
1514 BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1516 if (smc_nc->ebi_csa->nfd0_on_d16)
1517 regmap_update_bits(smc_nc->ebi_csa_regmap,
1518 smc_nc->ebi_csa->offs,
1519 smc_nc->ebi_csa->nfd0_on_d16,
1520 smc_nc->ebi_csa->nfd0_on_d16);
1523 static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1524 struct atmel_nand *nand)
1526 struct nand_chip *chip = &nand->base;
1528 atmel_nand_init(nc, nand);
1530 /* Overload some methods for the HSMC controller. */
1531 chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1532 chip->select_chip = atmel_hsmc_nand_select_chip;
1535 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand)
1537 list_del(&nand->node);
1542 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1546 struct atmel_nand *nand;
1554 /* Count num of nand nodes */
1555 ofnode_for_each_subnode(n, ofnode_get_parent(np))
1558 dev_err(nc->dev, "Missing or invalid reg property\n");
1559 return ERR_PTR(-EINVAL);
1562 nand = devm_kzalloc(nc->dev,
1563 sizeof(struct atmel_nand) +
1564 (numcs * sizeof(struct atmel_nand_cs)),
1567 dev_err(nc->dev, "Failed to allocate NAND object\n");
1568 return ERR_PTR(-ENOMEM);
1571 nand->numcs = numcs;
1573 gpio_request_by_name_nodev(np, "det-gpios", 0, &nand->cdgpio,
1576 for (i = 0; i < numcs; i++) {
1577 ret = ofnode_read_u32(np, "reg", &val);
1579 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1581 return ERR_PTR(ret);
1583 nand->cs[i].id = val;
1585 /* Read base address */
1586 struct resource res;
1588 if (ofnode_read_resource(np, 0, &res)) {
1589 dev_err(nc->dev, "Unable to read resource\n");
1590 return ERR_PTR(-ENOMEM);
1593 faddr = cpu_to_fdt32(val);
1594 base = ofnode_translate_address(np, &faddr);
1595 nand->cs[i].io.virt = (void *)base;
1597 if (!ofnode_read_u32(np, "atmel,rb", &val)) {
1598 if (val > ATMEL_NFC_MAX_RB_ID)
1599 return ERR_PTR(-EINVAL);
1601 nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1602 nand->cs[i].rb.id = val;
1604 gpio_request_by_name_nodev(np, "rb-gpios", 0,
1605 &nand->cs[i].rb.gpio,
1607 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1610 gpio_request_by_name_nodev(np, "cs-gpios", 0,
1611 &nand->cs[i].csgpio,
1615 nand_set_flash_node(&nand->base, np);
1620 static int nand_attach(struct nand_chip *chip)
1622 struct atmel_nand *nand = to_atmel_nand(chip);
1624 if (nand->controller->ops && nand->controller->ops->attach_chip)
1625 return nand->controller->ops->attach_chip(chip);
1630 int atmel_nand_scan(struct mtd_info *mtd, int maxchips)
1634 ret = nand_scan_ident(mtd, maxchips, NULL);
1638 ret = nand_attach(mtd_to_nand(mtd));
1642 ret = nand_scan_tail(mtd);
1647 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1648 struct atmel_nand *nand)
1650 struct nand_chip *chip = &nand->base;
1651 struct mtd_info *mtd = nand_to_mtd(chip);
1654 /* No card inserted, skip this NAND. */
1655 if (dm_gpio_is_valid(&nand->cdgpio) &&
1656 dm_gpio_get_value(&nand->cdgpio)) {
1657 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1661 nc->caps->ops->nand_init(nc, nand);
1663 ret = atmel_nand_scan(mtd, nand->numcs);
1665 dev_err(nc->dev, "NAND scan failed: %d\n", ret);
1669 ret = nand_register(0, mtd);
1671 dev_err(nc->dev, "nand register failed: %d\n", ret);
1675 list_add_tail(&nand->node, &nc->chips);
1681 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1683 struct atmel_nand *nand, *tmp;
1686 list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1687 ret = atmel_nand_controller_remove_nand(nand);
1695 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1703 * Add support for legacy nands
1706 np = nc->dev->node_;
1708 ret = ofnode_read_u32(np, "#address-cells", &val);
1710 dev_err(nc->dev, "missing #address-cells property\n");
1716 ret = ofnode_read_u32(np, "#size-cells", &val);
1718 dev_err(nc->dev, "missing #size-cells property\n");
1724 ofnode_for_each_subnode(nand_np, np) {
1725 struct atmel_nand *nand;
1727 nand = atmel_nand_create(nc, nand_np, reg_cells);
1729 ret = PTR_ERR(nand);
1733 ret = atmel_nand_controller_add_nand(nc, nand);
1741 atmel_nand_controller_remove_nands(nc);
1746 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9260_ebi_csa = {
1747 .offs = AT91SAM9260_MATRIX_EBICSA,
1750 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9261_ebi_csa = {
1751 .offs = AT91SAM9261_MATRIX_EBICSA,
1754 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9263_ebi_csa = {
1755 .offs = AT91SAM9263_MATRIX_EBI0CSA,
1758 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9rl_ebi_csa = {
1759 .offs = AT91SAM9RL_MATRIX_EBICSA,
1762 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9g45_ebi_csa = {
1763 .offs = AT91SAM9G45_MATRIX_EBICSA,
1766 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9n12_ebi_csa = {
1767 .offs = AT91SAM9N12_MATRIX_EBICSA,
1770 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9x5_ebi_csa = {
1771 .offs = AT91SAM9X5_MATRIX_EBICSA,
1774 static const struct atmel_smc_nand_ebi_csa_cfg sam9x60_ebi_csa = {
1775 .offs = AT91_SFR_CCFG_EBICSA,
1776 .nfd0_on_d16 = AT91_SFR_CCFG_NFD0_ON_D16,
1779 static const struct udevice_id atmel_ebi_csa_regmap_of_ids[] = {
1781 .compatible = "atmel,at91sam9260-matrix",
1782 .data = (ulong)&at91sam9260_ebi_csa,
1785 .compatible = "atmel,at91sam9261-matrix",
1786 .data = (ulong)&at91sam9261_ebi_csa,
1789 .compatible = "atmel,at91sam9263-matrix",
1790 .data = (ulong)&at91sam9263_ebi_csa,
1793 .compatible = "atmel,at91sam9rl-matrix",
1794 .data = (ulong)&at91sam9rl_ebi_csa,
1797 .compatible = "atmel,at91sam9g45-matrix",
1798 .data = (ulong)&at91sam9g45_ebi_csa,
1801 .compatible = "atmel,at91sam9n12-matrix",
1802 .data = (ulong)&at91sam9n12_ebi_csa,
1805 .compatible = "atmel,at91sam9x5-matrix",
1806 .data = (ulong)&at91sam9x5_ebi_csa,
1809 .compatible = "microchip,sam9x60-sfr",
1810 .data = (ulong)&sam9x60_ebi_csa,
1815 static int atmel_nand_attach_chip(struct nand_chip *chip)
1817 struct atmel_nand *nand = to_atmel_nand(chip);
1818 struct atmel_nand_controller *nc = to_nand_controller(nand->controller);
1819 struct mtd_info *mtd = nand_to_mtd(chip);
1822 ret = nc->caps->ops->ecc_init(chip);
1826 if (nc->caps->legacy_of_bindings || !ofnode_valid(nc->dev->node_)) {
1828 * We keep the MTD name unchanged to avoid breaking platforms
1829 * where the MTD cmdline parser is used and the bootloader
1830 * has not been updated to use the new naming scheme.
1832 mtd->name = "atmel_nand";
1833 } else if (!mtd->name) {
1835 * If the new bindings are used and the bootloader has not been
1836 * updated to pass a new mtdparts parameter on the cmdline, you
1837 * should define the following property in your nand node:
1839 * label = "atmel_nand";
1841 * This way, mtd->name will be set by the core when
1842 * nand_set_flash_node() is called.
1844 sprintf(mtd->name, "%s:nand.%d", nc->dev->name, nand->cs[0].id);
1850 static const struct nand_controller_ops atmel_nand_controller_ops = {
1851 .attach_chip = atmel_nand_attach_chip,
1855 atmel_nand_controller_init(struct atmel_nand_controller *nc,
1856 struct udevice *dev,
1857 const struct atmel_nand_controller_caps *caps)
1859 struct ofnode_phandle_args args;
1862 nc->base.ops = &atmel_nand_controller_ops;
1863 INIT_LIST_HEAD(&nc->chips);
1867 nc->pmecc = devm_atmel_pmecc_get(dev);
1868 if (IS_ERR(nc->pmecc)) {
1869 ret = PTR_ERR(nc->pmecc);
1870 if (ret != -EPROBE_DEFER)
1871 dev_err(dev, "Could not get PMECC object (err = %d)\n",
1876 /* We do not retrieve the SMC syscon when parsing old DTs. */
1877 if (nc->caps->legacy_of_bindings)
1880 nc->mck = devm_kzalloc(dev, sizeof(nc->mck), GFP_KERNEL);
1884 clk_get_by_index(dev->parent, 0, nc->mck);
1885 if (IS_ERR(nc->mck)) {
1886 dev_err(dev, "Failed to retrieve MCK clk\n");
1887 return PTR_ERR(nc->mck);
1890 ret = ofnode_parse_phandle_with_args(dev->parent->node_,
1891 "atmel,smc", NULL, 0, 0, &args);
1893 dev_err(dev, "Missing or invalid atmel,smc property\n");
1897 nc->smc = syscon_node_to_regmap(args.node);
1898 if (IS_ERR(nc->smc)) {
1899 ret = PTR_ERR(nc->smc);
1900 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
1908 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
1910 struct udevice *dev = nc->base.dev;
1911 struct ofnode_phandle_args args;
1912 const struct udevice_id *match = NULL;
1918 /* We do not retrieve the EBICSA regmap when parsing old DTs. */
1919 if (nc->base.caps->legacy_of_bindings)
1922 ret = ofnode_parse_phandle_with_args(dev->parent->node_,
1923 nc->base.caps->ebi_csa_regmap_name,
1926 dev_err(dev, "Unable to read ebi csa regmap\n");
1930 name = ofnode_get_property(args.node, "compatible", &len);
1932 for (i = 0; i < ARRAY_SIZE(atmel_ebi_csa_regmap_of_ids); i++) {
1933 if (!strcmp(name, atmel_ebi_csa_regmap_of_ids[i].compatible)) {
1934 match = &atmel_ebi_csa_regmap_of_ids[i];
1940 dev_err(dev, "Unable to find ebi csa conf");
1943 nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data;
1945 nc->ebi_csa_regmap = syscon_node_to_regmap(args.node);
1946 if (IS_ERR(nc->ebi_csa_regmap)) {
1947 ret = PTR_ERR(nc->ebi_csa_regmap);
1948 dev_err(dev, "Could not get EBICSA regmap (err = %d)\n", ret);
1953 * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
1954 * add 4 to ->ebi_csa->offs.
1960 static int atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
1962 struct udevice *dev = nc->base.dev;
1963 struct ofnode_phandle_args args;
1968 ret = ofnode_parse_phandle_with_args(dev->parent->node_,
1969 "atmel,smc", NULL, 0, 0, &args);
1971 dev_err(dev, "Missing or invalid atmel,smc property\n");
1975 nc->hsmc_layout = atmel_hsmc_get_reg_layout(args.node);
1976 if (IS_ERR(nc->hsmc_layout)) {
1977 dev_err(dev, "Could not get hsmc layout\n");
1981 /* Enable smc clock */
1982 ret = clk_get_by_index_nodev(args.node, 0, &smc_clk);
1984 dev_err(dev, "Unable to get smc clock (err = %d)", ret);
1988 ret = clk_prepare_enable(&smc_clk);
1992 ret = ofnode_parse_phandle_with_args(dev->node_,
1993 "atmel,nfc-io", NULL, 0, 0, &args);
1995 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
1999 nc->io = syscon_node_to_regmap(args.node);
2000 if (IS_ERR(nc->io)) {
2001 ret = PTR_ERR(nc->io);
2002 dev_err(dev, "Could not get NFC IO regmap\n");
2006 ret = ofnode_parse_phandle_with_args(dev->node_,
2007 "atmel,nfc-sram", NULL, 0, 0, &args);
2009 dev_err(dev, "Missing or invalid atmel,nfc-sram property\n");
2013 ret = ofnode_read_u32(args.node, "reg", &addr);
2015 dev_err(dev, "Could not read reg addr of nfc sram");
2018 nc->sram.virt = (void *)addr;
2024 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2026 struct atmel_hsmc_nand_controller *hsmc_nc;
2029 ret = atmel_nand_controller_remove_nands(nc);
2033 hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2036 clk_disable_unprepare(hsmc_nc->clk);
2037 devm_clk_put(nc->dev, hsmc_nc->clk);
2044 atmel_hsmc_nand_controller_probe(struct udevice *dev,
2045 const struct atmel_nand_controller_caps *caps)
2047 struct atmel_hsmc_nand_controller *nc;
2050 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2054 ret = atmel_nand_controller_init(&nc->base, dev, caps);
2058 ret = atmel_hsmc_nand_controller_init(nc);
2062 /* Make sure all irqs are masked before registering our IRQ handler. */
2063 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2065 /* Initial NFC configuration. */
2066 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2067 ATMEL_HSMC_NFC_CFG_DTO_MAX);
2069 ret = atmel_nand_controller_add_nands(&nc->base);
2076 atmel_hsmc_nand_controller_remove(&nc->base);
2081 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2082 .probe = atmel_hsmc_nand_controller_probe,
2083 .remove = atmel_hsmc_nand_controller_remove,
2084 .ecc_init = atmel_hsmc_nand_ecc_init,
2085 .nand_init = atmel_hsmc_nand_init,
2086 .setup_data_interface = atmel_hsmc_nand_setup_data_interface,
2089 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2091 .ale_offs = BIT(21),
2092 .cle_offs = BIT(22),
2093 .ops = &atmel_hsmc_nc_ops,
2097 atmel_smc_nand_controller_probe(struct udevice *dev,
2098 const struct atmel_nand_controller_caps *caps)
2100 struct atmel_smc_nand_controller *nc;
2103 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2107 ret = atmel_nand_controller_init(&nc->base, dev, caps);
2111 ret = atmel_smc_nand_controller_init(nc);
2115 return atmel_nand_controller_add_nands(&nc->base);
2119 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2123 ret = atmel_nand_controller_remove_nands(nc);
2131 * The SMC reg layout of at91rm9200 is completely different which prevents us
2132 * from re-using atmel_smc_nand_setup_data_interface() for the
2133 * ->setup_data_interface() hook.
2134 * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2135 * ->setup_data_interface() unassigned.
2137 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2138 .probe = atmel_smc_nand_controller_probe,
2139 .remove = atmel_smc_nand_controller_remove,
2140 .ecc_init = atmel_nand_ecc_init,
2141 .nand_init = atmel_smc_nand_init,
2144 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2145 .ale_offs = BIT(21),
2146 .cle_offs = BIT(22),
2147 .ebi_csa_regmap_name = "atmel,matrix",
2148 .ops = &at91rm9200_nc_ops,
2151 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2152 .probe = atmel_smc_nand_controller_probe,
2153 .remove = atmel_smc_nand_controller_remove,
2154 .ecc_init = atmel_nand_ecc_init,
2155 .nand_init = atmel_smc_nand_init,
2156 .setup_data_interface = atmel_smc_nand_setup_data_interface,
2159 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2160 .ale_offs = BIT(21),
2161 .cle_offs = BIT(22),
2162 .ebi_csa_regmap_name = "atmel,matrix",
2163 .ops = &atmel_smc_nc_ops,
2166 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2167 .ale_offs = BIT(22),
2168 .cle_offs = BIT(21),
2169 .ebi_csa_regmap_name = "atmel,matrix",
2170 .ops = &atmel_smc_nc_ops,
2173 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2175 .ale_offs = BIT(21),
2176 .cle_offs = BIT(22),
2177 .ebi_csa_regmap_name = "atmel,matrix",
2178 .ops = &atmel_smc_nc_ops,
2181 static const struct atmel_nand_controller_caps microchip_sam9x60_nc_caps = {
2183 .ale_offs = BIT(21),
2184 .cle_offs = BIT(22),
2185 .ebi_csa_regmap_name = "microchip,sfr",
2186 .ops = &atmel_smc_nc_ops,
2189 /* Only used to parse old bindings. */
2190 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2191 .ale_offs = BIT(21),
2192 .cle_offs = BIT(22),
2193 .ops = &atmel_smc_nc_ops,
2194 .legacy_of_bindings = true,
2197 static const struct udevice_id atmel_nand_controller_of_ids[] = {
2199 .compatible = "atmel,at91rm9200-nand-controller",
2200 .data = (ulong)&atmel_rm9200_nc_caps,
2203 .compatible = "atmel,at91sam9260-nand-controller",
2204 .data = (ulong)&atmel_sam9260_nc_caps,
2207 .compatible = "atmel,at91sam9261-nand-controller",
2208 .data = (ulong)&atmel_sam9261_nc_caps,
2211 .compatible = "atmel,at91sam9g45-nand-controller",
2212 .data = (ulong)&atmel_sam9g45_nc_caps,
2215 .compatible = "atmel,sama5d3-nand-controller",
2216 .data = (ulong)&atmel_sama5_nc_caps,
2219 .compatible = "microchip,sam9x60-nand-controller",
2220 .data = (ulong)µchip_sam9x60_nc_caps,
2222 /* Support for old/deprecated bindings: */
2224 .compatible = "atmel,at91rm9200-nand",
2225 .data = (ulong)&atmel_rm9200_nand_caps,
2228 .compatible = "atmel,sama5d4-nand",
2229 .data = (ulong)&atmel_rm9200_nand_caps,
2232 .compatible = "atmel,sama5d2-nand",
2233 .data = (ulong)&atmel_rm9200_nand_caps,
2238 static int atmel_nand_controller_probe(struct udevice *dev)
2240 const struct atmel_nand_controller_caps *caps;
2241 struct udevice *pmecc_dev;
2243 caps = (struct atmel_nand_controller_caps *)dev_get_driver_data(dev);
2245 printf("Could not retrieve NFC caps\n");
2249 /* Probe pmecc driver */
2250 if (uclass_get_device(UCLASS_MTD, 1, &pmecc_dev)) {
2251 printf("%s: get device fail\n", __func__);
2255 return caps->ops->probe(dev, caps);
2258 static int atmel_nand_controller_remove(struct udevice *dev)
2260 struct atmel_nand_controller *nc;
2262 nc = (struct atmel_nand_controller *)dev_get_driver_data(dev);
2264 return nc->caps->ops->remove(nc);
2267 U_BOOT_DRIVER(atmel_nand_controller) = {
2268 .name = "atmel-nand-controller",
2270 .of_match = atmel_nand_controller_of_ids,
2271 .probe = atmel_nand_controller_probe,
2272 .remove = atmel_nand_controller_remove,
2275 void board_nand_init(void)
2277 struct udevice *dev;
2280 ret = uclass_get_device_by_driver(UCLASS_MTD,
2281 DM_DRIVER_GET(atmel_nand_controller),
2283 if (ret && ret != -ENODEV)
2284 printf("Failed to initialize NAND controller. (error %d)\n",