drivers/i2c/ihs_i2c.c

   1 /*
   2  * (C) Copyright 2013
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <i2c.h>
  10 #ifdef CONFIG_DM_I2C
  11 #include <dm.h>
  12 #include <fpgamap.h>
  13 #include "../misc/gdsys_soc.h"
  14 #else
  15 #include <gdsys_fpga.h>
  16 #endif
  17 #include <asm/unaligned.h>
  18
  19 #ifdef CONFIG_DM_I2C
  20 struct ihs_i2c_priv {
  21         uint speed;
  22         phys_addr_t addr;
  23 };
  24
  25 enum {
  26         REG_INTERRUPT_STATUS = 0x00,
  27         REG_INTERRUPT_ENABLE_CONTROL = 0x02,
  28         REG_WRITE_MAILBOX_EXT = 0x04,
  29         REG_WRITE_MAILBOX = 0x06,
  30         REG_READ_MAILBOX_EXT = 0x08,
  31         REG_READ_MAILBOX = 0x0A,
  32 };
  33
  34 #else /* !CONFIG_DM_I2C */
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #ifdef CONFIG_SYS_I2C_IHS_DUAL
  38
  39 #define I2C_SET_REG(fld, val) \
  40         do { \
  41                 if (I2C_ADAP_HWNR & 0x10) \
  42                         FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
  43                 else \
  44                         FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
  45         } while (0)
  46 #else
  47 #define I2C_SET_REG(fld, val) \
  48                 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
  49 #endif
  50
  51 #ifdef CONFIG_SYS_I2C_IHS_DUAL
  52 #define I2C_GET_REG(fld, val) \
  53         do {                                    \
  54                 if (I2C_ADAP_HWNR & 0x10) \
  55                         FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
  56                 else \
  57                         FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
  58         } while (0)
  59 #else
  60 #define I2C_GET_REG(fld, val) \
  61                 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
  62 #endif
  63 #endif /* CONFIG_DM_I2C */
  64
  65 enum {
  66         I2CINT_ERROR_EV = BIT(13),
  67         I2CINT_TRANSMIT_EV = BIT(14),
  68         I2CINT_RECEIVE_EV = BIT(15),
  69 };
  70
  71 enum {
  72         I2CMB_READ = 0 << 10,
  73         I2CMB_WRITE = 1 << 10,
  74         I2CMB_1BYTE = 0 << 11,
  75         I2CMB_2BYTE = 1 << 11,
  76         I2CMB_DONT_HOLD_BUS = 0 << 13,
  77         I2CMB_HOLD_BUS = 1 << 13,
  78         I2CMB_NATIVE = 2 << 14,
  79 };
  80
  81 enum {
  82         I2COP_WRITE = 0,
  83         I2COP_READ = 1,
  84 };
  85
  86 #ifdef CONFIG_DM_I2C
  87 static int wait_for_int(struct udevice *dev, int read)
  88 #else
  89 static int wait_for_int(bool read)
  90 #endif
  91 {
  92         u16 val;
  93         uint ctr = 0;
  94 #ifdef CONFIG_DM_I2C
  95         struct ihs_i2c_priv *priv = dev_get_priv(dev);
  96         struct udevice *fpga;
  97
  98         gdsys_soc_get_fpga(dev, &fpga);
  99 #endif
 100
 101 #ifdef CONFIG_DM_I2C
 102         fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
 103                      FPGAMAP_SIZE_16);
 104 #else
 105         I2C_GET_REG(interrupt_status, &val);
 106 #endif
 107         /* Wait until error or receive/transmit interrupt was raised */
 108         while (!(val & (I2CINT_ERROR_EV
 109                | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
 110                 udelay(10);
 111                 if (ctr++ > 5000)
 112                         return 1;
 113 #ifdef CONFIG_DM_I2C
 114                 fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
 115                              FPGAMAP_SIZE_16);
 116 #else
 117                 I2C_GET_REG(interrupt_status, &val);
 118 #endif
 119         }
 120
 121         return (val & I2CINT_ERROR_EV) ? 1 : 0;
 122 }
 123
 124 #ifdef CONFIG_DM_I2C
 125 static int ihs_i2c_transfer(struct udevice *dev, uchar chip,
 126                             uchar *buffer, int len, int read, bool is_last)
 127 #else
 128 static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
 129                             bool is_last)
 130 #endif
 131 {
 132         u16 val;
 133         u16 data;
 134 #ifdef CONFIG_DM_I2C
 135         struct ihs_i2c_priv *priv = dev_get_priv(dev);
 136         struct udevice *fpga;
 137
 138         gdsys_soc_get_fpga(dev, &fpga);
 139 #endif
 140
 141         /* Clear interrupt status */
 142         data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
 143 #ifdef CONFIG_DM_I2C
 144         fpgamap_write(fpga, priv->addr + REG_INTERRUPT_STATUS, &data,
 145                       FPGAMAP_SIZE_16);
 146         fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
 147                      FPGAMAP_SIZE_16);
 148 #else
 149         I2C_SET_REG(interrupt_status, data);
 150         I2C_GET_REG(interrupt_status, &val);
 151 #endif
 152
 153         /* If we want to write and have data, write the bytes to the mailbox */
 154         if (!read && len) {
 155                 val = buffer[0];
 156
 157                 if (len > 1)
 158                         val |= buffer[1] << 8;
 159 #ifdef CONFIG_DM_I2C
 160                 fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX_EXT, &val,
 161                               FPGAMAP_SIZE_16);
 162 #else
 163                 I2C_SET_REG(write_mailbox_ext, val);
 164 #endif
 165         }
 166
 167         data = I2CMB_NATIVE
 168                | (read ? 0 : I2CMB_WRITE)
 169                | (chip << 1)
 170                | ((len > 1) ? I2CMB_2BYTE : 0)
 171                | (is_last ? 0 : I2CMB_HOLD_BUS);
 172
 173 #ifdef CONFIG_DM_I2C
 174         fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX, &data,
 175                       FPGAMAP_SIZE_16);
 176 #else
 177         I2C_SET_REG(write_mailbox, data);
 178 #endif
 179
 180 #ifdef CONFIG_DM_I2C
 181         if (wait_for_int(dev, read))
 182 #else
 183         if (wait_for_int(read))
 184 #endif
 185                 return 1;
 186
 187         /* If we want to read, get the bytes from the mailbox */
 188         if (read) {
 189 #ifdef CONFIG_DM_I2C
 190                 fpgamap_read(fpga, priv->addr + REG_READ_MAILBOX_EXT, &val,
 191                              FPGAMAP_SIZE_16);
 192 #else
 193                 I2C_GET_REG(read_mailbox_ext, &val);
 194 #endif
 195                 buffer[0] = val & 0xff;
 196                 if (len > 1)
 197                         buffer[1] = val >> 8;
 198         }
 199
 200         return 0;
 201 }
 202
 203 #ifdef CONFIG_DM_I2C
 204 static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read)
 205 #else
 206 static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
 207                                int read)
 208 #endif
 209 {
 210         while (len) {
 211                 int transfer = min(len, 2);
 212                 bool is_last = len <= transfer;
 213
 214 #ifdef CONFIG_DM_I2C
 215                 if (ihs_i2c_transfer(dev, chip, data, transfer, read,
 216                                      hold_bus ? false : is_last))
 217                         return 1;
 218 #else
 219                 if (ihs_i2c_transfer(chip, data, transfer, read,
 220                                      hold_bus ? false : is_last))
 221                         return 1;
 222 #endif
 223
 224                 data += transfer;
 225                 len -= transfer;
 226         }
 227
 228         return 0;
 229 }
 230
 231 #ifdef CONFIG_DM_I2C
 232 static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen,
 233                            bool hold_bus)
 234 #else
 235 static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus)
 236 #endif
 237 {
 238 #ifdef CONFIG_DM_I2C
 239         return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE);
 240 #else
 241         return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE);
 242 #endif
 243 }
 244
 245 #ifdef CONFIG_DM_I2C
 246 static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr,
 247                           int alen, uchar *buffer, int len, int read)
 248 #else
 249 static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
 250                           int alen, uchar *buffer, int len, int read)
 251 #endif
 252 {
 253         /* Don't hold the bus if length of data to send/receive is zero */
 254 #ifdef CONFIG_DM_I2C
 255         if (len <= 0 || ihs_i2c_address(dev, chip, addr, alen, len))
 256                 return 1;
 257 #else
 258         if (len <= 0 || ihs_i2c_address(chip, addr, alen, len))
 259                 return 1;
 260 #endif
 261
 262 #ifdef CONFIG_DM_I2C
 263         return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
 264 #else
 265         return ihs_i2c_send_buffer(chip, buffer, len, false, read);
 266 #endif
 267 }
 268
 269 #ifdef CONFIG_DM_I2C
 270
 271 int ihs_i2c_probe(struct udevice *bus)
 272 {
 273         struct ihs_i2c_priv *priv = dev_get_priv(bus);
 274         int addr;
 275
 276         addr = dev_read_u32_default(bus, "reg", -1);
 277
 278         priv->addr = addr;
 279
 280         return 0;
 281 }
 282
 283 static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed)
 284 {
 285         struct ihs_i2c_priv *priv = dev_get_priv(bus);
 286
 287         if (speed != priv->speed && priv->speed != 0)
 288                 return 1;
 289
 290         priv->speed = speed;
 291
 292         return 0;
 293 }
 294
 295 static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
 296 {
 297         struct i2c_msg *dmsg, *omsg, dummy;
 298
 299         memset(&dummy, 0, sizeof(struct i2c_msg));
 300
 301         /* We expect either two messages (one with an offset and one with the
 302          * actucal data) or one message (just data)
 303          */
 304         if (nmsgs > 2 || nmsgs == 0) {
 305                 debug("%s: Only one or two messages are supported.", __func__);
 306                 return -1;
 307         }
 308
 309         omsg = nmsgs == 1 ? &dummy : msg;
 310         dmsg = nmsgs == 1 ? msg : msg + 1;
 311
 312         if (dmsg->flags & I2C_M_RD)
 313                 return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
 314                                       omsg->len, dmsg->buf, dmsg->len,
 315                                       I2COP_READ);
 316         else
 317                 return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
 318                                       omsg->len, dmsg->buf, dmsg->len,
 319                                       I2COP_WRITE);
 320 }
 321
 322 static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
 323                               u32 chip_flags)
 324 {
 325         uchar buffer[2];
 326
 327         if (ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true))
 328                 return 1;
 329
 330         return 0;
 331 }
 332
 333 static const struct dm_i2c_ops ihs_i2c_ops = {
 334         .xfer           = ihs_i2c_xfer,
 335         .probe_chip     = ihs_i2c_probe_chip,
 336         .set_bus_speed  = ihs_i2c_set_bus_speed,
 337 };
 338
 339 static const struct udevice_id ihs_i2c_ids[] = {
 340         { .compatible = "gdsys,ihs_i2cmaster", },
 341         { /* sentinel */ }
 342 };
 343
 344 U_BOOT_DRIVER(i2c_ihs) = {
 345         .name = "i2c_ihs",
 346         .id = UCLASS_I2C,
 347         .of_match = ihs_i2c_ids,
 348         .probe = ihs_i2c_probe,
 349         .priv_auto_alloc_size = sizeof(struct ihs_i2c_priv),
 350         .ops = &ihs_i2c_ops,
 351 };
 352
 353 #else /* CONFIG_DM_I2C */
 354
 355 static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 356 {
 357 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 358         /*
 359          * Call board specific i2c bus reset routine before accessing the
 360          * environment, which might be in a chip on that bus. For details
 361          * about this problem see doc/I2C_Edge_Conditions.
 362          */
 363         i2c_init_board();
 364 #endif
 365 }
 366
 367 static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
 368 {
 369         uchar buffer[2];
 370
 371         if (ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true))
 372                 return 1;
 373
 374         return 0;
 375 }
 376
 377 static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 378                         int alen, uchar *buffer, int len)
 379 {
 380         u8 addr_bytes[4];
 381
 382         put_unaligned_le32(addr, addr_bytes);
 383
 384         return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
 385                               I2COP_READ);
 386 }
 387
 388 static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 389                          int alen, uchar *buffer, int len)
 390 {
 391         u8 addr_bytes[4];
 392
 393         put_unaligned_le32(addr, addr_bytes);
 394
 395         return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
 396                               I2COP_WRITE);
 397 }
 398
 399 static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
 400                                           unsigned int speed)
 401 {
 402         if (speed != adap->speed)
 403                 return 1;
 404         return speed;
 405 }
 406
 407 /*
 408  * Register IHS i2c adapters
 409  */
 410 #ifdef CONFIG_SYS_I2C_IHS_CH0
 411 U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
 412                          ihs_i2c_read, ihs_i2c_write,
 413                          ihs_i2c_set_bus_speed,
 414                          CONFIG_SYS_I2C_IHS_SPEED_0,
 415                          CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
 416 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 417 U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
 418                          ihs_i2c_read, ihs_i2c_write,
 419                          ihs_i2c_set_bus_speed,
 420                          CONFIG_SYS_I2C_IHS_SPEED_0_1,
 421                          CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
 422 #endif
 423 #endif
 424 #ifdef CONFIG_SYS_I2C_IHS_CH1
 425 U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
 426                          ihs_i2c_read, ihs_i2c_write,
 427                          ihs_i2c_set_bus_speed,
 428                          CONFIG_SYS_I2C_IHS_SPEED_1,
 429                          CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
 430 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 431 U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
 432                          ihs_i2c_read, ihs_i2c_write,
 433                          ihs_i2c_set_bus_speed,
 434                          CONFIG_SYS_I2C_IHS_SPEED_1_1,
 435                          CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
 436 #endif
 437 #endif
 438 #ifdef CONFIG_SYS_I2C_IHS_CH2
 439 U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
 440                          ihs_i2c_read, ihs_i2c_write,
 441                          ihs_i2c_set_bus_speed,
 442                          CONFIG_SYS_I2C_IHS_SPEED_2,
 443                          CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
 444 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 445 U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
 446                          ihs_i2c_read, ihs_i2c_write,
 447                          ihs_i2c_set_bus_speed,
 448                          CONFIG_SYS_I2C_IHS_SPEED_2_1,
 449                          CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
 450 #endif
 451 #endif
 452 #ifdef CONFIG_SYS_I2C_IHS_CH3
 453 U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
 454                          ihs_i2c_read, ihs_i2c_write,
 455                          ihs_i2c_set_bus_speed,
 456                          CONFIG_SYS_I2C_IHS_SPEED_3,
 457                          CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
 458 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 459 U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
 460                          ihs_i2c_read, ihs_i2c_write,
 461                          ihs_i2c_set_bus_speed,
 462                          CONFIG_SYS_I2C_IHS_SPEED_3_1,
 463                          CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
 464 #endif
 465 #endif
 466 #endif /* CONFIG_DM_I2C */