drivers/i2c/designware_i2c.c

   1 /*
   2  * (C) Copyright 2009
   3  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <i2c.h>
  11 #include <pci.h>
  12 #include <reset.h>
  13 #include <asm/io.h>
  14 #include "designware_i2c.h"
  15
  16 struct dw_scl_sda_cfg {
  17         u32 ss_hcnt;
  18         u32 fs_hcnt;
  19         u32 ss_lcnt;
  20         u32 fs_lcnt;
  21         u32 sda_hold;
  22 };
  23
  24 #ifdef CONFIG_X86
  25 /* BayTrail HCNT/LCNT/SDA hold time */
  26 static struct dw_scl_sda_cfg byt_config = {
  27         .ss_hcnt = 0x200,
  28         .fs_hcnt = 0x55,
  29         .ss_lcnt = 0x200,
  30         .fs_lcnt = 0x99,
  31         .sda_hold = 0x6,
  32 };
  33 #endif
  34
  35 struct dw_i2c {
  36         struct i2c_regs *regs;
  37         struct dw_scl_sda_cfg *scl_sda_cfg;
  38         struct reset_ctl reset_ctl;
  39 };
  40
  41 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  42 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  43 {
  44         u32 ena = enable ? IC_ENABLE_0B : 0;
  45
  46         writel(ena, &i2c_base->ic_enable);
  47 }
  48 #else
  49 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  50 {
  51         u32 ena = enable ? IC_ENABLE_0B : 0;
  52         int timeout = 100;
  53
  54         do {
  55                 writel(ena, &i2c_base->ic_enable);
  56                 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  57                         return;
  58
  59                 /*
  60                  * Wait 10 times the signaling period of the highest I2C
  61                  * transfer supported by the driver (for 400KHz this is
  62                  * 25us) as described in the DesignWare I2C databook.
  63                  */
  64                 udelay(25);
  65         } while (timeout--);
  66
  67         printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  68 }
  69 #endif
  70
  71 /*
  72  * i2c_set_bus_speed - Set the i2c speed
  73  * @speed:      required i2c speed
  74  *
  75  * Set the i2c speed.
  76  */
  77 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
  78                                            struct dw_scl_sda_cfg *scl_sda_cfg,
  79                                            unsigned int speed)
  80 {
  81         unsigned int cntl;
  82         unsigned int hcnt, lcnt;
  83         int i2c_spd;
  84
  85         if (speed >= I2C_MAX_SPEED)
  86                 i2c_spd = IC_SPEED_MODE_MAX;
  87         else if (speed >= I2C_FAST_SPEED)
  88                 i2c_spd = IC_SPEED_MODE_FAST;
  89         else
  90                 i2c_spd = IC_SPEED_MODE_STANDARD;
  91
  92         /* to set speed cltr must be disabled */
  93         dw_i2c_enable(i2c_base, false);
  94
  95         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
  96
  97         switch (i2c_spd) {
  98 #ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
  99         case IC_SPEED_MODE_MAX:
 100                 cntl |= IC_CON_SPD_SS;
 101                 if (scl_sda_cfg) {
 102                         hcnt = scl_sda_cfg->fs_hcnt;
 103                         lcnt = scl_sda_cfg->fs_lcnt;
 104                 } else {
 105                         hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
 106                         lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
 107                 }
 108                 writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
 109                 writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
 110                 break;
 111 #endif
 112
 113         case IC_SPEED_MODE_STANDARD:
 114                 cntl |= IC_CON_SPD_SS;
 115                 if (scl_sda_cfg) {
 116                         hcnt = scl_sda_cfg->ss_hcnt;
 117                         lcnt = scl_sda_cfg->ss_lcnt;
 118                 } else {
 119                         hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
 120                         lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
 121                 }
 122                 writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
 123                 writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
 124                 break;
 125
 126         case IC_SPEED_MODE_FAST:
 127         default:
 128                 cntl |= IC_CON_SPD_FS;
 129                 if (scl_sda_cfg) {
 130                         hcnt = scl_sda_cfg->fs_hcnt;
 131                         lcnt = scl_sda_cfg->fs_lcnt;
 132                 } else {
 133                         hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
 134                         lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
 135                 }
 136                 writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
 137                 writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
 138                 break;
 139         }
 140
 141         writel(cntl, &i2c_base->ic_con);
 142
 143         /* Configure SDA Hold Time if required */
 144         if (scl_sda_cfg)
 145                 writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
 146
 147         /* Enable back i2c now speed set */
 148         dw_i2c_enable(i2c_base, true);
 149
 150         return 0;
 151 }
 152
 153 /*
 154  * i2c_setaddress - Sets the target slave address
 155  * @i2c_addr:   target i2c address
 156  *
 157  * Sets the target slave address.
 158  */
 159 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
 160 {
 161         /* Disable i2c */
 162         dw_i2c_enable(i2c_base, false);
 163
 164         writel(i2c_addr, &i2c_base->ic_tar);
 165
 166         /* Enable i2c */
 167         dw_i2c_enable(i2c_base, true);
 168 }
 169
 170 /*
 171  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 172  *
 173  * Flushes the i2c RX FIFO
 174  */
 175 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
 176 {
 177         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 178                 readl(&i2c_base->ic_cmd_data);
 179 }
 180
 181 /*
 182  * i2c_wait_for_bb - Waits for bus busy
 183  *
 184  * Waits for bus busy
 185  */
 186 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
 187 {
 188         unsigned long start_time_bb = get_timer(0);
 189
 190         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
 191                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 192
 193                 /* Evaluate timeout */
 194                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
 195                         return 1;
 196         }
 197
 198         return 0;
 199 }
 200
 201 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
 202                          int alen)
 203 {
 204         if (i2c_wait_for_bb(i2c_base))
 205                 return 1;
 206
 207         i2c_setaddress(i2c_base, chip);
 208         while (alen) {
 209                 alen--;
 210                 /* high byte address going out first */
 211                 writel((addr >> (alen * 8)) & 0xff,
 212                        &i2c_base->ic_cmd_data);
 213         }
 214         return 0;
 215 }
 216
 217 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
 218 {
 219         ulong start_stop_det = get_timer(0);
 220
 221         while (1) {
 222                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
 223                         readl(&i2c_base->ic_clr_stop_det);
 224                         break;
 225                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 226                         break;
 227                 }
 228         }
 229
 230         if (i2c_wait_for_bb(i2c_base)) {
 231                 printf("Timed out waiting for bus\n");
 232                 return 1;
 233         }
 234
 235         i2c_flush_rxfifo(i2c_base);
 236
 237         return 0;
 238 }
 239
 240 /*
 241  * i2c_read - Read from i2c memory
 242  * @chip:       target i2c address
 243  * @addr:       address to read from
 244  * @alen:
 245  * @buffer:     buffer for read data
 246  * @len:        no of bytes to be read
 247  *
 248  * Read from i2c memory.
 249  */
 250 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
 251                          int alen, u8 *buffer, int len)
 252 {
 253         unsigned long start_time_rx;
 254         unsigned int active = 0;
 255
 256 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 257         /*
 258          * EEPROM chips that implement "address overflow" are ones
 259          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 260          * address and the extra bits end up in the "chip address"
 261          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 262          * four 256 byte chips.
 263          *
 264          * Note that we consider the length of the address field to
 265          * still be one byte because the extra address bits are
 266          * hidden in the chip address.
 267          */
 268         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 269         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 270
 271         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 272               addr);
 273 #endif
 274
 275         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 276                 return 1;
 277
 278         start_time_rx = get_timer(0);
 279         while (len) {
 280                 if (!active) {
 281                         /*
 282                          * Avoid writing to ic_cmd_data multiple times
 283                          * in case this loop spins too quickly and the
 284                          * ic_status RFNE bit isn't set after the first
 285                          * write. Subsequent writes to ic_cmd_data can
 286                          * trigger spurious i2c transfer.
 287                          */
 288                         if (len == 1)
 289                                 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 290                         else
 291                                 writel(IC_CMD, &i2c_base->ic_cmd_data);
 292                         active = 1;
 293                 }
 294
 295                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
 296                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 297                         len--;
 298                         start_time_rx = get_timer(0);
 299                         active = 0;
 300                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
 301                         return 1;
 302                 }
 303         }
 304
 305         return i2c_xfer_finish(i2c_base);
 306 }
 307
 308 /*
 309  * i2c_write - Write to i2c memory
 310  * @chip:       target i2c address
 311  * @addr:       address to read from
 312  * @alen:
 313  * @buffer:     buffer for read data
 314  * @len:        no of bytes to be read
 315  *
 316  * Write to i2c memory.
 317  */
 318 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
 319                           int alen, u8 *buffer, int len)
 320 {
 321         int nb = len;
 322         unsigned long start_time_tx;
 323
 324 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 325         /*
 326          * EEPROM chips that implement "address overflow" are ones
 327          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 328          * address and the extra bits end up in the "chip address"
 329          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 330          * four 256 byte chips.
 331          *
 332          * Note that we consider the length of the address field to
 333          * still be one byte because the extra address bits are
 334          * hidden in the chip address.
 335          */
 336         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 337         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 338
 339         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 340               addr);
 341 #endif
 342
 343         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 344                 return 1;
 345
 346         start_time_tx = get_timer(0);
 347         while (len) {
 348                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
 349                         if (--len == 0) {
 350                                 writel(*buffer | IC_STOP,
 351                                        &i2c_base->ic_cmd_data);
 352                         } else {
 353                                 writel(*buffer, &i2c_base->ic_cmd_data);
 354                         }
 355                         buffer++;
 356                         start_time_tx = get_timer(0);
 357
 358                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
 359                                 printf("Timed out. i2c write Failed\n");
 360                                 return 1;
 361                 }
 362         }
 363
 364         return i2c_xfer_finish(i2c_base);
 365 }
 366
 367 /*
 368  * __dw_i2c_init - Init function
 369  * @speed:      required i2c speed
 370  * @slaveaddr:  slave address for the device
 371  *
 372  * Initialization function.
 373  */
 374 static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
 375 {
 376         /* Disable i2c */
 377         dw_i2c_enable(i2c_base, false);
 378
 379         writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
 380                &i2c_base->ic_con);
 381         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
 382         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 383         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 384 #ifndef CONFIG_DM_I2C
 385         __dw_i2c_set_bus_speed(i2c_base, NULL, speed);
 386         writel(slaveaddr, &i2c_base->ic_sar);
 387 #endif
 388
 389         /* Enable i2c */
 390         dw_i2c_enable(i2c_base, true);
 391 }
 392
 393 #ifndef CONFIG_DM_I2C
 394 /*
 395  * The legacy I2C functions. These need to get removed once
 396  * all users of this driver are converted to DM.
 397  */
 398 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 399 {
 400         switch (adap->hwadapnr) {
 401 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 402         case 3:
 403                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
 404 #endif
 405 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 406         case 2:
 407                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
 408 #endif
 409 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 410         case 1:
 411                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
 412 #endif
 413         case 0:
 414                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
 415         default:
 416                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
 417         }
 418
 419         return NULL;
 420 }
 421
 422 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 423                                          unsigned int speed)
 424 {
 425         adap->speed = speed;
 426         return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
 427 }
 428
 429 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 430 {
 431         __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
 432 }
 433
 434 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 435                        int alen, u8 *buffer, int len)
 436 {
 437         return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
 438 }
 439
 440 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 441                         int alen, u8 *buffer, int len)
 442 {
 443         return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 444 }
 445
 446 /* dw_i2c_probe - Probe the i2c chip */
 447 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 448 {
 449         struct i2c_regs *i2c_base = i2c_get_base(adap);
 450         u32 tmp;
 451         int ret;
 452
 453         /*
 454          * Try to read the first location of the chip.
 455          */
 456         ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
 457         if (ret)
 458                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 459
 460         return ret;
 461 }
 462
 463 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 464                          dw_i2c_write, dw_i2c_set_bus_speed,
 465                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 466
 467 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 468 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 469                          dw_i2c_write, dw_i2c_set_bus_speed,
 470                          CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
 471 #endif
 472
 473 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 474 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 475                          dw_i2c_write, dw_i2c_set_bus_speed,
 476                          CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
 477 #endif
 478
 479 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 480 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 481                          dw_i2c_write, dw_i2c_set_bus_speed,
 482                          CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 483 #endif
 484
 485 #else /* CONFIG_DM_I2C */
 486 /* The DM I2C functions */
 487
 488 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 489                                int nmsgs)
 490 {
 491         struct dw_i2c *i2c = dev_get_priv(bus);
 492         int ret;
 493
 494         debug("i2c_xfer: %d messages\n", nmsgs);
 495         for (; nmsgs > 0; nmsgs--, msg++) {
 496                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 497                 if (msg->flags & I2C_M_RD) {
 498                         ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
 499                                             msg->buf, msg->len);
 500                 } else {
 501                         ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
 502                                              msg->buf, msg->len);
 503                 }
 504                 if (ret) {
 505                         debug("i2c_write: error sending\n");
 506                         return -EREMOTEIO;
 507                 }
 508         }
 509
 510         return 0;
 511 }
 512
 513 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 514 {
 515         struct dw_i2c *i2c = dev_get_priv(bus);
 516
 517         return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
 518 }
 519
 520 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 521                                      uint chip_flags)
 522 {
 523         struct dw_i2c *i2c = dev_get_priv(bus);
 524         struct i2c_regs *i2c_base = i2c->regs;
 525         u32 tmp;
 526         int ret;
 527
 528         /* Try to read the first location of the chip */
 529         ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
 530         if (ret)
 531                 __dw_i2c_init(i2c_base, 0, 0);
 532
 533         return ret;
 534 }
 535
 536 static int designware_i2c_probe(struct udevice *bus)
 537 {
 538         struct dw_i2c *priv = dev_get_priv(bus);
 539         int ret;
 540
 541         if (device_is_on_pci_bus(bus)) {
 542 #ifdef CONFIG_DM_PCI
 543                 /* Save base address from PCI BAR */
 544                 priv->regs = (struct i2c_regs *)
 545                         dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
 546 #ifdef CONFIG_X86
 547                 /* Use BayTrail specific timing values */
 548                 priv->scl_sda_cfg = &byt_config;
 549 #endif
 550 #endif
 551         } else {
 552                 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
 553         }
 554
 555         ret = reset_get_by_name(bus, "i2c", &priv->reset_ctl);
 556         if (ret)
 557                 pr_info("reset_get_by_name() failed: %d\n", ret);
 558
 559         if (&priv->reset_ctl)
 560                 reset_deassert(&priv->reset_ctl);
 561
 562         __dw_i2c_init(priv->regs, 0, 0);
 563
 564         return 0;
 565 }
 566
 567 static int designware_i2c_bind(struct udevice *dev)
 568 {
 569         static int num_cards;
 570         char name[20];
 571
 572         /* Create a unique device name for PCI type devices */
 573         if (device_is_on_pci_bus(dev)) {
 574                 /*
 575                  * ToDo:
 576                  * Setting req_seq in the driver is probably not recommended.
 577                  * But without a DT alias the number is not configured. And
 578                  * using this driver is impossible for PCIe I2C devices.
 579                  * This can be removed, once a better (correct) way for this
 580                  * is found and implemented.
 581                  */
 582                 dev->req_seq = num_cards;
 583                 sprintf(name, "i2c_designware#%u", num_cards++);
 584                 device_set_name(dev, name);
 585         }
 586
 587         return 0;
 588 }
 589
 590 static const struct dm_i2c_ops designware_i2c_ops = {
 591         .xfer           = designware_i2c_xfer,
 592         .probe_chip     = designware_i2c_probe_chip,
 593         .set_bus_speed  = designware_i2c_set_bus_speed,
 594 };
 595
 596 static const struct udevice_id designware_i2c_ids[] = {
 597         { .compatible = "snps,designware-i2c" },
 598         { }
 599 };
 600
 601 U_BOOT_DRIVER(i2c_designware) = {
 602         .name   = "i2c_designware",
 603         .id     = UCLASS_I2C,
 604         .of_match = designware_i2c_ids,
 605         .bind   = designware_i2c_bind,
 606         .probe  = designware_i2c_probe,
 607         .priv_auto_alloc_size = sizeof(struct dw_i2c),
 608         .ops    = &designware_i2c_ops,
 609 };
 610
 611 #ifdef CONFIG_X86
 612 static struct pci_device_id designware_pci_supported[] = {
 613         /* Intel BayTrail has 7 I2C controller located on the PCI bus */
 614         { PCI_VDEVICE(INTEL, 0x0f41) },
 615         { PCI_VDEVICE(INTEL, 0x0f42) },
 616         { PCI_VDEVICE(INTEL, 0x0f43) },
 617         { PCI_VDEVICE(INTEL, 0x0f44) },
 618         { PCI_VDEVICE(INTEL, 0x0f45) },
 619         { PCI_VDEVICE(INTEL, 0x0f46) },
 620         { PCI_VDEVICE(INTEL, 0x0f47) },
 621         {},
 622 };
 623
 624 U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
 625 #endif
 626
 627 #endif /* CONFIG_DM_I2C */