drivers/fpga/socfpga_arria10.c

   1 /*
   2  * Copyright (C) 2017 Intel Corporation <www.intel.com>
   3  *
   4  * SPDX-License-Identifier:    GPL-2.0
   5  */
   6
   7 #include <asm/io.h>
   8 #include <asm/arch/fpga_manager.h>
   9 #include <asm/arch/reset_manager.h>
  10 #include <asm/arch/system_manager.h>
  11 #include <asm/arch/sdram.h>
  12 #include <asm/arch/misc.h>
  13 #include <altera.h>
  14 #include <common.h>
  15 #include <errno.h>
  16 #include <wait_bit.h>
  17 #include <watchdog.h>
  18
  19 #define CFGWDTH_32      1
  20 #define MIN_BITSTREAM_SIZECHECK 230
  21 #define ENCRYPTION_OFFSET       69
  22 #define COMPRESSION_OFFSET      229
  23 #define FPGA_TIMEOUT_MSEC       1000  /* timeout in ms */
  24 #define FPGA_TIMEOUT_CNT        0x1000000
  25
  26 static const struct socfpga_fpga_manager *fpga_manager_base =
  27                 (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
  28
  29 static const struct socfpga_system_manager *system_manager_base =
  30                 (void *)SOCFPGA_SYSMGR_ADDRESS;
  31
  32 static void fpgamgr_set_cd_ratio(unsigned long ratio);
  33
  34 static uint32_t fpgamgr_get_msel(void)
  35 {
  36         u32 reg;
  37
  38         reg = readl(&fpga_manager_base->imgcfg_stat);
  39         reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
  40                 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
  41
  42         return reg;
  43 }
  44
  45 static void fpgamgr_set_cfgwdth(int width)
  46 {
  47         if (width)
  48                 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  49                         ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  50         else
  51                 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  52                         ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  53 }
  54
  55 int is_fpgamgr_user_mode(void)
  56 {
  57         return (readl(&fpga_manager_base->imgcfg_stat) &
  58                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
  59 }
  60
  61 static int wait_for_user_mode(void)
  62 {
  63         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
  64                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
  65                 1, FPGA_TIMEOUT_MSEC, false);
  66 }
  67
  68 static int is_fpgamgr_early_user_mode(void)
  69 {
  70         return (readl(&fpga_manager_base->imgcfg_stat) &
  71                 ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
  72 }
  73
  74 int fpgamgr_wait_early_user_mode(void)
  75 {
  76         u32 sync_data = 0xffffffff;
  77         u32 i = 0;
  78         unsigned start = get_timer(0);
  79         unsigned long cd_ratio;
  80
  81         /* Getting existing CDRATIO */
  82         cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
  83                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
  84                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
  85
  86         /* Using CDRATIO_X1 for better compatibility */
  87         fpgamgr_set_cd_ratio(CDRATIO_x1);
  88
  89         while (!is_fpgamgr_early_user_mode()) {
  90                 if (get_timer(start) > FPGA_TIMEOUT_MSEC)
  91                         return -ETIMEDOUT;
  92                 fpgamgr_program_write((const long unsigned int *)&sync_data,
  93                                 sizeof(sync_data));
  94                 udelay(FPGA_TIMEOUT_MSEC);
  95                 i++;
  96         }
  97
  98         debug("Additional %i sync word needed\n", i);
  99
 100         /* restoring original CDRATIO */
 101         fpgamgr_set_cd_ratio(cd_ratio);
 102
 103         return 0;
 104 }
 105
 106 /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
 107 static int wait_for_nconfig_pin_and_nstatus_pin(void)
 108 {
 109         unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
 110                                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
 111
 112         /*
 113          * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
 114          * de-asserted, timeout at 1000ms
 115          */
 116         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
 117                                  true, FPGA_TIMEOUT_MSEC, false);
 118 }
 119
 120 static int wait_for_f2s_nstatus_pin(unsigned long value)
 121 {
 122         /* Poll until f2s to specific value, timeout at 1000ms */
 123         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
 124                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
 125                 value, FPGA_TIMEOUT_MSEC, false);
 126 }
 127
 128 /* set CD ratio */
 129 static void fpgamgr_set_cd_ratio(unsigned long ratio)
 130 {
 131         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 132                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
 133
 134         setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 135                 (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
 136                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
 137 }
 138
 139 /* get the MSEL value, verify we are set for FPP configuration mode */
 140 static int fpgamgr_verify_msel(void)
 141 {
 142         u32 msel = fpgamgr_get_msel();
 143
 144         if (msel & ~BIT(0)) {
 145                 printf("Fail: read msel=%d\n", msel);
 146                 return -EPERM;
 147         }
 148
 149         return 0;
 150 }
 151
 152 /*
 153  * Write cdratio and cdwidth based on whether the bitstream is compressed
 154  * and/or encoded
 155  */
 156 static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
 157                                        size_t rbf_size)
 158 {
 159         unsigned int cd_ratio;
 160         bool encrypt, compress;
 161
 162         /*
 163          * According to the bitstream specification,
 164          * both encryption and compression status are
 165          * in location before offset 230 of the buffer.
 166          */
 167         if (rbf_size < MIN_BITSTREAM_SIZECHECK)
 168                 return -EINVAL;
 169
 170         encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
 171         encrypt = encrypt != 0;
 172
 173         compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
 174         compress = !compress;
 175
 176         debug("header word %d = %08x\n", 69, rbf_data[69]);
 177         debug("header word %d = %08x\n", 229, rbf_data[229]);
 178         debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
 179
 180         /*
 181          * from the register map description of cdratio in imgcfg_ctrl_02:
 182          *  Normal Configuration    : 32bit Passive Parallel
 183          *  Partial Reconfiguration : 16bit Passive Parallel
 184          */
 185
 186         /*
 187          * cd ratio is dependent on cfg width and whether the bitstream
 188          * is encrypted and/or compressed.
 189          *
 190          * | width | encr. | compr. | cd ratio |
 191          * |  16   |   0   |   0    |     1    |
 192          * |  16   |   0   |   1    |     4    |
 193          * |  16   |   1   |   0    |     2    |
 194          * |  16   |   1   |   1    |     4    |
 195          * |  32   |   0   |   0    |     1    |
 196          * |  32   |   0   |   1    |     8    |
 197          * |  32   |   1   |   0    |     4    |
 198          * |  32   |   1   |   1    |     8    |
 199          */
 200         if (!compress && !encrypt) {
 201                 cd_ratio = CDRATIO_x1;
 202         } else {
 203                 if (compress)
 204                         cd_ratio = CDRATIO_x4;
 205                 else
 206                         cd_ratio = CDRATIO_x2;
 207
 208                 /* if 32 bit, double the cd ratio (so register
 209                    field setting is incremented) */
 210                 if (cfg_width == CFGWDTH_32)
 211                         cd_ratio += 1;
 212         }
 213
 214         fpgamgr_set_cfgwdth(cfg_width);
 215         fpgamgr_set_cd_ratio(cd_ratio);
 216
 217         return 0;
 218 }
 219
 220 static int fpgamgr_reset(void)
 221 {
 222         unsigned long reg;
 223
 224         /* S2F_NCONFIG = 0 */
 225         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 226                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 227
 228         /* Wait for f2s_nstatus == 0 */
 229         if (wait_for_f2s_nstatus_pin(0))
 230                 return -ETIME;
 231
 232         /* S2F_NCONFIG = 1 */
 233         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 234                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 235
 236         /* Wait for f2s_nstatus == 1 */
 237         if (wait_for_f2s_nstatus_pin(1))
 238                 return -ETIME;
 239
 240         /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
 241         reg = readl(&fpga_manager_base->imgcfg_stat);
 242         if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
 243                 return -EPERM;
 244
 245         if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
 246                 return -EPERM;
 247
 248         return 0;
 249 }
 250
 251 /* Start the FPGA programming by initialize the FPGA Manager */
 252 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
 253 {
 254         int ret;
 255
 256         /* Step 1 */
 257         if (fpgamgr_verify_msel())
 258                 return -EPERM;
 259
 260         /* Step 2 */
 261         if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
 262                 return -EPERM;
 263
 264         /*
 265          * Step 3:
 266          * Make sure no other external devices are trying to interfere with
 267          * programming:
 268          */
 269         if (wait_for_nconfig_pin_and_nstatus_pin())
 270                 return -ETIME;
 271
 272         /*
 273          * Step 4:
 274          * Deassert the signal drives from HPS
 275          *
 276          * S2F_NCE = 1
 277          * S2F_PR_REQUEST = 0
 278          * EN_CFG_CTRL = 0
 279          * EN_CFG_DATA = 0
 280          * S2F_NCONFIG = 1
 281          * S2F_NSTATUS_OE = 0
 282          * S2F_CONDONE_OE = 0
 283          */
 284         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 285                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 286
 287         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 288                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
 289
 290         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 291                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 292                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 293
 294         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 295                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 296
 297         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 298                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
 299                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
 300
 301         /*
 302          * Step 5:
 303          * Enable overrides
 304          * S2F_NENABLE_CONFIG = 0
 305          * S2F_NENABLE_NCONFIG = 0
 306          */
 307         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 308                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
 309         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 310                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
 311
 312         /*
 313          * Disable driving signals that HPS doesn't need to drive.
 314          * S2F_NENABLE_NSTATUS = 1
 315          * S2F_NENABLE_CONDONE = 1
 316          */
 317         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 318                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
 319                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
 320
 321         /*
 322          * Step 6:
 323          * Drive chip select S2F_NCE = 0
 324          */
 325          clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 326                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 327
 328         /* Step 7 */
 329         if (wait_for_nconfig_pin_and_nstatus_pin())
 330                 return -ETIME;
 331
 332         /* Step 8 */
 333         ret = fpgamgr_reset();
 334
 335         if (ret)
 336                 return ret;
 337
 338         /*
 339          * Step 9:
 340          * EN_CFG_CTRL and EN_CFG_DATA = 1
 341          */
 342         setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 343                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 344                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 345
 346         return 0;
 347 }
 348
 349 /* Ensure the FPGA entering config done */
 350 static int fpgamgr_program_poll_cd(void)
 351 {
 352         unsigned long reg, i;
 353
 354         for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
 355                 reg = readl(&fpga_manager_base->imgcfg_stat);
 356                 if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
 357                         return 0;
 358
 359                 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
 360                         printf("nstatus == 0 while waiting for condone\n");
 361                         return -EPERM;
 362                 }
 363         }
 364
 365         if (i == FPGA_TIMEOUT_CNT)
 366                 return -ETIME;
 367
 368         return 0;
 369 }
 370
 371 /* Ensure the FPGA entering user mode */
 372 static int fpgamgr_program_poll_usermode(void)
 373 {
 374         unsigned long reg;
 375         int ret = 0;
 376
 377         if (fpgamgr_dclkcnt_set(0xf))
 378                 return -ETIME;
 379
 380         ret = wait_for_user_mode();
 381         if (ret < 0) {
 382                 printf("%s: Failed to enter user mode with ", __func__);
 383                 printf("error code %d\n", ret);
 384                 return ret;
 385         }
 386
 387         /*
 388          * Step 14:
 389          * Stop DATA path and Dclk
 390          * EN_CFG_CTRL and EN_CFG_DATA = 0
 391          */
 392         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 393                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 394                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 395
 396         /*
 397          * Step 15:
 398          * Disable overrides
 399          * S2F_NENABLE_CONFIG = 1
 400          * S2F_NENABLE_NCONFIG = 1
 401          */
 402         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 403                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
 404         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 405                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
 406
 407         /* Disable chip select S2F_NCE = 1 */
 408         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 409                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 410
 411         /*
 412          * Step 16:
 413          * Final check
 414          */
 415         reg = readl(&fpga_manager_base->imgcfg_stat);
 416         if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
 417                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
 418             ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
 419                 ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
 420             ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
 421                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
 422                 return -EPERM;
 423
 424         return 0;
 425 }
 426
 427 int fpgamgr_program_finish(void)
 428 {
 429         /* Ensure the FPGA entering config done */
 430         int status = fpgamgr_program_poll_cd();
 431
 432         if (status) {
 433                 printf("FPGA: Poll CD failed with error code %d\n", status);
 434                 return -EPERM;
 435         }
 436         WATCHDOG_RESET();
 437
 438         /* Ensure the FPGA entering user mode */
 439         status = fpgamgr_program_poll_usermode();
 440         if (status) {
 441                 printf("FPGA: Poll usermode failed with error code %d\n",
 442                         status);
 443                 return -EPERM;
 444         }
 445
 446         printf("Full Configuration Succeeded.\n");
 447
 448         return 0;
 449 }
 450
 451 /*
 452  * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
 453  * Return 0 for sucess, non-zero for error.
 454  */
 455 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 456 {
 457         unsigned long status;
 458
 459         /* disable all signals from hps peripheral controller to fpga */
 460         writel(0, &system_manager_base->fpgaintf_en_global);
 461
 462         /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
 463         socfpga_bridges_reset();
 464
 465         /* Initialize the FPGA Manager */
 466         status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
 467         if (status)
 468                 return status;
 469
 470         /* Write the RBF data to FPGA Manager */
 471         fpgamgr_program_write(rbf_data, rbf_size);
 472
 473         return fpgamgr_program_finish();
 474 }