drivers/ddr/fsl/ctrl_regs.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2008-2016 Freescale Semiconductor, Inc.
   4  * Copyright 2017-2018 NXP Semiconductor
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  */
  12
  13 #include <common.h>
  14 #include <fsl_ddr_sdram.h>
  15 #include <fsl_errata.h>
  16 #include <fsl_ddr.h>
  17 #include <fsl_immap.h>
  18 #include <asm/io.h>
  19 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
  20         defined(CONFIG_ARM)
  21 #include <asm/arch/clock.h>
  22 #endif
  23
  24 /*
  25  * Determine Rtt value.
  26  *
  27  * This should likely be either board or controller specific.
  28  *
  29  * Rtt(nominal) - DDR2:
  30  *      0 = Rtt disabled
  31  *      1 = 75 ohm
  32  *      2 = 150 ohm
  33  *      3 = 50 ohm
  34  * Rtt(nominal) - DDR3:
  35  *      0 = Rtt disabled
  36  *      1 = 60 ohm
  37  *      2 = 120 ohm
  38  *      3 = 40 ohm
  39  *      4 = 20 ohm
  40  *      5 = 30 ohm
  41  *
  42  * FIXME: Apparently 8641 needs a value of 2
  43  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  44  *
  45  * FIXME: There was some effort down this line earlier:
  46  *
  47  *      unsigned int i;
  48  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  49  *              if (popts->dimmslot[i].num_valid_cs
  50  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  51  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  52  *                      rtt = 2;
  53  *                      break;
  54  *              }
  55  *      }
  56  */
  57 static inline int fsl_ddr_get_rtt(void)
  58 {
  59         int rtt;
  60
  61 #if defined(CONFIG_SYS_FSL_DDR1)
  62         rtt = 0;
  63 #elif defined(CONFIG_SYS_FSL_DDR2)
  64         rtt = 3;
  65 #else
  66         rtt = 0;
  67 #endif
  68
  69         return rtt;
  70 }
  71
  72 #ifdef CONFIG_SYS_FSL_DDR4
  73 /*
  74  * compute CAS write latency according to DDR4 spec
  75  * CWL = 9 for <= 1600MT/s
  76  *       10 for <= 1866MT/s
  77  *       11 for <= 2133MT/s
  78  *       12 for <= 2400MT/s
  79  *       14 for <= 2667MT/s
  80  *       16 for <= 2933MT/s
  81  *       18 for higher
  82  */
  83 static inline unsigned int compute_cas_write_latency(
  84                                 const unsigned int ctrl_num)
  85 {
  86         unsigned int cwl;
  87         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  88         if (mclk_ps >= 1250)
  89                 cwl = 9;
  90         else if (mclk_ps >= 1070)
  91                 cwl = 10;
  92         else if (mclk_ps >= 935)
  93                 cwl = 11;
  94         else if (mclk_ps >= 833)
  95                 cwl = 12;
  96         else if (mclk_ps >= 750)
  97                 cwl = 14;
  98         else if (mclk_ps >= 681)
  99                 cwl = 16;
 100         else
 101                 cwl = 18;
 102
 103         return cwl;
 104 }
 105 #else
 106 /*
 107  * compute the CAS write latency according to DDR3 spec
 108  * CWL = 5 if tCK >= 2.5ns
 109  *       6 if 2.5ns > tCK >= 1.875ns
 110  *       7 if 1.875ns > tCK >= 1.5ns
 111  *       8 if 1.5ns > tCK >= 1.25ns
 112  *       9 if 1.25ns > tCK >= 1.07ns
 113  *       10 if 1.07ns > tCK >= 0.935ns
 114  *       11 if 0.935ns > tCK >= 0.833ns
 115  *       12 if 0.833ns > tCK >= 0.75ns
 116  */
 117 static inline unsigned int compute_cas_write_latency(
 118                                 const unsigned int ctrl_num)
 119 {
 120         unsigned int cwl;
 121         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 122
 123         if (mclk_ps >= 2500)
 124                 cwl = 5;
 125         else if (mclk_ps >= 1875)
 126                 cwl = 6;
 127         else if (mclk_ps >= 1500)
 128                 cwl = 7;
 129         else if (mclk_ps >= 1250)
 130                 cwl = 8;
 131         else if (mclk_ps >= 1070)
 132                 cwl = 9;
 133         else if (mclk_ps >= 935)
 134                 cwl = 10;
 135         else if (mclk_ps >= 833)
 136                 cwl = 11;
 137         else if (mclk_ps >= 750)
 138                 cwl = 12;
 139         else {
 140                 cwl = 12;
 141                 printf("Warning: CWL is out of range\n");
 142         }
 143         return cwl;
 144 }
 145 #endif
 146
 147 /* Chip Select Configuration (CSn_CONFIG) */
 148 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 149                                const memctl_options_t *popts,
 150                                const dimm_params_t *dimm_params)
 151 {
 152         unsigned int cs_n_en = 0; /* Chip Select enable */
 153         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 154         unsigned int intlv_ctl = 0; /* Interleaving control */
 155         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 156         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 157         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 158         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 159         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 160         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 161         int go_config = 0;
 162 #ifdef CONFIG_SYS_FSL_DDR4
 163         unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
 164 #else
 165         unsigned int n_banks_per_sdram_device;
 166 #endif
 167
 168         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 169         switch (i) {
 170         case 0:
 171                 if (dimm_params[dimm_number].n_ranks > 0) {
 172                         go_config = 1;
 173                         /* These fields only available in CS0_CONFIG */
 174                         if (!popts->memctl_interleaving)
 175                                 break;
 176                         switch (popts->memctl_interleaving_mode) {
 177                         case FSL_DDR_256B_INTERLEAVING:
 178                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 179                         case FSL_DDR_PAGE_INTERLEAVING:
 180                         case FSL_DDR_BANK_INTERLEAVING:
 181                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 182                                 intlv_en = popts->memctl_interleaving;
 183                                 intlv_ctl = popts->memctl_interleaving_mode;
 184                                 break;
 185                         default:
 186                                 break;
 187                         }
 188                 }
 189                 break;
 190         case 1:
 191                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 192                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 193                         go_config = 1;
 194                 break;
 195         case 2:
 196                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 197                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 198                         go_config = 1;
 199                 break;
 200         case 3:
 201                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 202                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 203                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 204                         go_config = 1;
 205                 break;
 206         default:
 207                 break;
 208         }
 209         if (go_config) {
 210                 cs_n_en = 1;
 211                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 212                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 213                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 214 #ifdef CONFIG_SYS_FSL_DDR4
 215                 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
 216                 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
 217 #else
 218                 n_banks_per_sdram_device
 219                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 220                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 221 #endif
 222                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 223                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 224         }
 225         ddr->cs[i].config = (0
 226                 | ((cs_n_en & 0x1) << 31)
 227                 | ((intlv_en & 0x3) << 29)
 228                 | ((intlv_ctl & 0xf) << 24)
 229                 | ((ap_n_en & 0x1) << 23)
 230
 231                 /* XXX: some implementation only have 1 bit starting at left */
 232                 | ((odt_rd_cfg & 0x7) << 20)
 233
 234                 /* XXX: Some implementation only have 1 bit starting at left */
 235                 | ((odt_wr_cfg & 0x7) << 16)
 236
 237                 | ((ba_bits_cs_n & 0x3) << 14)
 238                 | ((row_bits_cs_n & 0x7) << 8)
 239 #ifdef CONFIG_SYS_FSL_DDR4
 240                 | ((bg_bits_cs_n & 0x3) << 4)
 241 #endif
 242                 | ((col_bits_cs_n & 0x7) << 0)
 243                 );
 244         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 245 }
 246
 247 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 248 /* FIXME: 8572 */
 249 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 250 {
 251         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 252
 253         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 254         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 255 }
 256
 257 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 258
 259 #if !defined(CONFIG_SYS_FSL_DDR1)
 260 /*
 261  * Check DIMM configuration, return 2 if quad-rank or two dual-rank
 262  * Return 1 if other two slots configuration. Return 0 if single slot.
 263  */
 264 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 265 {
 266 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
 267         if (dimm_params[0].n_ranks == 4)
 268                 return 2;
 269 #endif
 270
 271 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
 272         if ((dimm_params[0].n_ranks == 2) &&
 273                 (dimm_params[1].n_ranks == 2))
 274                 return 2;
 275
 276 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 277         if (dimm_params[0].n_ranks == 4)
 278                 return 2;
 279 #endif
 280
 281         if ((dimm_params[0].n_ranks != 0) &&
 282             (dimm_params[2].n_ranks != 0))
 283                 return 1;
 284 #endif
 285         return 0;
 286 }
 287
 288 /*
 289  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 290  *
 291  * Avoid writing for DDR I.  The new PQ38 DDR controller
 292  * dreams up non-zero default values to be backwards compatible.
 293  */
 294 static void set_timing_cfg_0(const unsigned int ctrl_num,
 295                                 fsl_ddr_cfg_regs_t *ddr,
 296                                 const memctl_options_t *popts,
 297                                 const dimm_params_t *dimm_params)
 298 {
 299         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 300         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 301         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 302         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 303         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 304
 305         /* Active powerdown exit timing (tXARD and tXARDS). */
 306         unsigned char act_pd_exit_mclk;
 307         /* Precharge powerdown exit timing (tXP). */
 308         unsigned char pre_pd_exit_mclk;
 309         /* ODT powerdown exit timing (tAXPD). */
 310         unsigned char taxpd_mclk = 0;
 311         /* Mode register set cycle time (tMRD). */
 312         unsigned char tmrd_mclk;
 313 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
 314         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 315 #endif
 316
 317 #ifdef CONFIG_SYS_FSL_DDR4
 318         /* tXP=max(4nCK, 6ns) */
 319         int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
 320         unsigned int data_rate = get_ddr_freq(ctrl_num);
 321
 322         /* for faster clock, need more time for data setup */
 323         trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
 324
 325         /*
 326          * for single quad-rank DIMM and two-slot DIMMs
 327          * to avoid ODT overlap
 328          */
 329         switch (avoid_odt_overlap(dimm_params)) {
 330         case 2:
 331                 twrt_mclk = 2;
 332                 twwt_mclk = 2;
 333                 trrt_mclk = 2;
 334                 break;
 335         default:
 336                 twrt_mclk = 1;
 337                 twwt_mclk = 1;
 338                 trrt_mclk = 0;
 339                 break;
 340         }
 341
 342         act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 343         pre_pd_exit_mclk = act_pd_exit_mclk;
 344         /*
 345          * MRS_CYC = max(tMRD, tMOD)
 346          * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
 347          */
 348         tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
 349 #elif defined(CONFIG_SYS_FSL_DDR3)
 350         unsigned int data_rate = get_ddr_freq(ctrl_num);
 351         int txp;
 352         unsigned int ip_rev;
 353         int odt_overlap;
 354         /*
 355          * (tXARD and tXARDS). Empirical?
 356          * The DDR3 spec has not tXARD,
 357          * we use the tXP instead of it.
 358          * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
 359          *     max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
 360          * spec has not the tAXPD, we use
 361          * tAXPD=1, need design to confirm.
 362          */
 363         txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
 364
 365         ip_rev = fsl_ddr_get_version(ctrl_num);
 366         if (ip_rev >= 0x40700) {
 367                 /*
 368                  * MRS_CYC = max(tMRD, tMOD)
 369                  * tMRD = 4nCK (8nCK for RDIMM)
 370                  * tMOD = max(12nCK, 15ns)
 371                  */
 372                 tmrd_mclk = max((unsigned int)12,
 373                                 picos_to_mclk(ctrl_num, 15000));
 374         } else {
 375                 /*
 376                  * MRS_CYC = tMRD
 377                  * tMRD = 4nCK (8nCK for RDIMM)
 378                  */
 379                 if (popts->registered_dimm_en)
 380                         tmrd_mclk = 8;
 381                 else
 382                         tmrd_mclk = 4;
 383         }
 384
 385         /* set the turnaround time */
 386
 387         /*
 388          * for single quad-rank DIMM and two-slot DIMMs
 389          * to avoid ODT overlap
 390          */
 391         odt_overlap = avoid_odt_overlap(dimm_params);
 392         switch (odt_overlap) {
 393         case 2:
 394                 twwt_mclk = 2;
 395                 trrt_mclk = 1;
 396                 break;
 397         case 1:
 398                 twwt_mclk = 1;
 399                 trrt_mclk = 0;
 400                 break;
 401         default:
 402                 break;
 403         }
 404
 405         /* for faster clock, need more time for data setup */
 406         trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
 407
 408         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 409                 twrt_mclk = 1;
 410
 411         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 412                 act_pd_exit_mclk = 1;
 413                 pre_pd_exit_mclk = 1;
 414                 taxpd_mclk = 1;
 415         } else {
 416                 /* act_pd_exit_mclk = tXARD, see above */
 417                 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 418                 /* Mode register MR0[A12] is '1' - fast exit */
 419                 pre_pd_exit_mclk = act_pd_exit_mclk;
 420                 taxpd_mclk = 1;
 421         }
 422 #else /* CONFIG_SYS_FSL_DDR2 */
 423         /*
 424          * (tXARD and tXARDS). Empirical?
 425          * tXARD = 2 for DDR2
 426          * tXP=2
 427          * tAXPD=8
 428          */
 429         act_pd_exit_mclk = 2;
 430         pre_pd_exit_mclk = 2;
 431         taxpd_mclk = 8;
 432         tmrd_mclk = 2;
 433 #endif
 434
 435         if (popts->trwt_override)
 436                 trwt_mclk = popts->trwt;
 437
 438         ddr->timing_cfg_0 = (0
 439                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 440                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 441                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 442                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 443                 | ((act_pd_exit_mclk & 0xf) << 20)  /* ACT_PD_EXIT */
 444                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 445                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 446                 | ((tmrd_mclk & 0x1f) << 0)     /* MRS_CYC */
 447                 );
 448         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 449 }
 450 #endif  /* !defined(CONFIG_SYS_FSL_DDR1) */
 451
 452 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 453 static void set_timing_cfg_3(const unsigned int ctrl_num,
 454                              fsl_ddr_cfg_regs_t *ddr,
 455                              const memctl_options_t *popts,
 456                              const common_timing_params_t *common_dimm,
 457                              unsigned int cas_latency,
 458                              unsigned int additive_latency)
 459 {
 460         /* Extended precharge to activate interval (tRP) */
 461         unsigned int ext_pretoact = 0;
 462         /* Extended Activate to precharge interval (tRAS) */
 463         unsigned int ext_acttopre = 0;
 464         /* Extended activate to read/write interval (tRCD) */
 465         unsigned int ext_acttorw = 0;
 466         /* Extended refresh recovery time (tRFC) */
 467         unsigned int ext_refrec;
 468         /* Extended MCAS latency from READ cmd */
 469         unsigned int ext_caslat = 0;
 470         /* Extended additive latency */
 471         unsigned int ext_add_lat = 0;
 472         /* Extended last data to precharge interval (tWR) */
 473         unsigned int ext_wrrec = 0;
 474         /* Control Adjust */
 475         unsigned int cntl_adj = 0;
 476
 477         ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
 478         ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
 479         ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
 480         ext_caslat = (2 * cas_latency - 1) >> 4;
 481         ext_add_lat = additive_latency >> 4;
 482 #ifdef CONFIG_SYS_FSL_DDR4
 483         ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
 484 #else
 485         ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
 486         /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 487 #endif
 488         ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
 489                 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 490
 491         ddr->timing_cfg_3 = (0
 492                 | ((ext_pretoact & 0x1) << 28)
 493                 | ((ext_acttopre & 0x3) << 24)
 494                 | ((ext_acttorw & 0x1) << 22)
 495                 | ((ext_refrec & 0x3F) << 16)
 496                 | ((ext_caslat & 0x3) << 12)
 497                 | ((ext_add_lat & 0x1) << 10)
 498                 | ((ext_wrrec & 0x1) << 8)
 499                 | ((cntl_adj & 0x7) << 0)
 500                 );
 501         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 502 }
 503
 504 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 505 static void set_timing_cfg_1(const unsigned int ctrl_num,
 506                              fsl_ddr_cfg_regs_t *ddr,
 507                              const memctl_options_t *popts,
 508                              const common_timing_params_t *common_dimm,
 509                              unsigned int cas_latency)
 510 {
 511         /* Precharge-to-activate interval (tRP) */
 512         unsigned char pretoact_mclk;
 513         /* Activate to precharge interval (tRAS) */
 514         unsigned char acttopre_mclk;
 515         /*  Activate to read/write interval (tRCD) */
 516         unsigned char acttorw_mclk;
 517         /* CASLAT */
 518         unsigned char caslat_ctrl;
 519         /*  Refresh recovery time (tRFC) ; trfc_low */
 520         unsigned char refrec_ctrl;
 521         /* Last data to precharge minimum interval (tWR) */
 522         unsigned char wrrec_mclk;
 523         /* Activate-to-activate interval (tRRD) */
 524         unsigned char acttoact_mclk;
 525         /* Last write data pair to read command issue interval (tWTR) */
 526         unsigned char wrtord_mclk;
 527 #ifdef CONFIG_SYS_FSL_DDR4
 528         /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
 529         static const u8 wrrec_table[] = {
 530                 10, 10, 10, 10, 10,
 531                 10, 10, 10, 10, 10,
 532                 12, 12, 14, 14, 16,
 533                 16, 18, 18, 20, 20,
 534                 24, 24, 24, 24};
 535 #else
 536         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 537         static const u8 wrrec_table[] = {
 538                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 539 #endif
 540
 541         pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
 542         acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
 543         acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
 544
 545         /*
 546          * Translate CAS Latency to a DDR controller field value:
 547          *
 548          *      CAS Lat DDR I   DDR II  Ctrl
 549          *      Clocks  SPD Bit SPD Bit Value
 550          *      ------- ------- ------- -----
 551          *      1.0     0               0001
 552          *      1.5     1               0010
 553          *      2.0     2       2       0011
 554          *      2.5     3               0100
 555          *      3.0     4       3       0101
 556          *      3.5     5               0110
 557          *      4.0             4       0111
 558          *      4.5                     1000
 559          *      5.0             5       1001
 560          */
 561 #if defined(CONFIG_SYS_FSL_DDR1)
 562         caslat_ctrl = (cas_latency + 1) & 0x07;
 563 #elif defined(CONFIG_SYS_FSL_DDR2)
 564         caslat_ctrl = 2 * cas_latency - 1;
 565 #else
 566         /*
 567          * if the CAS latency more than 8 cycle,
 568          * we need set extend bit for it at
 569          * TIMING_CFG_3[EXT_CASLAT]
 570          */
 571         if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
 572                 caslat_ctrl = 2 * cas_latency - 1;
 573         else
 574                 caslat_ctrl = (cas_latency - 1) << 1;
 575 #endif
 576
 577 #ifdef CONFIG_SYS_FSL_DDR4
 578         refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
 579         wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 580         acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
 581         wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
 582         if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
 583                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 584         else
 585                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 586 #else
 587         refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
 588         wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 589         acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
 590         wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
 591         if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
 592                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 593         else
 594                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 595 #endif
 596         if (popts->otf_burst_chop_en)
 597                 wrrec_mclk += 2;
 598
 599         /*
 600          * JEDEC has min requirement for tRRD
 601          */
 602 #if defined(CONFIG_SYS_FSL_DDR3)
 603         if (acttoact_mclk < 4)
 604                 acttoact_mclk = 4;
 605 #endif
 606         /*
 607          * JEDEC has some min requirements for tWTR
 608          */
 609 #if defined(CONFIG_SYS_FSL_DDR2)
 610         if (wrtord_mclk < 2)
 611                 wrtord_mclk = 2;
 612 #elif defined(CONFIG_SYS_FSL_DDR3)
 613         if (wrtord_mclk < 4)
 614                 wrtord_mclk = 4;
 615 #endif
 616         if (popts->otf_burst_chop_en)
 617                 wrtord_mclk += 2;
 618
 619         ddr->timing_cfg_1 = (0
 620                 | ((pretoact_mclk & 0x0F) << 28)
 621                 | ((acttopre_mclk & 0x0F) << 24)
 622                 | ((acttorw_mclk & 0xF) << 20)
 623                 | ((caslat_ctrl & 0xF) << 16)
 624                 | ((refrec_ctrl & 0xF) << 12)
 625                 | ((wrrec_mclk & 0x0F) << 8)
 626                 | ((acttoact_mclk & 0x0F) << 4)
 627                 | ((wrtord_mclk & 0x0F) << 0)
 628                 );
 629         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 630 }
 631
 632 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 633 static void set_timing_cfg_2(const unsigned int ctrl_num,
 634                              fsl_ddr_cfg_regs_t *ddr,
 635                              const memctl_options_t *popts,
 636                              const common_timing_params_t *common_dimm,
 637                              unsigned int cas_latency,
 638                              unsigned int additive_latency)
 639 {
 640         /* Additive latency */
 641         unsigned char add_lat_mclk;
 642         /* CAS-to-preamble override */
 643         unsigned short cpo;
 644         /* Write latency */
 645         unsigned char wr_lat;
 646         /*  Read to precharge (tRTP) */
 647         unsigned char rd_to_pre;
 648         /* Write command to write data strobe timing adjustment */
 649         unsigned char wr_data_delay;
 650         /* Minimum CKE pulse width (tCKE) */
 651         unsigned char cke_pls;
 652         /* Window for four activates (tFAW) */
 653         unsigned short four_act;
 654 #ifdef CONFIG_SYS_FSL_DDR3
 655         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 656 #endif
 657
 658         /* FIXME add check that this must be less than acttorw_mclk */
 659         add_lat_mclk = additive_latency;
 660         cpo = popts->cpo_override;
 661
 662 #if defined(CONFIG_SYS_FSL_DDR1)
 663         /*
 664          * This is a lie.  It should really be 1, but if it is
 665          * set to 1, bits overlap into the old controller's
 666          * otherwise unused ACSM field.  If we leave it 0, then
 667          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 668          */
 669         wr_lat = 0;
 670 #elif defined(CONFIG_SYS_FSL_DDR2)
 671         wr_lat = cas_latency - 1;
 672 #else
 673         wr_lat = compute_cas_write_latency(ctrl_num);
 674 #endif
 675
 676 #ifdef CONFIG_SYS_FSL_DDR4
 677         rd_to_pre = picos_to_mclk(ctrl_num, 7500);
 678 #else
 679         rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
 680 #endif
 681         /*
 682          * JEDEC has some min requirements for tRTP
 683          */
 684 #if defined(CONFIG_SYS_FSL_DDR2)
 685         if (rd_to_pre  < 2)
 686                 rd_to_pre  = 2;
 687 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 688         if (rd_to_pre < 4)
 689                 rd_to_pre = 4;
 690 #endif
 691         if (popts->otf_burst_chop_en)
 692                 rd_to_pre += 2; /* according to UM */
 693
 694         wr_data_delay = popts->write_data_delay;
 695 #ifdef CONFIG_SYS_FSL_DDR4
 696         cpo = 0;
 697         cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
 698 #elif defined(CONFIG_SYS_FSL_DDR3)
 699         /*
 700          * cke pulse = max(3nCK, 7.5ns) for DDR3-800
 701          *             max(3nCK, 5.625ns) for DDR3-1066, 1333
 702          *             max(3nCK, 5ns) for DDR3-1600, 1866, 2133
 703          */
 704         cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
 705                                         (mclk_ps > 1245 ? 5625 : 5000)));
 706 #else
 707         cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
 708 #endif
 709         four_act = picos_to_mclk(ctrl_num,
 710                                  popts->tfaw_window_four_activates_ps);
 711
 712         ddr->timing_cfg_2 = (0
 713                 | ((add_lat_mclk & 0xf) << 28)
 714                 | ((cpo & 0x1f) << 23)
 715                 | ((wr_lat & 0xf) << 19)
 716                 | (((wr_lat & 0x10) >> 4) << 18)
 717                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 718                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 719                 | ((cke_pls & 0x7) << 6)
 720                 | ((four_act & 0x3f) << 0)
 721                 );
 722         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 723 }
 724
 725 /* DDR SDRAM Register Control Word */
 726 static void set_ddr_sdram_rcw(const unsigned int ctrl_num,
 727                               fsl_ddr_cfg_regs_t *ddr,
 728                               const memctl_options_t *popts,
 729                               const common_timing_params_t *common_dimm)
 730 {
 731         unsigned int ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
 732         unsigned int rc0a, rc0f;
 733
 734         if (common_dimm->all_dimms_registered &&
 735             !common_dimm->all_dimms_unbuffered) {
 736                 if (popts->rcw_override) {
 737                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 738                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 739                         ddr->ddr_sdram_rcw_3 = popts->rcw_3;
 740                 } else {
 741                         rc0a = ddr_freq > 3200 ? 0x7 :
 742                                (ddr_freq > 2933 ? 0x6 :
 743                                 (ddr_freq > 2666 ? 0x5 :
 744                                  (ddr_freq > 2400 ? 0x4 :
 745                                   (ddr_freq > 2133 ? 0x3 :
 746                                    (ddr_freq > 1866 ? 0x2 :
 747                                     (ddr_freq > 1600 ? 1 : 0))))));
 748                         rc0f = ddr_freq > 3200 ? 0x3 :
 749                                (ddr_freq > 2400 ? 0x2 :
 750                                 (ddr_freq > 2133 ? 0x1 : 0));
 751                         ddr->ddr_sdram_rcw_1 =
 752                                 common_dimm->rcw[0] << 28 | \
 753                                 common_dimm->rcw[1] << 24 | \
 754                                 common_dimm->rcw[2] << 20 | \
 755                                 common_dimm->rcw[3] << 16 | \
 756                                 common_dimm->rcw[4] << 12 | \
 757                                 common_dimm->rcw[5] << 8 | \
 758                                 common_dimm->rcw[6] << 4 | \
 759                                 common_dimm->rcw[7];
 760                         ddr->ddr_sdram_rcw_2 =
 761                                 common_dimm->rcw[8] << 28 | \
 762                                 common_dimm->rcw[9] << 24 | \
 763                                 rc0a << 20 | \
 764                                 common_dimm->rcw[11] << 16 | \
 765                                 common_dimm->rcw[12] << 12 | \
 766                                 common_dimm->rcw[13] << 8 | \
 767                                 common_dimm->rcw[14] << 4 | \
 768                                 rc0f;
 769                         ddr->ddr_sdram_rcw_3 =
 770                                 ((ddr_freq - 1260 + 19) / 20) << 8;
 771                 }
 772                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n",
 773                       ddr->ddr_sdram_rcw_1);
 774                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n",
 775                       ddr->ddr_sdram_rcw_2);
 776                 debug("FSLDDR: ddr_sdram_rcw_3 = 0x%08x\n",
 777                       ddr->ddr_sdram_rcw_3);
 778         }
 779 }
 780
 781 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 782 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 783                                const memctl_options_t *popts,
 784                                const common_timing_params_t *common_dimm)
 785 {
 786         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 787         unsigned int sren;              /* Self refresh enable (during sleep) */
 788         unsigned int ecc_en;            /* ECC enable. */
 789         unsigned int rd_en;             /* Registered DIMM enable */
 790         unsigned int sdram_type;        /* Type of SDRAM */
 791         unsigned int dyn_pwr;           /* Dynamic power management mode */
 792         unsigned int dbw;               /* DRAM dta bus width */
 793         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 794         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 795         unsigned int threet_en;         /* Enable 3T timing */
 796         unsigned int twot_en;           /* Enable 2T timing */
 797         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 798         unsigned int x32_en = 0;        /* x32 enable */
 799         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 800         unsigned int hse;               /* Global half strength override */
 801         unsigned int acc_ecc_en = 0;    /* Accumulated ECC enable */
 802         unsigned int mem_halt = 0;      /* memory controller halt */
 803         unsigned int bi = 0;            /* Bypass initialization */
 804
 805         mem_en = 1;
 806         sren = popts->self_refresh_in_sleep;
 807         if (common_dimm->all_dimms_ecc_capable) {
 808                 /* Allow setting of ECC only if all DIMMs are ECC. */
 809                 ecc_en = popts->ecc_mode;
 810         } else {
 811                 ecc_en = 0;
 812         }
 813
 814         if (common_dimm->all_dimms_registered &&
 815             !common_dimm->all_dimms_unbuffered) {
 816                 rd_en = 1;
 817                 twot_en = 0;
 818         } else {
 819                 rd_en = 0;
 820                 twot_en = popts->twot_en;
 821         }
 822
 823         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 824
 825         dyn_pwr = popts->dynamic_power;
 826         dbw = popts->data_bus_width;
 827         /* 8-beat burst enable DDR-III case
 828          * we must clear it when use the on-the-fly mode,
 829          * must set it when use the 32-bits bus mode.
 830          */
 831         if ((sdram_type == SDRAM_TYPE_DDR3) ||
 832             (sdram_type == SDRAM_TYPE_DDR4)) {
 833                 if (popts->burst_length == DDR_BL8)
 834                         eight_be = 1;
 835                 if (popts->burst_length == DDR_OTF)
 836                         eight_be = 0;
 837                 if (dbw == 0x1)
 838                         eight_be = 1;
 839         }
 840
 841         threet_en = popts->threet_en;
 842         ba_intlv_ctl = popts->ba_intlv_ctl;
 843         hse = popts->half_strength_driver_enable;
 844
 845         /* set when ddr bus width < 64 */
 846         acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
 847
 848         ddr->ddr_sdram_cfg = (0
 849                         | ((mem_en & 0x1) << 31)
 850                         | ((sren & 0x1) << 30)
 851                         | ((ecc_en & 0x1) << 29)
 852                         | ((rd_en & 0x1) << 28)
 853                         | ((sdram_type & 0x7) << 24)
 854                         | ((dyn_pwr & 0x1) << 21)
 855                         | ((dbw & 0x3) << 19)
 856                         | ((eight_be & 0x1) << 18)
 857                         | ((ncap & 0x1) << 17)
 858                         | ((threet_en & 0x1) << 16)
 859                         | ((twot_en & 0x1) << 15)
 860                         | ((ba_intlv_ctl & 0x7F) << 8)
 861                         | ((x32_en & 0x1) << 5)
 862                         | ((pchb8 & 0x1) << 4)
 863                         | ((hse & 0x1) << 3)
 864                         | ((acc_ecc_en & 0x1) << 2)
 865                         | ((mem_halt & 0x1) << 1)
 866                         | ((bi & 0x1) << 0)
 867                         );
 868         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 869 }
 870
 871 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 872 static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 873                                fsl_ddr_cfg_regs_t *ddr,
 874                                const memctl_options_t *popts,
 875                                const unsigned int unq_mrs_en)
 876 {
 877         unsigned int frc_sr = 0;        /* Force self refresh */
 878         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 879         unsigned int odt_cfg = 0;       /* ODT configuration */
 880         unsigned int num_pr;            /* Number of posted refreshes */
 881         unsigned int slow = 0;          /* DDR will be run less than 1250 */
 882         unsigned int x4_en = 0;         /* x4 DRAM enable */
 883         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 884         unsigned int ap_en;             /* Address Parity Enable */
 885         unsigned int d_init;            /* DRAM data initialization */
 886         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 887         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 888         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 889         int i;
 890 #ifndef CONFIG_SYS_FSL_DDR4
 891         unsigned int dll_rst_dis = 1;   /* DLL reset disable */
 892         unsigned int dqs_cfg;           /* DQS configuration */
 893
 894         dqs_cfg = popts->dqs_config;
 895 #endif
 896         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 897                 if (popts->cs_local_opts[i].odt_rd_cfg
 898                         || popts->cs_local_opts[i].odt_wr_cfg) {
 899                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 900                         break;
 901                 }
 902         }
 903         sr_ie = popts->self_refresh_interrupt_en;
 904         num_pr = popts->package_3ds + 1;
 905
 906         /*
 907          * 8572 manual says
 908          *     {TIMING_CFG_1[PRETOACT]
 909          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 910          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 911          *      << DDR_SDRAM_INTERVAL[REFINT]
 912          */
 913 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 914         obc_cfg = popts->otf_burst_chop_en;
 915 #else
 916         obc_cfg = 0;
 917 #endif
 918
 919 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
 920         slow = get_ddr_freq(ctrl_num) < 1249000000;
 921 #endif
 922
 923         if (popts->registered_dimm_en)
 924                 rcw_en = 1;
 925
 926         /* DDR4 can have address parity for UDIMM and discrete */
 927         if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
 928             (!popts->registered_dimm_en)) {
 929                 ap_en = 0;
 930         } else {
 931                 ap_en = popts->ap_en;
 932         }
 933
 934         x4_en = popts->x4_en ? 1 : 0;
 935
 936 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 937         /* Use the DDR controller to auto initialize memory. */
 938         d_init = popts->ecc_init_using_memctl;
 939         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 940         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 941 #else
 942         /* Memory will be initialized via DMA, or not at all. */
 943         d_init = 0;
 944 #endif
 945
 946 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 947         md_en = popts->mirrored_dimm;
 948 #endif
 949         qd_en = popts->quad_rank_present ? 1 : 0;
 950         ddr->ddr_sdram_cfg_2 = (0
 951                 | ((frc_sr & 0x1) << 31)
 952                 | ((sr_ie & 0x1) << 30)
 953 #ifndef CONFIG_SYS_FSL_DDR4
 954                 | ((dll_rst_dis & 0x1) << 29)
 955                 | ((dqs_cfg & 0x3) << 26)
 956 #endif
 957                 | ((odt_cfg & 0x3) << 21)
 958                 | ((num_pr & 0xf) << 12)
 959                 | ((slow & 1) << 11)
 960                 | (x4_en << 10)
 961                 | (qd_en << 9)
 962                 | (unq_mrs_en << 8)
 963                 | ((obc_cfg & 0x1) << 6)
 964                 | ((ap_en & 0x1) << 5)
 965                 | ((d_init & 0x1) << 4)
 966                 | ((rcw_en & 0x1) << 2)
 967                 | ((md_en & 0x1) << 0)
 968                 );
 969         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 970 }
 971
 972 #ifdef CONFIG_SYS_FSL_DDR4
 973 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 974 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
 975                                 fsl_ddr_cfg_regs_t *ddr,
 976                                 const memctl_options_t *popts,
 977                                 const common_timing_params_t *common_dimm,
 978                                 const unsigned int unq_mrs_en)
 979 {
 980         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 981         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 982         int i;
 983         unsigned int wr_crc = 0;        /* Disable */
 984         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 985         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 986         unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
 987         unsigned int mpr = 0;   /* serial */
 988         unsigned int wc_lat;
 989         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 990
 991         if (popts->rtt_override)
 992                 rtt_wr = popts->rtt_wr_override_value;
 993         else
 994                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 995
 996         if (common_dimm->extended_op_srt)
 997                 srt = common_dimm->extended_op_srt;
 998
 999         esdmode2 = (0
1000                 | ((wr_crc & 0x1) << 12)
1001                 | ((rtt_wr & 0x3) << 9)
1002                 | ((srt & 0x3) << 6)
1003                 | ((cwl & 0x7) << 3));
1004
1005         if (mclk_ps >= 1250)
1006                 wc_lat = 0;
1007         else if (mclk_ps >= 833)
1008                 wc_lat = 1;
1009         else
1010                 wc_lat = 2;
1011
1012         esdmode3 = (0
1013                 | ((mpr & 0x3) << 11)
1014                 | ((wc_lat & 0x3) << 9));
1015
1016         ddr->ddr_sdram_mode_2 = (0
1017                                  | ((esdmode2 & 0xFFFF) << 16)
1018                                  | ((esdmode3 & 0xFFFF) << 0)
1019                                  );
1020         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1021
1022         if (unq_mrs_en) {       /* unique mode registers are supported */
1023                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1024                         if (popts->rtt_override)
1025                                 rtt_wr = popts->rtt_wr_override_value;
1026                         else
1027                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1028
1029                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
1030                         esdmode2 |= (rtt_wr & 0x3) << 9;
1031                         switch (i) {
1032                         case 1:
1033                                 ddr->ddr_sdram_mode_4 = (0
1034                                         | ((esdmode2 & 0xFFFF) << 16)
1035                                         | ((esdmode3 & 0xFFFF) << 0)
1036                                         );
1037                                 break;
1038                         case 2:
1039                                 ddr->ddr_sdram_mode_6 = (0
1040                                         | ((esdmode2 & 0xFFFF) << 16)
1041                                         | ((esdmode3 & 0xFFFF) << 0)
1042                                         );
1043                                 break;
1044                         case 3:
1045                                 ddr->ddr_sdram_mode_8 = (0
1046                                         | ((esdmode2 & 0xFFFF) << 16)
1047                                         | ((esdmode3 & 0xFFFF) << 0)
1048                                         );
1049                                 break;
1050                         }
1051                 }
1052                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1053                       ddr->ddr_sdram_mode_4);
1054                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1055                       ddr->ddr_sdram_mode_6);
1056                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1057                       ddr->ddr_sdram_mode_8);
1058         }
1059 }
1060 #elif defined(CONFIG_SYS_FSL_DDR3)
1061 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1062 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1063                                 fsl_ddr_cfg_regs_t *ddr,
1064                                 const memctl_options_t *popts,
1065                                 const common_timing_params_t *common_dimm,
1066                                 const unsigned int unq_mrs_en)
1067 {
1068         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1069         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1070         int i;
1071         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
1072         unsigned int srt = 0;   /* self-refresh temerature, normal range */
1073         unsigned int asr = 0;   /* auto self-refresh disable */
1074         unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
1075         unsigned int pasr = 0;  /* partial array self refresh disable */
1076
1077         if (popts->rtt_override)
1078                 rtt_wr = popts->rtt_wr_override_value;
1079         else
1080                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
1081
1082         if (common_dimm->extended_op_srt)
1083                 srt = common_dimm->extended_op_srt;
1084
1085         esdmode2 = (0
1086                 | ((rtt_wr & 0x3) << 9)
1087                 | ((srt & 0x1) << 7)
1088                 | ((asr & 0x1) << 6)
1089                 | ((cwl & 0x7) << 3)
1090                 | ((pasr & 0x7) << 0));
1091         ddr->ddr_sdram_mode_2 = (0
1092                                  | ((esdmode2 & 0xFFFF) << 16)
1093                                  | ((esdmode3 & 0xFFFF) << 0)
1094                                  );
1095         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1096
1097         if (unq_mrs_en) {       /* unique mode registers are supported */
1098                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1099                         if (popts->rtt_override)
1100                                 rtt_wr = popts->rtt_wr_override_value;
1101                         else
1102                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1103
1104                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
1105                         esdmode2 |= (rtt_wr & 0x3) << 9;
1106                         switch (i) {
1107                         case 1:
1108                                 ddr->ddr_sdram_mode_4 = (0
1109                                         | ((esdmode2 & 0xFFFF) << 16)
1110                                         | ((esdmode3 & 0xFFFF) << 0)
1111                                         );
1112                                 break;
1113                         case 2:
1114                                 ddr->ddr_sdram_mode_6 = (0
1115                                         | ((esdmode2 & 0xFFFF) << 16)
1116                                         | ((esdmode3 & 0xFFFF) << 0)
1117                                         );
1118                                 break;
1119                         case 3:
1120                                 ddr->ddr_sdram_mode_8 = (0
1121                                         | ((esdmode2 & 0xFFFF) << 16)
1122                                         | ((esdmode3 & 0xFFFF) << 0)
1123                                         );
1124                                 break;
1125                         }
1126                 }
1127                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1128                         ddr->ddr_sdram_mode_4);
1129                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1130                         ddr->ddr_sdram_mode_6);
1131                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1132                         ddr->ddr_sdram_mode_8);
1133         }
1134 }
1135
1136 #else /* for DDR2 and DDR1 */
1137 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1138 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1139                                 fsl_ddr_cfg_regs_t *ddr,
1140                                 const memctl_options_t *popts,
1141                                 const common_timing_params_t *common_dimm,
1142                                 const unsigned int unq_mrs_en)
1143 {
1144         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1145         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1146
1147         ddr->ddr_sdram_mode_2 = (0
1148                                  | ((esdmode2 & 0xFFFF) << 16)
1149                                  | ((esdmode3 & 0xFFFF) << 0)
1150                                  );
1151         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1152 }
1153 #endif
1154
1155 #ifdef CONFIG_SYS_FSL_DDR4
1156 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1157 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1158                                 const memctl_options_t *popts,
1159                                 const common_timing_params_t *common_dimm,
1160                                 const unsigned int unq_mrs_en)
1161 {
1162         int i;
1163         unsigned short esdmode4 = 0;    /* Extended SDRAM mode 4 */
1164         unsigned short esdmode5;        /* Extended SDRAM mode 5 */
1165         int rtt_park = 0;
1166         bool four_cs = false;
1167         const unsigned int mclk_ps = get_memory_clk_period_ps(0);
1168
1169 #if CONFIG_CHIP_SELECTS_PER_CTRL == 4
1170         if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
1171             (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) &&
1172             (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) &&
1173             (ddr->cs[3].config & SDRAM_CS_CONFIG_EN))
1174                 four_cs = true;
1175 #endif
1176         if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
1177                 esdmode5 = 0x00000500;  /* Data mask enable, RTT_PARK CS0 */
1178                 rtt_park = four_cs ? 0 : 1;
1179         } else {
1180                 esdmode5 = 0x00000400;  /* Data mask enabled */
1181         }
1182
1183         /*
1184          * For DDR3, set C/A latency if address parity is enabled.
1185          * For DDR4, set C/A latency for UDIMM only. For RDIMM the delay is
1186          * handled by register chip and RCW settings.
1187          */
1188         if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
1189             ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
1190              !popts->registered_dimm_en)) {
1191                 if (mclk_ps >= 935) {
1192                         /* for DDR4-1600/1866/2133 */
1193                         esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1194                 } else if (mclk_ps >= 833) {
1195                         /* for DDR4-2400 */
1196                         esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1197                 } else {
1198                         printf("parity: mclk_ps = %d not supported\n", mclk_ps);
1199                 }
1200         }
1201
1202         ddr->ddr_sdram_mode_9 = (0
1203                                  | ((esdmode4 & 0xffff) << 16)
1204                                  | ((esdmode5 & 0xffff) << 0)
1205                                 );
1206
1207         /* Normally only the first enabled CS use 0x500, others use 0x400
1208          * But when four chip-selects are all enabled, all mode registers
1209          * need 0x500 to park.
1210          */
1211
1212         debug("FSLDDR: ddr_sdram_mode_9 = 0x%08x\n", ddr->ddr_sdram_mode_9);
1213         if (unq_mrs_en) {       /* unique mode registers are supported */
1214                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1215                         if (!rtt_park &&
1216                             (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
1217                                 esdmode5 |= 0x00000500; /* RTT_PARK */
1218                                 rtt_park = four_cs ? 0 : 1;
1219                         } else {
1220                                 esdmode5 = 0x00000400;
1221                         }
1222
1223                         if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
1224                             ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
1225                              !popts->registered_dimm_en)) {
1226                                 if (mclk_ps >= 935) {
1227                                         /* for DDR4-1600/1866/2133 */
1228                                         esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1229                                 } else if (mclk_ps >= 833) {
1230                                         /* for DDR4-2400 */
1231                                         esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1232                                 } else {
1233                                         printf("parity: mclk_ps = %d not supported\n",
1234                                                mclk_ps);
1235                                 }
1236                         }
1237
1238                         switch (i) {
1239                         case 1:
1240                                 ddr->ddr_sdram_mode_11 = (0
1241                                         | ((esdmode4 & 0xFFFF) << 16)
1242                                         | ((esdmode5 & 0xFFFF) << 0)
1243                                         );
1244                                 break;
1245                         case 2:
1246                                 ddr->ddr_sdram_mode_13 = (0
1247                                         | ((esdmode4 & 0xFFFF) << 16)
1248                                         | ((esdmode5 & 0xFFFF) << 0)
1249                                         );
1250                                 break;
1251                         case 3:
1252                                 ddr->ddr_sdram_mode_15 = (0
1253                                         | ((esdmode4 & 0xFFFF) << 16)
1254                                         | ((esdmode5 & 0xFFFF) << 0)
1255                                         );
1256                                 break;
1257                         }
1258                 }
1259                 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1260                       ddr->ddr_sdram_mode_11);
1261                 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1262                       ddr->ddr_sdram_mode_13);
1263                 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1264                       ddr->ddr_sdram_mode_15);
1265         }
1266 }
1267
1268 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1269 static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
1270                                 fsl_ddr_cfg_regs_t *ddr,
1271                                 const memctl_options_t *popts,
1272                                 const common_timing_params_t *common_dimm,
1273                                 const unsigned int unq_mrs_en)
1274 {
1275         int i;
1276         unsigned short esdmode6 = 0;    /* Extended SDRAM mode 6 */
1277         unsigned short esdmode7 = 0;    /* Extended SDRAM mode 7 */
1278         unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1279
1280         esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1281
1282         if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
1283                 esdmode6 |= 1 << 6;     /* Range 2 */
1284
1285         ddr->ddr_sdram_mode_10 = (0
1286                                  | ((esdmode6 & 0xffff) << 16)
1287                                  | ((esdmode7 & 0xffff) << 0)
1288                                 );
1289         debug("FSLDDR: ddr_sdram_mode_10 = 0x%08x\n", ddr->ddr_sdram_mode_10);
1290         if (unq_mrs_en) {       /* unique mode registers are supported */
1291                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1292                         switch (i) {
1293                         case 1:
1294                                 ddr->ddr_sdram_mode_12 = (0
1295                                         | ((esdmode6 & 0xFFFF) << 16)
1296                                         | ((esdmode7 & 0xFFFF) << 0)
1297                                         );
1298                                 break;
1299                         case 2:
1300                                 ddr->ddr_sdram_mode_14 = (0
1301                                         | ((esdmode6 & 0xFFFF) << 16)
1302                                         | ((esdmode7 & 0xFFFF) << 0)
1303                                         );
1304                                 break;
1305                         case 3:
1306                                 ddr->ddr_sdram_mode_16 = (0
1307                                         | ((esdmode6 & 0xFFFF) << 16)
1308                                         | ((esdmode7 & 0xFFFF) << 0)
1309                                         );
1310                                 break;
1311                         }
1312                 }
1313                 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1314                       ddr->ddr_sdram_mode_12);
1315                 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1316                       ddr->ddr_sdram_mode_14);
1317                 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1318                       ddr->ddr_sdram_mode_16);
1319         }
1320 }
1321
1322 #endif
1323
1324 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1325 static void set_ddr_sdram_interval(const unsigned int ctrl_num,
1326                                 fsl_ddr_cfg_regs_t *ddr,
1327                                 const memctl_options_t *popts,
1328                                 const common_timing_params_t *common_dimm)
1329 {
1330         unsigned int refint;    /* Refresh interval */
1331         unsigned int bstopre;   /* Precharge interval */
1332
1333         refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
1334
1335         bstopre = popts->bstopre;
1336
1337         /* refint field used 0x3FFF in earlier controllers */
1338         ddr->ddr_sdram_interval = (0
1339                                    | ((refint & 0xFFFF) << 16)
1340                                    | ((bstopre & 0x3FFF) << 0)
1341                                    );
1342         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
1343 }
1344
1345 #ifdef CONFIG_SYS_FSL_DDR4
1346 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1347 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1348                                fsl_ddr_cfg_regs_t *ddr,
1349                                const memctl_options_t *popts,
1350                                const common_timing_params_t *common_dimm,
1351                                unsigned int cas_latency,
1352                                unsigned int additive_latency,
1353                                const unsigned int unq_mrs_en)
1354 {
1355         int i;
1356         unsigned short esdmode;         /* Extended SDRAM mode */
1357         unsigned short sdmode;          /* SDRAM mode */
1358
1359         /* Mode Register - MR1 */
1360         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1361         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1362         unsigned int rtt;
1363         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1364         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1365         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1366         unsigned int dll_en = 1;        /* DLL Enable  1=Enable (Normal),
1367                                                        0=Disable (Test/Debug) */
1368
1369         /* Mode Register - MR0 */
1370         unsigned int wr = 0;    /* Write Recovery */
1371         unsigned int dll_rst;   /* DLL Reset */
1372         unsigned int mode;      /* Normal=0 or Test=1 */
1373         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1374         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1375         unsigned int bt;
1376         unsigned int bl;        /* BL: Burst Length */
1377
1378         unsigned int wr_mclk;
1379         /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1380         static const u8 wr_table[] = {
1381                 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1382         /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1383         static const u8 cas_latency_table[] = {
1384                 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1385                 9, 9, 10, 10, 11, 11};
1386
1387         if (popts->rtt_override)
1388                 rtt = popts->rtt_override_value;
1389         else
1390                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1391
1392         if (additive_latency == (cas_latency - 1))
1393                 al = 1;
1394         if (additive_latency == (cas_latency - 2))
1395                 al = 2;
1396
1397         if (popts->quad_rank_present)
1398                 dic = 1;        /* output driver impedance 240/7 ohm */
1399
1400         /*
1401          * The esdmode value will also be used for writing
1402          * MR1 during write leveling for DDR3, although the
1403          * bits specifically related to the write leveling
1404          * scheme will be handled automatically by the DDR
1405          * controller. so we set the wrlvl_en = 0 here.
1406          */
1407         esdmode = (0
1408                 | ((qoff & 0x1) << 12)
1409                 | ((tdqs_en & 0x1) << 11)
1410                 | ((rtt & 0x7) << 8)
1411                 | ((wrlvl_en & 0x1) << 7)
1412                 | ((al & 0x3) << 3)
1413                 | ((dic & 0x3) << 1)   /* DIC field is split */
1414                 | ((dll_en & 0x1) << 0)
1415                 );
1416
1417         /*
1418          * DLL control for precharge PD
1419          * 0=slow exit DLL off (tXPDLL)
1420          * 1=fast exit DLL on (tXP)
1421          */
1422
1423         wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1424         if (wr_mclk <= 24) {
1425                 wr = wr_table[wr_mclk - 10];
1426         } else {
1427                 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1428                        wr_mclk);
1429         }
1430
1431         dll_rst = 0;    /* dll no reset */
1432         mode = 0;       /* normal mode */
1433
1434         /* look up table to get the cas latency bits */
1435         if (cas_latency >= 9 && cas_latency <= 24)
1436                 caslat = cas_latency_table[cas_latency - 9];
1437         else
1438                 printf("Error: unsupported cas latency for mode register\n");
1439
1440         bt = 0; /* Nibble sequential */
1441
1442         switch (popts->burst_length) {
1443         case DDR_BL8:
1444                 bl = 0;
1445                 break;
1446         case DDR_OTF:
1447                 bl = 1;
1448                 break;
1449         case DDR_BC4:
1450                 bl = 2;
1451                 break;
1452         default:
1453                 printf("Error: invalid burst length of %u specified. ",
1454                        popts->burst_length);
1455                 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1456                 bl = 1;
1457                 break;
1458         }
1459
1460         sdmode = (0
1461                   | ((wr & 0x7) << 9)
1462                   | ((dll_rst & 0x1) << 8)
1463                   | ((mode & 0x1) << 7)
1464                   | (((caslat >> 1) & 0x7) << 4)
1465                   | ((bt & 0x1) << 3)
1466                   | ((caslat & 1) << 2)
1467                   | ((bl & 0x3) << 0)
1468                   );
1469
1470         ddr->ddr_sdram_mode = (0
1471                                | ((esdmode & 0xFFFF) << 16)
1472                                | ((sdmode & 0xFFFF) << 0)
1473                                );
1474
1475         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1476
1477         if (unq_mrs_en) {       /* unique mode registers are supported */
1478                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1479                         if (popts->rtt_override)
1480                                 rtt = popts->rtt_override_value;
1481                         else
1482                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1483
1484                         esdmode &= 0xF8FF;      /* clear bit 10,9,8 for rtt */
1485                         esdmode |= (rtt & 0x7) << 8;
1486                         switch (i) {
1487                         case 1:
1488                                 ddr->ddr_sdram_mode_3 = (0
1489                                        | ((esdmode & 0xFFFF) << 16)
1490                                        | ((sdmode & 0xFFFF) << 0)
1491                                        );
1492                                 break;
1493                         case 2:
1494                                 ddr->ddr_sdram_mode_5 = (0
1495                                        | ((esdmode & 0xFFFF) << 16)
1496                                        | ((sdmode & 0xFFFF) << 0)
1497                                        );
1498                                 break;
1499                         case 3:
1500                                 ddr->ddr_sdram_mode_7 = (0
1501                                        | ((esdmode & 0xFFFF) << 16)
1502                                        | ((sdmode & 0xFFFF) << 0)
1503                                        );
1504                                 break;
1505                         }
1506                 }
1507                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1508                       ddr->ddr_sdram_mode_3);
1509                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1510                       ddr->ddr_sdram_mode_5);
1511                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1512                       ddr->ddr_sdram_mode_5);
1513         }
1514 }
1515
1516 #elif defined(CONFIG_SYS_FSL_DDR3)
1517 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1518 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1519                                fsl_ddr_cfg_regs_t *ddr,
1520                                const memctl_options_t *popts,
1521                                const common_timing_params_t *common_dimm,
1522                                unsigned int cas_latency,
1523                                unsigned int additive_latency,
1524                                const unsigned int unq_mrs_en)
1525 {
1526         int i;
1527         unsigned short esdmode;         /* Extended SDRAM mode */
1528         unsigned short sdmode;          /* SDRAM mode */
1529
1530         /* Mode Register - MR1 */
1531         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1532         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1533         unsigned int rtt;
1534         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1535         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1536         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1537         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1538                                                        1=Disable (Test/Debug) */
1539
1540         /* Mode Register - MR0 */
1541         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
1542         unsigned int wr = 0;    /* Write Recovery */
1543         unsigned int dll_rst;   /* DLL Reset */
1544         unsigned int mode;      /* Normal=0 or Test=1 */
1545         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1546         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1547         unsigned int bt;
1548         unsigned int bl;        /* BL: Burst Length */
1549
1550         unsigned int wr_mclk;
1551         /*
1552          * DDR_SDRAM_MODE doesn't support 9,11,13,15
1553          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1554          * for this table
1555          */
1556         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
1557
1558         if (popts->rtt_override)
1559                 rtt = popts->rtt_override_value;
1560         else
1561                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1562
1563         if (additive_latency == (cas_latency - 1))
1564                 al = 1;
1565         if (additive_latency == (cas_latency - 2))
1566                 al = 2;
1567
1568         if (popts->quad_rank_present)
1569                 dic = 1;        /* output driver impedance 240/7 ohm */
1570
1571         /*
1572          * The esdmode value will also be used for writing
1573          * MR1 during write leveling for DDR3, although the
1574          * bits specifically related to the write leveling
1575          * scheme will be handled automatically by the DDR
1576          * controller. so we set the wrlvl_en = 0 here.
1577          */
1578         esdmode = (0
1579                 | ((qoff & 0x1) << 12)
1580                 | ((tdqs_en & 0x1) << 11)
1581                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1582                 | ((wrlvl_en & 0x1) << 7)
1583                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1584                 | ((dic & 0x2) << 4)   /* DIC field is split */
1585                 | ((al & 0x3) << 3)
1586                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1587                 | ((dic & 0x1) << 1)   /* DIC field is split */
1588                 | ((dll_en & 0x1) << 0)
1589                 );
1590
1591         /*
1592          * DLL control for precharge PD
1593          * 0=slow exit DLL off (tXPDLL)
1594          * 1=fast exit DLL on (tXP)
1595          */
1596         dll_on = 1;
1597
1598         wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1599         if (wr_mclk <= 16) {
1600                 wr = wr_table[wr_mclk - 5];
1601         } else {
1602                 printf("Error: unsupported write recovery for mode register "
1603                        "wr_mclk = %d\n", wr_mclk);
1604         }
1605
1606         dll_rst = 0;    /* dll no reset */
1607         mode = 0;       /* normal mode */
1608
1609         /* look up table to get the cas latency bits */
1610         if (cas_latency >= 5 && cas_latency <= 16) {
1611                 unsigned char cas_latency_table[] = {
1612                         0x2,    /* 5 clocks */
1613                         0x4,    /* 6 clocks */
1614                         0x6,    /* 7 clocks */
1615                         0x8,    /* 8 clocks */
1616                         0xa,    /* 9 clocks */
1617                         0xc,    /* 10 clocks */
1618                         0xe,    /* 11 clocks */
1619                         0x1,    /* 12 clocks */
1620                         0x3,    /* 13 clocks */
1621                         0x5,    /* 14 clocks */
1622                         0x7,    /* 15 clocks */
1623                         0x9,    /* 16 clocks */
1624                 };
1625                 caslat = cas_latency_table[cas_latency - 5];
1626         } else {
1627                 printf("Error: unsupported cas latency for mode register\n");
1628         }
1629
1630         bt = 0; /* Nibble sequential */
1631
1632         switch (popts->burst_length) {
1633         case DDR_BL8:
1634                 bl = 0;
1635                 break;
1636         case DDR_OTF:
1637                 bl = 1;
1638                 break;
1639         case DDR_BC4:
1640                 bl = 2;
1641                 break;
1642         default:
1643                 printf("Error: invalid burst length of %u specified. "
1644                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1645                         popts->burst_length);
1646                 bl = 1;
1647                 break;
1648         }
1649
1650         sdmode = (0
1651                   | ((dll_on & 0x1) << 12)
1652                   | ((wr & 0x7) << 9)
1653                   | ((dll_rst & 0x1) << 8)
1654                   | ((mode & 0x1) << 7)
1655                   | (((caslat >> 1) & 0x7) << 4)
1656                   | ((bt & 0x1) << 3)
1657                   | ((caslat & 1) << 2)
1658                   | ((bl & 0x3) << 0)
1659                   );
1660
1661         ddr->ddr_sdram_mode = (0
1662                                | ((esdmode & 0xFFFF) << 16)
1663                                | ((sdmode & 0xFFFF) << 0)
1664                                );
1665
1666         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1667
1668         if (unq_mrs_en) {       /* unique mode registers are supported */
1669                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1670                         if (popts->rtt_override)
1671                                 rtt = popts->rtt_override_value;
1672                         else
1673                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1674
1675                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
1676                         esdmode |= (0
1677                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1678                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1679                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1680                                 );
1681                         switch (i) {
1682                         case 1:
1683                                 ddr->ddr_sdram_mode_3 = (0
1684                                        | ((esdmode & 0xFFFF) << 16)
1685                                        | ((sdmode & 0xFFFF) << 0)
1686                                        );
1687                                 break;
1688                         case 2:
1689                                 ddr->ddr_sdram_mode_5 = (0
1690                                        | ((esdmode & 0xFFFF) << 16)
1691                                        | ((sdmode & 0xFFFF) << 0)
1692                                        );
1693                                 break;
1694                         case 3:
1695                                 ddr->ddr_sdram_mode_7 = (0
1696                                        | ((esdmode & 0xFFFF) << 16)
1697                                        | ((sdmode & 0xFFFF) << 0)
1698                                        );
1699                                 break;
1700                         }
1701                 }
1702                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1703                         ddr->ddr_sdram_mode_3);
1704                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1705                         ddr->ddr_sdram_mode_5);
1706                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1707                         ddr->ddr_sdram_mode_5);
1708         }
1709 }
1710
1711 #else /* !CONFIG_SYS_FSL_DDR3 */
1712
1713 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1714 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1715                                fsl_ddr_cfg_regs_t *ddr,
1716                                const memctl_options_t *popts,
1717                                const common_timing_params_t *common_dimm,
1718                                unsigned int cas_latency,
1719                                unsigned int additive_latency,
1720                                const unsigned int unq_mrs_en)
1721 {
1722         unsigned short esdmode;         /* Extended SDRAM mode */
1723         unsigned short sdmode;          /* SDRAM mode */
1724
1725         /*
1726          * FIXME: This ought to be pre-calculated in a
1727          * technology-specific routine,
1728          * e.g. compute_DDR2_mode_register(), and then the
1729          * sdmode and esdmode passed in as part of common_dimm.
1730          */
1731
1732         /* Extended Mode Register */
1733         unsigned int mrs = 0;           /* Mode Register Set */
1734         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1735         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1736         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1737         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1738                                            0x7=OCD default state */
1739         unsigned int rtt;
1740         unsigned int al;                /* Posted CAS# additive latency (AL) */
1741         unsigned int ods = 0;           /* Output Drive Strength:
1742                                                 0 = Full strength (18ohm)
1743                                                 1 = Reduced strength (4ohm) */
1744         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1745                                                        1=Disable (Test/Debug) */
1746
1747         /* Mode Register (MR) */
1748         unsigned int mr;        /* Mode Register Definition */
1749         unsigned int pd;        /* Power-Down Mode */
1750         unsigned int wr;        /* Write Recovery */
1751         unsigned int dll_res;   /* DLL Reset */
1752         unsigned int mode;      /* Normal=0 or Test=1 */
1753         unsigned int caslat = 0;/* CAS# latency */
1754         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1755         unsigned int bt;
1756         unsigned int bl;        /* BL: Burst Length */
1757
1758         dqs_en = !popts->dqs_config;
1759         rtt = fsl_ddr_get_rtt();
1760
1761         al = additive_latency;
1762
1763         esdmode = (0
1764                 | ((mrs & 0x3) << 14)
1765                 | ((outputs & 0x1) << 12)
1766                 | ((rdqs_en & 0x1) << 11)
1767                 | ((dqs_en & 0x1) << 10)
1768                 | ((ocd & 0x7) << 7)
1769                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1770                 | ((al & 0x7) << 3)
1771                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1772                 | ((ods & 0x1) << 1)
1773                 | ((dll_en & 0x1) << 0)
1774                 );
1775
1776         mr = 0;          /* FIXME: CHECKME */
1777
1778         /*
1779          * 0 = Fast Exit (Normal)
1780          * 1 = Slow Exit (Low Power)
1781          */
1782         pd = 0;
1783
1784 #if defined(CONFIG_SYS_FSL_DDR1)
1785         wr = 0;       /* Historical */
1786 #elif defined(CONFIG_SYS_FSL_DDR2)
1787         wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1788 #endif
1789         dll_res = 0;
1790         mode = 0;
1791
1792 #if defined(CONFIG_SYS_FSL_DDR1)
1793         if (1 <= cas_latency && cas_latency <= 4) {
1794                 unsigned char mode_caslat_table[4] = {
1795                         0x5,    /* 1.5 clocks */
1796                         0x2,    /* 2.0 clocks */
1797                         0x6,    /* 2.5 clocks */
1798                         0x3     /* 3.0 clocks */
1799                 };
1800                 caslat = mode_caslat_table[cas_latency - 1];
1801         } else {
1802                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1803         }
1804 #elif defined(CONFIG_SYS_FSL_DDR2)
1805         caslat = cas_latency;
1806 #endif
1807         bt = 0;
1808
1809         switch (popts->burst_length) {
1810         case DDR_BL4:
1811                 bl = 2;
1812                 break;
1813         case DDR_BL8:
1814                 bl = 3;
1815                 break;
1816         default:
1817                 printf("Error: invalid burst length of %u specified. "
1818                         " Defaulting to 4 beats.\n",
1819                         popts->burst_length);
1820                 bl = 2;
1821                 break;
1822         }
1823
1824         sdmode = (0
1825                   | ((mr & 0x3) << 14)
1826                   | ((pd & 0x1) << 12)
1827                   | ((wr & 0x7) << 9)
1828                   | ((dll_res & 0x1) << 8)
1829                   | ((mode & 0x1) << 7)
1830                   | ((caslat & 0x7) << 4)
1831                   | ((bt & 0x1) << 3)
1832                   | ((bl & 0x7) << 0)
1833                   );
1834
1835         ddr->ddr_sdram_mode = (0
1836                                | ((esdmode & 0xFFFF) << 16)
1837                                | ((sdmode & 0xFFFF) << 0)
1838                                );
1839         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1840 }
1841 #endif
1842
1843 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1844 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1845 {
1846         unsigned int init_value;        /* Initialization value */
1847
1848 #ifdef CONFIG_MEM_INIT_VALUE
1849         init_value = CONFIG_MEM_INIT_VALUE;
1850 #else
1851         init_value = 0xDEADBEEF;
1852 #endif
1853         ddr->ddr_data_init = init_value;
1854 }
1855
1856 /*
1857  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1858  * The old controller on the 8540/60 doesn't have this register.
1859  * Hope it's OK to set it (to 0) anyway.
1860  */
1861 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1862                                          const memctl_options_t *popts)
1863 {
1864         unsigned int clk_adjust;        /* Clock adjust */
1865         unsigned int ss_en = 0;         /* Source synchronous enable */
1866
1867 #if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
1868         /* Per FSL Application Note: AN2805 */
1869         ss_en = 1;
1870 #endif
1871         if (fsl_ddr_get_version(0) >= 0x40701) {
1872                 /* clk_adjust in 5-bits on T-series and LS-series */
1873                 clk_adjust = (popts->clk_adjust & 0x1F) << 22;
1874         } else {
1875                 /* clk_adjust in 4-bits on earlier MPC85xx and P-series */
1876                 clk_adjust = (popts->clk_adjust & 0xF) << 23;
1877         }
1878
1879         ddr->ddr_sdram_clk_cntl = (0
1880                                    | ((ss_en & 0x1) << 31)
1881                                    | clk_adjust
1882                                    );
1883         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1884 }
1885
1886 /* DDR Initialization Address (DDR_INIT_ADDR) */
1887 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1888 {
1889         unsigned int init_addr = 0;     /* Initialization address */
1890
1891         ddr->ddr_init_addr = init_addr;
1892 }
1893
1894 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1895 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1896 {
1897         unsigned int uia = 0;   /* Use initialization address */
1898         unsigned int init_ext_addr = 0; /* Initialization address */
1899
1900         ddr->ddr_init_ext_addr = (0
1901                                   | ((uia & 0x1) << 31)
1902                                   | (init_ext_addr & 0xF)
1903                                   );
1904 }
1905
1906 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1907 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1908                                 const memctl_options_t *popts)
1909 {
1910         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1911         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1912         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1913         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1914         unsigned int trwt_mclk = 0;     /* ext_rwt */
1915         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1916
1917 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1918         if (popts->burst_length == DDR_BL8) {
1919                 /* We set BL/2 for fixed BL8 */
1920                 rrt = 0;        /* BL/2 clocks */
1921                 wwt = 0;        /* BL/2 clocks */
1922         } else {
1923                 /* We need to set BL/2 + 2 to BC4 and OTF */
1924                 rrt = 2;        /* BL/2 + 2 clocks */
1925                 wwt = 2;        /* BL/2 + 2 clocks */
1926         }
1927 #endif
1928 #ifdef CONFIG_SYS_FSL_DDR4
1929         dll_lock = 2;   /* tDLLK = 1024 clocks */
1930 #elif defined(CONFIG_SYS_FSL_DDR3)
1931         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1932 #endif
1933
1934         if (popts->trwt_override)
1935                 trwt_mclk = popts->trwt;
1936
1937         ddr->timing_cfg_4 = (0
1938                              | ((rwt & 0xf) << 28)
1939                              | ((wrt & 0xf) << 24)
1940                              | ((rrt & 0xf) << 20)
1941                              | ((wwt & 0xf) << 16)
1942                              | ((trwt_mclk & 0xc) << 12)
1943                              | (dll_lock & 0x3)
1944                              );
1945         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1946 }
1947
1948 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1949 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1950 {
1951         unsigned int rodt_on = 0;       /* Read to ODT on */
1952         unsigned int rodt_off = 0;      /* Read to ODT off */
1953         unsigned int wodt_on = 0;       /* Write to ODT on */
1954         unsigned int wodt_off = 0;      /* Write to ODT off */
1955
1956 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1957         unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1958                               ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1959         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1960         if (cas_latency >= wr_lat)
1961                 rodt_on = cas_latency - wr_lat + 1;
1962         rodt_off = 4;   /*  4 clocks */
1963         wodt_on = 1;    /*  1 clocks */
1964         wodt_off = 4;   /*  4 clocks */
1965 #endif
1966
1967         ddr->timing_cfg_5 = (0
1968                              | ((rodt_on & 0x1f) << 24)
1969                              | ((rodt_off & 0x7) << 20)
1970                              | ((wodt_on & 0x1f) << 12)
1971                              | ((wodt_off & 0x7) << 8)
1972                              );
1973         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1974 }
1975
1976 #ifdef CONFIG_SYS_FSL_DDR4
1977 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1978 {
1979         unsigned int hs_caslat = 0;
1980         unsigned int hs_wrlat = 0;
1981         unsigned int hs_wrrec = 0;
1982         unsigned int hs_clkadj = 0;
1983         unsigned int hs_wrlvl_start = 0;
1984
1985         ddr->timing_cfg_6 = (0
1986                              | ((hs_caslat & 0x1f) << 24)
1987                              | ((hs_wrlat & 0x1f) << 19)
1988                              | ((hs_wrrec & 0x1f) << 12)
1989                              | ((hs_clkadj & 0x1f) << 6)
1990                              | ((hs_wrlvl_start & 0x1f) << 0)
1991                             );
1992         debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1993 }
1994
1995 static void set_timing_cfg_7(const unsigned int ctrl_num,
1996                              fsl_ddr_cfg_regs_t *ddr,
1997                              const memctl_options_t *popts,
1998                              const common_timing_params_t *common_dimm)
1999 {
2000         unsigned int txpr, tcksre, tcksrx;
2001         unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd;
2002         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
2003
2004         txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
2005         tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
2006         tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
2007
2008         if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN &&
2009             CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4) {
2010                 /* for DDR4 only */
2011                 par_lat = (ddr->ddr_sdram_rcw_2 & 0xf) + 1;
2012                 debug("PAR_LAT = %u for mclk_ps = %d\n", par_lat, mclk_ps);
2013         }
2014
2015         cs_to_cmd = 0;
2016
2017         if (txpr <= 200)
2018                 cke_rst = 0;
2019         else if (txpr <= 256)
2020                 cke_rst = 1;
2021         else if (txpr <= 512)
2022                 cke_rst = 2;
2023         else
2024                 cke_rst = 3;
2025
2026         if (tcksre <= 19)
2027                 cksre = tcksre - 5;
2028         else
2029                 cksre = 15;
2030
2031         if (tcksrx <= 19)
2032                 cksrx = tcksrx - 5;
2033         else
2034                 cksrx = 15;
2035
2036         ddr->timing_cfg_7 = (0
2037                              | ((cke_rst & 0x3) << 28)
2038                              | ((cksre & 0xf) << 24)
2039                              | ((cksrx & 0xf) << 20)
2040                              | ((par_lat & 0xf) << 16)
2041                              | ((cs_to_cmd & 0xf) << 4)
2042                             );
2043         debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
2044 }
2045
2046 static void set_timing_cfg_8(const unsigned int ctrl_num,
2047                              fsl_ddr_cfg_regs_t *ddr,
2048                              const memctl_options_t *popts,
2049                              const common_timing_params_t *common_dimm,
2050                              unsigned int cas_latency)
2051 {
2052         int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
2053         unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
2054         int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
2055         int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
2056                       ((ddr->timing_cfg_2 & 0x00040000) >> 14);
2057
2058         rwt_bg = cas_latency + 2 + 4 - wr_lat;
2059         if (rwt_bg < tccdl)
2060                 rwt_bg = tccdl - rwt_bg;
2061         else
2062                 rwt_bg = 0;
2063
2064         wrt_bg = wr_lat + 4 + 1 - cas_latency;
2065         if (wrt_bg < tccdl)
2066                 wrt_bg = tccdl - wrt_bg;
2067         else
2068                 wrt_bg = 0;
2069
2070         if (popts->burst_length == DDR_BL8) {
2071                 rrt_bg = tccdl - 4;
2072                 wwt_bg = tccdl - 4;
2073         } else {
2074                 rrt_bg = tccdl - 2;
2075                 wwt_bg = tccdl - 2;
2076         }
2077
2078         acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
2079         wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
2080         if (popts->otf_burst_chop_en)
2081                 wrtord_bg += 2;
2082
2083         pre_all_rec = 0;
2084
2085         ddr->timing_cfg_8 = (0
2086                              | ((rwt_bg & 0xf) << 28)
2087                              | ((wrt_bg & 0xf) << 24)
2088                              | ((rrt_bg & 0xf) << 20)
2089                              | ((wwt_bg & 0xf) << 16)
2090                              | ((acttoact_bg & 0xf) << 12)
2091                              | ((wrtord_bg & 0xf) << 8)
2092                              | ((pre_all_rec & 0x1f) << 0)
2093                             );
2094
2095         debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
2096 }
2097
2098 static void set_timing_cfg_9(const unsigned int ctrl_num,
2099                              fsl_ddr_cfg_regs_t *ddr,
2100                              const memctl_options_t *popts,
2101                              const common_timing_params_t *common_dimm)
2102 {
2103         unsigned int refrec_cid_mclk = 0;
2104         unsigned int acttoact_cid_mclk = 0;
2105
2106         if (popts->package_3ds) {
2107                 refrec_cid_mclk =
2108                         picos_to_mclk(ctrl_num, common_dimm->trfc_slr_ps);
2109                 acttoact_cid_mclk = 4U; /* tRRDS_slr */
2110         }
2111
2112         ddr->timing_cfg_9 = (refrec_cid_mclk & 0x3ff) << 16     |
2113                             (acttoact_cid_mclk & 0xf) << 8;
2114
2115         debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
2116 }
2117
2118 /* This function needs to be called after set_ddr_sdram_cfg() is called */
2119 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
2120                                const dimm_params_t *dimm_params)
2121 {
2122         unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
2123         int i;
2124
2125         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
2126                 if (dimm_params[i].n_ranks)
2127                         break;
2128         }
2129         if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) {
2130                 puts("DDR error: no DIMM found!\n");
2131                 return;
2132         }
2133
2134         ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) |
2135                         ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) |
2136                         ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) |
2137                         ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) |
2138                         ((dimm_params[i].dq_mapping[4] & 0x3F) << 2);
2139
2140         ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) |
2141                         ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) |
2142                         ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) |
2143                         ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) |
2144                         ((dimm_params[i].dq_mapping[11] & 0x3F) << 2);
2145
2146         ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) |
2147                         ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) |
2148                         ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) |
2149                         ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) |
2150                         ((dimm_params[i].dq_mapping[16] & 0x3F) << 2);
2151
2152         /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
2153         ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) |
2154                         ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) |
2155                         (acc_ecc_en ? 0 :
2156                          (dimm_params[i].dq_mapping[9] & 0x3F) << 14) |
2157                         dimm_params[i].dq_mapping_ors;
2158
2159         debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
2160         debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
2161         debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
2162         debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
2163 }
2164 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
2165                                const memctl_options_t *popts)
2166 {
2167         int rd_pre;
2168
2169         rd_pre = popts->quad_rank_present ? 1 : 0;
2170
2171         ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
2172         /* Disable MRS on parity error for RDIMMs */
2173         ddr->ddr_sdram_cfg_3 |= popts->registered_dimm_en ? 1 : 0;
2174
2175         if (popts->package_3ds) {       /* only 2,4,8 are supported */
2176                 if ((popts->package_3ds + 1) & 0x1) {
2177                         printf("Error: Unsupported 3DS DIMM with %d die\n",
2178                                popts->package_3ds + 1);
2179                 } else {
2180                         ddr->ddr_sdram_cfg_3 |= ((popts->package_3ds + 1) >> 1)
2181                                                 << 4;
2182                 }
2183         }
2184
2185         debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
2186 }
2187 #endif  /* CONFIG_SYS_FSL_DDR4 */
2188
2189 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
2190 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
2191 {
2192         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
2193         /* Normal Operation Full Calibration Time (tZQoper) */
2194         unsigned int zqoper = 0;
2195         /* Normal Operation Short Calibration Time (tZQCS) */
2196         unsigned int zqcs = 0;
2197 #ifdef CONFIG_SYS_FSL_DDR4
2198         unsigned int zqcs_init;
2199 #endif
2200
2201         if (zq_en) {
2202 #ifdef CONFIG_SYS_FSL_DDR4
2203                 zqinit = 10;    /* 1024 clocks */
2204                 zqoper = 9;     /* 512 clocks */
2205                 zqcs = 7;       /* 128 clocks */
2206                 zqcs_init = 5;  /* 1024 refresh sequences */
2207 #else
2208                 zqinit = 9;     /* 512 clocks */
2209                 zqoper = 8;     /* 256 clocks */
2210                 zqcs = 6;       /* 64 clocks */
2211 #endif
2212         }
2213
2214         ddr->ddr_zq_cntl = (0
2215                             | ((zq_en & 0x1) << 31)
2216                             | ((zqinit & 0xF) << 24)
2217                             | ((zqoper & 0xF) << 16)
2218                             | ((zqcs & 0xF) << 8)
2219 #ifdef CONFIG_SYS_FSL_DDR4
2220                             | ((zqcs_init & 0xF) << 0)
2221 #endif
2222                             );
2223         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
2224 }
2225
2226 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
2227 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
2228                                 const memctl_options_t *popts)
2229 {
2230         /*
2231          * First DQS pulse rising edge after margining mode
2232          * is programmed (tWL_MRD)
2233          */
2234         unsigned int wrlvl_mrd = 0;
2235         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2236         unsigned int wrlvl_odten = 0;
2237         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2238         unsigned int wrlvl_dqsen = 0;
2239         /* WRLVL_SMPL: Write leveling sample time */
2240         unsigned int wrlvl_smpl = 0;
2241         /* WRLVL_WLR: Write leveling repeition time */
2242         unsigned int wrlvl_wlr = 0;
2243         /* WRLVL_START: Write leveling start time */
2244         unsigned int wrlvl_start = 0;
2245
2246         /* suggest enable write leveling for DDR3 due to fly-by topology */
2247         if (wrlvl_en) {
2248                 /* tWL_MRD min = 40 nCK, we set it 64 */
2249                 wrlvl_mrd = 0x6;
2250                 /* tWL_ODTEN 128 */
2251                 wrlvl_odten = 0x7;
2252                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2253                 wrlvl_dqsen = 0x5;
2254                 /*
2255                  * Write leveling sample time at least need 6 clocks
2256                  * higher than tWLO to allow enough time for progagation
2257                  * delay and sampling the prime data bits.
2258                  */
2259                 wrlvl_smpl = 0xf;
2260                 /*
2261                  * Write leveling repetition time
2262                  * at least tWLO + 6 clocks clocks
2263                  * we set it 64
2264                  */
2265                 wrlvl_wlr = 0x6;
2266                 /*
2267                  * Write leveling start time
2268                  * The value use for the DQS_ADJUST for the first sample
2269                  * when write leveling is enabled. It probably needs to be
2270                  * overridden per platform.
2271                  */
2272                 wrlvl_start = 0x8;
2273                 /*
2274                  * Override the write leveling sample and start time
2275                  * according to specific board
2276                  */
2277                 if (popts->wrlvl_override) {
2278                         wrlvl_smpl = popts->wrlvl_sample;
2279                         wrlvl_start = popts->wrlvl_start;
2280                 }
2281         }
2282
2283         ddr->ddr_wrlvl_cntl = (0
2284                                | ((wrlvl_en & 0x1) << 31)
2285                                | ((wrlvl_mrd & 0x7) << 24)
2286                                | ((wrlvl_odten & 0x7) << 20)
2287                                | ((wrlvl_dqsen & 0x7) << 16)
2288                                | ((wrlvl_smpl & 0xf) << 12)
2289                                | ((wrlvl_wlr & 0x7) << 8)
2290                                | ((wrlvl_start & 0x1F) << 0)
2291                                );
2292         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
2293         ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2294         debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2295         ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2296         debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2297
2298 }
2299
2300 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
2301 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
2302 {
2303         /* Self Refresh Idle Threshold */
2304         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2305 }
2306
2307 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2308 {
2309         if (popts->addr_hash) {
2310                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
2311                 puts("Address hashing enabled.\n");
2312         }
2313 }
2314
2315 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2316 {
2317         ddr->ddr_cdr1 = popts->ddr_cdr1;
2318         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2319 }
2320
2321 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2322 {
2323         ddr->ddr_cdr2 = popts->ddr_cdr2;
2324         debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2325 }
2326
2327 unsigned int
2328 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2329 {
2330         unsigned int res = 0;
2331
2332         /*
2333          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2334          * not set at the same time.
2335          */
2336         if (ddr->ddr_sdram_cfg & 0x10000000
2337             && ddr->ddr_sdram_cfg & 0x00008000) {
2338                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2339                                 " should not be set at the same time.\n");
2340                 res++;
2341         }
2342
2343         return res;
2344 }
2345
2346 unsigned int
2347 compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
2348                                const memctl_options_t *popts,
2349                                fsl_ddr_cfg_regs_t *ddr,
2350                                const common_timing_params_t *common_dimm,
2351                                const dimm_params_t *dimm_params,
2352                                unsigned int dbw_cap_adj,
2353                                unsigned int size_only)
2354 {
2355         unsigned int i;
2356         unsigned int cas_latency;
2357         unsigned int additive_latency;
2358         unsigned int sr_it;
2359         unsigned int zq_en;
2360         unsigned int wrlvl_en;
2361         unsigned int ip_rev = 0;
2362         unsigned int unq_mrs_en = 0;
2363         int cs_en = 1;
2364 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2365         unsigned int ddr_freq;
2366 #endif
2367 #if (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
2368         defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
2369         defined(CONFIG_SYS_FSL_ERRATUM_A009942)
2370         struct ccsr_ddr __iomem *ddrc;
2371
2372         switch (ctrl_num) {
2373         case 0:
2374                 ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR;
2375                 break;
2376 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
2377         case 1:
2378                 ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
2379                 break;
2380 #endif
2381 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
2382         case 2:
2383                 ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
2384                 break;
2385 #endif
2386 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
2387         case 3:
2388                 ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
2389                 break;
2390 #endif
2391         default:
2392                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
2393                 return 1;
2394         }
2395 #endif
2396
2397         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2398
2399         if (common_dimm == NULL) {
2400                 printf("Error: subset DIMM params struct null pointer\n");
2401                 return 1;
2402         }
2403
2404         /*
2405          * Process overrides first.
2406          *
2407          * FIXME: somehow add dereated caslat to this
2408          */
2409         cas_latency = (popts->cas_latency_override)
2410                 ? popts->cas_latency_override_value
2411                 : common_dimm->lowest_common_spd_caslat;
2412
2413         additive_latency = (popts->additive_latency_override)
2414                 ? popts->additive_latency_override_value
2415                 : common_dimm->additive_latency;
2416
2417         sr_it = (popts->auto_self_refresh_en)
2418                 ? popts->sr_it
2419                 : 0;
2420         /* ZQ calibration */
2421         zq_en = (popts->zq_en) ? 1 : 0;
2422         /* write leveling */
2423         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
2424
2425         /* Chip Select Memory Bounds (CSn_BNDS) */
2426         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
2427                 unsigned long long ea, sa;
2428                 unsigned int cs_per_dimm
2429                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2430                 unsigned int dimm_number
2431                         = i / cs_per_dimm;
2432                 unsigned long long rank_density
2433                         = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
2434
2435                 if (dimm_params[dimm_number].n_ranks == 0) {
2436                         debug("Skipping setup of CS%u "
2437                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
2438                         continue;
2439                 }
2440                 if (popts->memctl_interleaving) {
2441                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2442                         case FSL_DDR_CS0_CS1_CS2_CS3:
2443                                 break;
2444                         case FSL_DDR_CS0_CS1:
2445                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2446                                 if (i > 1)
2447                                         cs_en = 0;
2448                                 break;
2449                         case FSL_DDR_CS2_CS3:
2450                         default:
2451                                 if (i > 0)
2452                                         cs_en = 0;
2453                                 break;
2454                         }
2455                         sa = common_dimm->base_address;
2456                         ea = sa + common_dimm->total_mem - 1;
2457                 } else if (!popts->memctl_interleaving) {
2458                         /*
2459                          * If memory interleaving between controllers is NOT
2460                          * enabled, the starting address for each memory
2461                          * controller is distinct.  However, because rank
2462                          * interleaving is enabled, the starting and ending
2463                          * addresses of the total memory on that memory
2464                          * controller needs to be programmed into its
2465                          * respective CS0_BNDS.
2466                          */
2467                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2468                         case FSL_DDR_CS0_CS1_CS2_CS3:
2469                                 sa = common_dimm->base_address;
2470                                 ea = sa + common_dimm->total_mem - 1;
2471                                 break;
2472                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2473                                 if ((i >= 2) && (dimm_number == 0)) {
2474                                         sa = dimm_params[dimm_number].base_address +
2475                                               2 * rank_density;
2476                                         ea = sa + 2 * rank_density - 1;
2477                                 } else {
2478                                         sa = dimm_params[dimm_number].base_address;
2479                                         ea = sa + 2 * rank_density - 1;
2480                                 }
2481                                 break;
2482                         case FSL_DDR_CS0_CS1:
2483                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2484                                         sa = dimm_params[dimm_number].base_address;
2485                                         ea = sa + rank_density - 1;
2486                                         if (i != 1)
2487                                                 sa += (i % cs_per_dimm) * rank_density;
2488                                         ea += (i % cs_per_dimm) * rank_density;
2489                                 } else {
2490                                         sa = 0;
2491                                         ea = 0;
2492                                 }
2493                                 if (i == 0)
2494                                         ea += rank_density;
2495                                 break;
2496                         case FSL_DDR_CS2_CS3:
2497                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2498                                         sa = dimm_params[dimm_number].base_address;
2499                                         ea = sa + rank_density - 1;
2500                                         if (i != 3)
2501                                                 sa += (i % cs_per_dimm) * rank_density;
2502                                         ea += (i % cs_per_dimm) * rank_density;
2503                                 } else {
2504                                         sa = 0;
2505                                         ea = 0;
2506                                 }
2507                                 if (i == 2)
2508                                         ea += (rank_density >> dbw_cap_adj);
2509                                 break;
2510                         default:  /* No bank(chip-select) interleaving */
2511                                 sa = dimm_params[dimm_number].base_address;
2512                                 ea = sa + rank_density - 1;
2513                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2514                                         sa += (i % cs_per_dimm) * rank_density;
2515                                         ea += (i % cs_per_dimm) * rank_density;
2516                                 } else {
2517                                         sa = 0;
2518                                         ea = 0;
2519                                 }
2520                                 break;
2521                         }
2522                 }
2523
2524                 sa >>= 24;
2525                 ea >>= 24;
2526
2527                 if (cs_en) {
2528                         ddr->cs[i].bnds = (0
2529                                 | ((sa & 0xffff) << 16) /* starting address */
2530                                 | ((ea & 0xffff) << 0)  /* ending address */
2531                                 );
2532                 } else {
2533                         /* setting bnds to 0xffffffff for inactive CS */
2534                         ddr->cs[i].bnds = 0xffffffff;
2535                 }
2536
2537                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
2538                 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2539                 set_csn_config_2(i, ddr);
2540         }
2541
2542         /*
2543          * In the case we only need to compute the ddr sdram size, we only need
2544          * to set csn registers, so return from here.
2545          */
2546         if (size_only)
2547                 return 0;
2548
2549         set_ddr_eor(ddr, popts);
2550
2551 #if !defined(CONFIG_SYS_FSL_DDR1)
2552         set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
2553 #endif
2554
2555         set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
2556                          additive_latency);
2557         set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
2558         set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
2559                          cas_latency, additive_latency);
2560
2561         set_ddr_cdr1(ddr, popts);
2562         set_ddr_cdr2(ddr, popts);
2563         set_ddr_sdram_cfg(ddr, popts, common_dimm);
2564         ip_rev = fsl_ddr_get_version(ctrl_num);
2565         if (ip_rev > 0x40400)
2566                 unq_mrs_en = 1;
2567
2568         if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
2569                 ddr->debug[18] = popts->cswl_override;
2570
2571         set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
2572         set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
2573                            cas_latency, additive_latency, unq_mrs_en);
2574         set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2575 #ifdef CONFIG_SYS_FSL_DDR4
2576         set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2577         set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2578 #endif
2579         set_ddr_sdram_rcw(ctrl_num, ddr, popts, common_dimm);
2580
2581         set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
2582         set_ddr_data_init(ddr);
2583         set_ddr_sdram_clk_cntl(ddr, popts);
2584         set_ddr_init_addr(ddr);
2585         set_ddr_init_ext_addr(ddr);
2586         set_timing_cfg_4(ddr, popts);
2587         set_timing_cfg_5(ddr, cas_latency);
2588 #ifdef CONFIG_SYS_FSL_DDR4
2589         set_ddr_sdram_cfg_3(ddr, popts);
2590         set_timing_cfg_6(ddr);
2591         set_timing_cfg_7(ctrl_num, ddr, popts, common_dimm);
2592         set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
2593         set_timing_cfg_9(ctrl_num, ddr, popts, common_dimm);
2594         set_ddr_dq_mapping(ddr, dimm_params);
2595 #endif
2596
2597         set_ddr_zq_cntl(ddr, zq_en);
2598         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
2599
2600         set_ddr_sr_cntr(ddr, sr_it);
2601
2602 #ifdef CONFIG_SYS_FSL_DDR_EMU
2603         /* disble DDR training for emulator */
2604         ddr->debug[2] = 0x00000400;
2605         ddr->debug[4] = 0xff800800;
2606         ddr->debug[5] = 0x08000800;
2607         ddr->debug[6] = 0x08000800;
2608         ddr->debug[7] = 0x08000800;
2609         ddr->debug[8] = 0x08000800;
2610 #endif
2611 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2612         if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2613                 ddr->debug[2] |= 0x00000200;    /* set bit 22 */
2614 #endif
2615
2616 #if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
2617         /* Erratum applies when accumulated ECC is used, or DBI is enabled */
2618 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
2619 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
2620         if (has_erratum_a008378()) {
2621                 if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) ||
2622                     IS_DBI(ddr->ddr_sdram_cfg_3)) {
2623                         ddr->debug[28] = ddr_in32(&ddrc->debug[28]);
2624                         ddr->debug[28] |= (0x9 << 20);
2625                 }
2626         }
2627 #endif
2628
2629 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2630         ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
2631         ddr->debug[28] |= ddr_in32(&ddrc->debug[28]);
2632         ddr->debug[28] &= 0xff0fff00;
2633         if (ddr_freq <= 1333)
2634                 ddr->debug[28] |= 0x0080006a;
2635         else if (ddr_freq <= 1600)
2636                 ddr->debug[28] |= 0x0070006f;
2637         else if (ddr_freq <= 1867)
2638                 ddr->debug[28] |= 0x00700076;
2639         else if (ddr_freq <= 2133)
2640                 ddr->debug[28] |= 0x0060007b;
2641         if (popts->cpo_sample)
2642                 ddr->debug[28] = (ddr->debug[28] & 0xffffff00) |
2643                                   popts->cpo_sample;
2644 #endif
2645
2646         return check_fsl_memctl_config_regs(ddr);
2647 }
2648
2649 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2650 /*
2651  * This additional workaround of A009942 checks the condition to determine if
2652  * the CPO value set by the existing A009942 workaround needs to be updated.
2653  * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with
2654  * expected optimal value, the optimal value is highly board dependent.
2655  */
2656 void erratum_a009942_check_cpo(void)
2657 {
2658         struct ccsr_ddr __iomem *ddr =
2659                 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
2660         u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal;
2661         u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24;
2662         u32 cpo_max = cpo_min;
2663         u32 sdram_cfg, i, tmp, lanes, ddr_type;
2664         bool update_cpo = false, has_ecc = false;
2665
2666         sdram_cfg = ddr_in32(&ddr->sdram_cfg);
2667         if (sdram_cfg & SDRAM_CFG_32_BE)
2668                 lanes = 4;
2669         else if (sdram_cfg & SDRAM_CFG_16_BE)
2670                 lanes = 2;
2671         else
2672                 lanes = 8;
2673
2674         if (sdram_cfg & SDRAM_CFG_ECC_EN)
2675                 has_ecc = true;
2676
2677         /* determine the maximum and minimum CPO values */
2678         for (i = 9; i < 9 + lanes / 2; i++) {
2679                 cpo = ddr_in32(&ddr->debug[i]);
2680                 cpo_e = cpo >> 24;
2681                 cpo_o = (cpo >> 8) & 0xff;
2682                 tmp = min(cpo_e, cpo_o);
2683                 if (tmp < cpo_min)
2684                         cpo_min = tmp;
2685                 tmp = max(cpo_e, cpo_o);
2686                 if (tmp > cpo_max)
2687                         cpo_max = tmp;
2688         }
2689
2690         if (has_ecc) {
2691                 cpo = ddr_in32(&ddr->debug[13]);
2692                 cpo = cpo >> 24;
2693                 if (cpo < cpo_min)
2694                         cpo_min = cpo;
2695                 if (cpo > cpo_max)
2696                         cpo_max = cpo;
2697         }
2698
2699         cpo_target = ddr_in32(&ddr->debug[28]) & 0xff;
2700         cpo_optimal = ((cpo_max + cpo_min) >> 1) + 0x27;
2701         debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal,
2702               cpo_target);
2703         debug("cpo_max = 0x%x, cpo_min = 0x%x\n", cpo_max, cpo_min);
2704
2705         ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
2706                     SDRAM_CFG_SDRAM_TYPE_SHIFT;
2707         if (ddr_type == SDRAM_TYPE_DDR4)
2708                 update_cpo = (cpo_min + 0x3b) < cpo_target ? true : false;
2709         else if (ddr_type == SDRAM_TYPE_DDR3)
2710                 update_cpo = (cpo_min + 0x3f) < cpo_target ? true : false;
2711
2712         if (update_cpo) {
2713                 printf("WARN: pls set popts->cpo_sample = 0x%x ", cpo_optimal);
2714                 printf("in <board>/ddr.c to optimize cpo\n");
2715         }
2716 }
2717 #endif