drivers/crypto/fsl/jr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   4  * Copyright 2018, 2021 NXP
   5  *
   6  * Based on CAAM driver in drivers/crypto/caam in Linux
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <linux/kernel.h>
  12 #include <log.h>
  13 #include <malloc.h>
  14 #include <power-domain.h>
  15 #include "jr.h"
  16 #include "jobdesc.h"
  17 #include "desc_constr.h"
  18 #include <time.h>
  19 #include <asm/cache.h>
  20 #ifdef CONFIG_FSL_CORENET
  21 #include <asm/cache.h>
  22 #include <asm/fsl_pamu.h>
  23 #endif
  24 #include <dm.h>
  25 #include <dm/lists.h>
  26 #include <dm/root.h>
  27 #include <dm/device-internal.h>
  28 #include <linux/delay.h>
  29
  30 #define CIRC_CNT(head, tail, size)      (((head) - (tail)) & (size - 1))
  31 #define CIRC_SPACE(head, tail, size)    CIRC_CNT((tail), (head) + 1, (size))
  32
  33 uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
  34         0,
  35 #if defined(CONFIG_ARCH_C29X)
  36         CFG_SYS_FSL_SEC_IDX_OFFSET,
  37         2 * CFG_SYS_FSL_SEC_IDX_OFFSET
  38 #endif
  39 };
  40
  41 #if CONFIG_IS_ENABLED(DM)
  42 struct udevice *caam_dev;
  43 #else
  44 #define SEC_ADDR(idx)   \
  45         (ulong)((CFG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
  46
  47 #define SEC_JR0_ADDR(idx)       \
  48         (ulong)(SEC_ADDR(idx) + \
  49          (CFG_SYS_FSL_JR0_OFFSET - CFG_SYS_FSL_SEC_OFFSET))
  50 struct caam_regs caam_st;
  51 #endif
  52
  53 static inline u32 jr_start_reg(u8 jrid)
  54 {
  55         return (1 << jrid);
  56 }
  57
  58 static inline void start_jr(struct caam_regs *caam)
  59 {
  60         ccsr_sec_t *sec = caam->sec;
  61         u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
  62         u32 scfgr = sec_in32(&sec->scfgr);
  63         u32 jrstart = jr_start_reg(caam->jrid);
  64
  65         if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
  66                 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
  67                  * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
  68                  */
  69                 if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
  70                     (scfgr & SEC_SCFGR_VIRT_EN))
  71                         sec_out32(&sec->jrstartr, jrstart);
  72         } else {
  73                 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
  74                 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
  75                         sec_out32(&sec->jrstartr, jrstart);
  76         }
  77 }
  78
  79 static inline void jr_disable_irq(struct jr_regs *regs)
  80 {
  81         uint32_t jrcfg = sec_in32(&regs->jrcfg1);
  82
  83         jrcfg = jrcfg | JR_INTMASK;
  84
  85         sec_out32(&regs->jrcfg1, jrcfg);
  86 }
  87
  88 static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam)
  89 {
  90         struct jr_regs *regs = caam->regs;
  91         struct jobring *jr = &caam->jr[sec_idx];
  92         caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
  93         caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring);
  94
  95 #ifdef CONFIG_CAAM_64BIT
  96         sec_out32(&regs->irba_h, ip_base >> 32);
  97 #else
  98         sec_out32(&regs->irba_h, 0x0);
  99 #endif
 100         sec_out32(&regs->irba_l, (uint32_t)ip_base);
 101 #ifdef CONFIG_CAAM_64BIT
 102         sec_out32(&regs->orba_h, op_base >> 32);
 103 #else
 104         sec_out32(&regs->orba_h, 0x0);
 105 #endif
 106         sec_out32(&regs->orba_l, (uint32_t)op_base);
 107         sec_out32(&regs->ors, JR_SIZE);
 108         sec_out32(&regs->irs, JR_SIZE);
 109
 110         if (!jr->irq)
 111                 jr_disable_irq(regs);
 112 }
 113
 114 static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
 115 {
 116         struct jobring *jr = &caam->jr[sec_idx];
 117 #if CONFIG_IS_ENABLED(OF_CONTROL)
 118         ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
 119 #endif
 120         memset(jr, 0, sizeof(struct jobring));
 121
 122         jr->jq_id = caam->jrid;
 123         jr->irq = DEFAULT_IRQ;
 124
 125 #ifdef CONFIG_FSL_CORENET
 126         jr->liodn = DEFAULT_JR_LIODN;
 127 #endif
 128         jr->size = JR_SIZE;
 129         jr->input_ring = (caam_dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
 130                                 JR_SIZE * sizeof(caam_dma_addr_t));
 131         if (!jr->input_ring)
 132                 return -1;
 133
 134         jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring),
 135                               ARCH_DMA_MINALIGN);
 136         jr->output_ring =
 137             (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size);
 138         if (!jr->output_ring)
 139                 return -1;
 140
 141         memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
 142         memset(jr->output_ring, 0, jr->op_size);
 143
 144 #if CONFIG_IS_ENABLED(OF_CONTROL)
 145         if (!ofnode_valid(scu_node))
 146 #endif
 147         start_jr(caam);
 148
 149         jr_initregs(sec_idx, caam);
 150
 151         return 0;
 152 }
 153
 154 /* -1 --- error, can't enqueue -- no space available */
 155 static int jr_enqueue(uint32_t *desc_addr,
 156                void (*callback)(uint32_t status, void *arg),
 157                void *arg, uint8_t sec_idx, struct caam_regs *caam)
 158 {
 159         struct jr_regs *regs = caam->regs;
 160         struct jobring *jr = &caam->jr[sec_idx];
 161         int head = jr->head;
 162         uint32_t desc_word;
 163         int length = desc_len(desc_addr);
 164         int i;
 165 #ifdef CONFIG_CAAM_64BIT
 166         uint32_t *addr_hi, *addr_lo;
 167 #endif
 168
 169         /* The descriptor must be submitted to SEC block as per endianness
 170          * of the SEC Block.
 171          * So, if the endianness of Core and SEC block is different, each word
 172          * of the descriptor will be byte-swapped.
 173          */
 174         for (i = 0; i < length; i++) {
 175                 desc_word = desc_addr[i];
 176                 sec_out32((uint32_t *)&desc_addr[i], desc_word);
 177         }
 178
 179         caam_dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
 180
 181         jr->info[head].desc_phys_addr = desc_phys_addr;
 182         jr->info[head].callback = (void *)callback;
 183         jr->info[head].arg = arg;
 184         jr->info[head].op_done = 0;
 185
 186         unsigned long start = (unsigned long)&jr->info[head] &
 187                                         ~(ARCH_DMA_MINALIGN - 1);
 188         unsigned long end = ALIGN((unsigned long)&jr->info[head] +
 189                                   sizeof(struct jr_info), ARCH_DMA_MINALIGN);
 190         flush_dcache_range(start, end);
 191
 192 #ifdef CONFIG_CAAM_64BIT
 193         /* Write the 64 bit Descriptor address on Input Ring.
 194          * The 32 bit hign and low part of the address will
 195          * depend on endianness of SEC block.
 196          */
 197 #ifdef CONFIG_SYS_FSL_SEC_LE
 198         addr_lo = (uint32_t *)(&jr->input_ring[head]);
 199         addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1;
 200 #elif defined(CONFIG_SYS_FSL_SEC_BE)
 201         addr_hi = (uint32_t *)(&jr->input_ring[head]);
 202         addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1;
 203 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
 204
 205         sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
 206         sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
 207
 208 #else
 209         /* Write the 32 bit Descriptor address on Input Ring. */
 210         sec_out32(&jr->input_ring[head], desc_phys_addr);
 211 #endif /* ifdef CONFIG_CAAM_64BIT */
 212
 213         start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
 214         end = ALIGN((unsigned long)&jr->input_ring[head] +
 215                      sizeof(caam_dma_addr_t), ARCH_DMA_MINALIGN);
 216         flush_dcache_range(start, end);
 217
 218         jr->head = (head + 1) & (jr->size - 1);
 219
 220         /* Invalidate output ring */
 221         start = (unsigned long)jr->output_ring &
 222                                         ~(ARCH_DMA_MINALIGN - 1);
 223         end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
 224                     ARCH_DMA_MINALIGN);
 225         invalidate_dcache_range(start, end);
 226
 227         sec_out32(&regs->irja, 1);
 228
 229         return 0;
 230 }
 231
 232 static int jr_dequeue(int sec_idx, struct caam_regs *caam)
 233 {
 234         struct jr_regs *regs = caam->regs;
 235         struct jobring *jr = &caam->jr[sec_idx];
 236         int head = jr->head;
 237         int tail = jr->tail;
 238         int idx, i, found;
 239         void (*callback)(uint32_t status, void *arg);
 240         void *arg = NULL;
 241 #ifdef CONFIG_CAAM_64BIT
 242         uint32_t *addr_hi, *addr_lo;
 243 #else
 244         uint32_t *addr;
 245 #endif
 246
 247         while (sec_in32(&regs->orsf) && CIRC_CNT(jr->head, jr->tail,
 248                                                  jr->size)) {
 249
 250                 found = 0;
 251
 252                 caam_dma_addr_t op_desc;
 253         #ifdef CONFIG_CAAM_64BIT
 254                 /* Read the 64 bit Descriptor address from Output Ring.
 255                  * The 32 bit hign and low part of the address will
 256                  * depend on endianness of SEC block.
 257                  */
 258         #ifdef CONFIG_SYS_FSL_SEC_LE
 259                 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc);
 260                 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
 261         #elif defined(CONFIG_SYS_FSL_SEC_BE)
 262                 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc);
 263                 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
 264         #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
 265
 266                 op_desc = ((u64)sec_in32(addr_hi) << 32) |
 267                           ((u64)sec_in32(addr_lo));
 268
 269         #else
 270                 /* Read the 32 bit Descriptor address from Output Ring. */
 271                 addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
 272                 op_desc = sec_in32(addr);
 273         #endif /* ifdef CONFIG_CAAM_64BIT */
 274
 275                 uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);
 276
 277                 for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) {
 278                         idx = (tail + i) & (jr->size - 1);
 279                         if (op_desc == jr->info[idx].desc_phys_addr) {
 280                                 found = 1;
 281                                 break;
 282                         }
 283                 }
 284
 285                 /* Error condition if match not found */
 286                 if (!found)
 287                         return -1;
 288
 289                 jr->info[idx].op_done = 1;
 290                 callback = (void *)jr->info[idx].callback;
 291                 arg = jr->info[idx].arg;
 292
 293                 /* When the job on tail idx gets done, increment
 294                  * tail till the point where job completed out of oredr has
 295                  * been taken into account
 296                  */
 297                 if (idx == tail)
 298                         do {
 299                                 tail = (tail + 1) & (jr->size - 1);
 300                         } while (jr->info[tail].op_done);
 301
 302                 jr->tail = tail;
 303                 jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
 304
 305                 sec_out32(&regs->orjr, 1);
 306                 jr->info[idx].op_done = 0;
 307
 308                 callback(status, arg);
 309         }
 310
 311         return 0;
 312 }
 313
 314 static void desc_done(uint32_t status, void *arg)
 315 {
 316         struct result *x = arg;
 317         x->status = status;
 318         caam_jr_strstatus(status);
 319         x->done = 1;
 320 }
 321
 322 static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
 323 {
 324         struct caam_regs *caam;
 325 #if CONFIG_IS_ENABLED(DM)
 326         caam = dev_get_priv(caam_dev);
 327 #else
 328         caam = &caam_st;
 329 #endif
 330         unsigned long long timeval = 0;
 331         unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
 332         struct result op;
 333         int ret = 0;
 334
 335         memset(&op, 0, sizeof(op));
 336
 337         ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam);
 338         if (ret) {
 339                 debug("Error in SEC enq\n");
 340                 ret = JQ_ENQ_ERR;
 341                 goto out;
 342         }
 343
 344         while (op.done != 1) {
 345                 udelay(1);
 346                 timeval += 1;
 347
 348                 ret = jr_dequeue(sec_idx, caam);
 349                 if (ret) {
 350                         debug("Error in SEC deq\n");
 351                         ret = JQ_DEQ_ERR;
 352                         goto out;
 353                 }
 354
 355                 if (timeval > timeout) {
 356                         debug("SEC Dequeue timed out\n");
 357                         ret = JQ_DEQ_TO_ERR;
 358                         goto out;
 359                 }
 360         }
 361
 362         if (op.status) {
 363                 debug("Error %x\n", op.status);
 364                 ret = op.status;
 365         }
 366 out:
 367         return ret;
 368 }
 369
 370 int run_descriptor_jr(uint32_t *desc)
 371 {
 372         return run_descriptor_jr_idx(desc, 0);
 373 }
 374
 375 static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam)
 376 {
 377         struct jobring *jr = &caam->jr[sec_idx];
 378
 379         jr->head = 0;
 380         jr->tail = 0;
 381         jr->read_idx = 0;
 382         jr->write_idx = 0;
 383         memset(jr->info, 0, sizeof(jr->info));
 384         memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
 385         memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
 386
 387         return 0;
 388 }
 389
 390 static int jr_hw_reset(struct jr_regs *regs)
 391 {
 392         uint32_t timeout = 100000;
 393         uint32_t jrint, jrcr;
 394
 395         sec_out32(&regs->jrcr, JRCR_RESET);
 396         do {
 397                 jrint = sec_in32(&regs->jrint);
 398         } while (((jrint & JRINT_ERR_HALT_MASK) ==
 399                   JRINT_ERR_HALT_INPROGRESS) && --timeout);
 400
 401         jrint = sec_in32(&regs->jrint);
 402         if (((jrint & JRINT_ERR_HALT_MASK) !=
 403              JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
 404                 return -1;
 405
 406         timeout = 100000;
 407         sec_out32(&regs->jrcr, JRCR_RESET);
 408         do {
 409                 jrcr = sec_in32(&regs->jrcr);
 410         } while ((jrcr & JRCR_RESET) && --timeout);
 411
 412         if (timeout == 0)
 413                 return -1;
 414
 415         return 0;
 416 }
 417
 418 static inline int jr_reset_sec(uint8_t sec_idx)
 419 {
 420         struct caam_regs *caam;
 421 #if CONFIG_IS_ENABLED(DM)
 422         caam = dev_get_priv(caam_dev);
 423 #else
 424         caam = &caam_st;
 425 #endif
 426         if (jr_hw_reset(caam->regs) < 0)
 427                 return -1;
 428
 429         /* Clean up the jobring structure maintained by software */
 430         jr_sw_cleanup(sec_idx, caam);
 431
 432         return 0;
 433 }
 434
 435 int jr_reset(void)
 436 {
 437         return jr_reset_sec(0);
 438 }
 439
 440 int sec_reset(void)
 441 {
 442         struct caam_regs *caam;
 443 #if CONFIG_IS_ENABLED(DM)
 444         caam = dev_get_priv(caam_dev);
 445 #else
 446         caam = &caam_st;
 447 #endif
 448         ccsr_sec_t *sec = caam->sec;
 449         uint32_t mcfgr = sec_in32(&sec->mcfgr);
 450         uint32_t timeout = 100000;
 451
 452         mcfgr |= MCFGR_SWRST;
 453         sec_out32(&sec->mcfgr, mcfgr);
 454
 455         mcfgr |= MCFGR_DMA_RST;
 456         sec_out32(&sec->mcfgr, mcfgr);
 457         do {
 458                 mcfgr = sec_in32(&sec->mcfgr);
 459         } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
 460
 461         if (timeout == 0)
 462                 return -1;
 463
 464         timeout = 100000;
 465         do {
 466                 mcfgr = sec_in32(&sec->mcfgr);
 467         } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
 468
 469         if (timeout == 0)
 470                 return -1;
 471
 472         return 0;
 473 }
 474
 475 static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
 476 {
 477         u32 *desc;
 478         int sh_idx, ret = 0;
 479         int desc_size = ALIGN(sizeof(u32) * 2, ARCH_DMA_MINALIGN);
 480
 481         desc = memalign(ARCH_DMA_MINALIGN, desc_size);
 482         if (!desc) {
 483                 debug("cannot allocate RNG init descriptor memory\n");
 484                 return -ENOMEM;
 485         }
 486
 487         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 488                 /*
 489                  * If the corresponding bit is set, then it means the state
 490                  * handle was initialized by us, and thus it needs to be
 491                  * deinitialized as well
 492                  */
 493
 494                 if (state_handle_mask & RDSTA_IF(sh_idx)) {
 495                         /*
 496                          * Create the descriptor for deinstantating this state
 497                          * handle.
 498                          */
 499                         inline_cnstr_jobdesc_rng_deinstantiation(desc, sh_idx);
 500                         flush_dcache_range((unsigned long)desc,
 501                                            (unsigned long)desc + desc_size);
 502
 503                         ret = run_descriptor_jr_idx(desc, sec_idx);
 504                         if (ret) {
 505                                 printf("SEC%u:  RNG4 SH%d deinstantiation failed with error 0x%x\n",
 506                                        sec_idx, sh_idx, ret);
 507                                 ret = -EIO;
 508                                 break;
 509                         }
 510
 511                         printf("SEC%u:  Deinstantiated RNG4 SH%d\n",
 512                                sec_idx, sh_idx);
 513                 }
 514         }
 515
 516         free(desc);
 517         return ret;
 518 }
 519
 520 static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec, int gen_sk)
 521 {
 522         u32 *desc;
 523         u32 rdsta_val;
 524         int ret = 0, sh_idx, size;
 525         struct rng4tst __iomem *rng =
 526                         (struct rng4tst __iomem *)&sec->rng;
 527
 528         desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
 529         if (!desc) {
 530                 printf("cannot allocate RNG init descriptor memory\n");
 531                 return -1;
 532         }
 533
 534         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 535                 /*
 536                  * If the corresponding bit is set, this state handle
 537                  * was initialized by somebody else, so it's left alone.
 538                  */
 539                 rdsta_val = sec_in32(&rng->rdsta);
 540                 if (rdsta_val & (RDSTA_IF(sh_idx))) {
 541                         if (rdsta_val & RDSTA_PR(sh_idx))
 542                                 continue;
 543
 544                         printf("SEC%u:  RNG4 SH%d was instantiated w/o prediction resistance. Tearing it down\n",
 545                                sec_idx, sh_idx);
 546
 547                         ret = deinstantiate_rng(sec_idx, RDSTA_IF(sh_idx));
 548                         if (ret)
 549                                 break;
 550                 }
 551
 552                 inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx, gen_sk);
 553                 size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
 554                 flush_dcache_range((unsigned long)desc,
 555                                    (unsigned long)desc + size);
 556
 557                 ret = run_descriptor_jr_idx(desc, sec_idx);
 558
 559                 if (ret)
 560                         printf("SEC%u:  RNG4 SH%d instantiation failed with error 0x%x\n",
 561                                sec_idx, sh_idx, ret);
 562
 563                 rdsta_val = sec_in32(&rng->rdsta);
 564                 if (!(rdsta_val & RDSTA_IF(sh_idx))) {
 565                         free(desc);
 566                         return -1;
 567                 }
 568
 569                 memset(desc, 0, sizeof(uint32_t) * 6);
 570         }
 571
 572         free(desc);
 573
 574         return ret;
 575 }
 576
 577 static u8 get_rng_vid(ccsr_sec_t *sec)
 578 {
 579         u8 vid;
 580
 581         if (caam_get_era() < 10) {
 582                 vid = (sec_in32(&sec->chavid_ls) & SEC_CHAVID_RNG_LS_MASK)
 583                        >> SEC_CHAVID_LS_RNG_SHIFT;
 584         } else {
 585                 vid = (sec_in32(&sec->vreg.rng) & CHA_VER_VID_MASK)
 586                        >> CHA_VER_VID_SHIFT;
 587         }
 588
 589         return vid;
 590 }
 591
 592 /*
 593  * By default, the TRNG runs for 200 clocks per sample;
 594  * 1200 clocks per sample generates better entropy.
 595  */
 596 static void kick_trng(int ent_delay, ccsr_sec_t *sec)
 597 {
 598         struct rng4tst __iomem *rng =
 599                         (struct rng4tst __iomem *)&sec->rng;
 600         u32 val;
 601
 602         /* put RNG4 into program mode */
 603         sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
 604         /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
 605          * length (in system clocks) of each Entropy sample taken
 606          * */
 607         val = sec_in32(&rng->rtsdctl);
 608         val = (val & ~RTSDCTL_ENT_DLY_MASK) |
 609               (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
 610         sec_out32(&rng->rtsdctl, val);
 611         /* min. freq. count, equal to 1/4 of the entropy sample length */
 612         sec_out32(&rng->rtfreqmin, ent_delay >> 2);
 613         /* disable maximum frequency count */
 614         sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
 615         /*
 616          * select raw sampling in both entropy shifter
 617          * and statistical checker
 618          */
 619         sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
 620         /* put RNG4 into run mode */
 621         sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
 622 }
 623
 624 static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
 625 {
 626         int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY;
 627         struct rng4tst __iomem *rng =
 628                         (struct rng4tst __iomem *)&sec->rng;
 629         u32 inst_handles;
 630
 631         gen_sk = !(sec_in32(&rng->rdsta) & RDSTA_SKVN);
 632         do {
 633                 inst_handles = sec_in32(&rng->rdsta) & RDSTA_MASK;
 634
 635                 /*
 636                  * If either of the SH's were instantiated by somebody else
 637                  * then it is assumed that the entropy
 638                  * parameters are properly set and thus the function
 639                  * setting these (kick_trng(...)) is skipped.
 640                  * Also, if a handle was instantiated, do not change
 641                  * the TRNG parameters.
 642                  */
 643                 if (!inst_handles) {
 644                         kick_trng(ent_delay, sec);
 645                         ent_delay += 400;
 646                 }
 647                 /*
 648                  * if instantiate_rng(...) fails, the loop will rerun
 649                  * and the kick_trng(...) function will modfiy the
 650                  * upper and lower limits of the entropy sampling
 651                  * interval, leading to a sucessful initialization of
 652                  * the RNG.
 653                  */
 654                 ret = instantiate_rng(sec_idx, sec, gen_sk);
 655                 /*
 656                  * entropy delay is calculated via self-test method.
 657                  * self-test are run across different volatge, temp.
 658                  * if worst case value for ent_dly is identified,
 659                  * loop can be skipped for that platform.
 660                  */
 661                 if (IS_ENABLED(CONFIG_MX6SX))
 662                         break;
 663
 664         } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
 665         if (ret) {
 666                 printf("SEC%u:  Failed to instantiate RNG\n", sec_idx);
 667                 return ret;
 668         }
 669
 670          /* Enable RDB bit so that RNG works faster */
 671         sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
 672
 673         return ret;
 674 }
 675
 676 int sec_init_idx(uint8_t sec_idx)
 677 {
 678         int ret = 0;
 679         struct caam_regs *caam;
 680 #if CONFIG_IS_ENABLED(DM)
 681         if (!caam_dev) {
 682                 printf("caam_jr: caam not found\n");
 683                 return -1;
 684         }
 685         caam = dev_get_priv(caam_dev);
 686 #else
 687         caam_st.sec = (void *)SEC_ADDR(sec_idx);
 688         caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
 689         caam_st.jrid = 0;
 690         caam = &caam_st;
 691 #endif
 692 #if CONFIG_IS_ENABLED(OF_CONTROL)
 693         ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
 694
 695         if (ofnode_valid(scu_node))
 696                 goto init;
 697 #endif
 698
 699         ccsr_sec_t *sec = caam->sec;
 700         uint32_t mcr = sec_in32(&sec->mcfgr);
 701 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
 702         uint32_t jrdid_ms = 0;
 703 #endif
 704 #ifdef CONFIG_FSL_CORENET
 705         uint32_t liodnr;
 706         uint32_t liodn_ns;
 707         uint32_t liodn_s;
 708 #endif
 709
 710         if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
 711                 printf("SEC%u:  initialization failed\n", sec_idx);
 712                 return -1;
 713         }
 714
 715         /*
 716          * Modifying CAAM Read/Write Attributes
 717          * For LS2080A
 718          * For AXI Write - Cacheable, Write Back, Write allocate
 719          * For AXI Read - Cacheable, Read allocate
 720          * Only For LS2080a, to solve CAAM coherency issues
 721          */
 722 #ifdef CONFIG_ARCH_LS2080A
 723         mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
 724         mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
 725 #else
 726         mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
 727 #endif
 728
 729 #ifdef CONFIG_CAAM_64BIT
 730         mcr |= (1 << MCFGR_PS_SHIFT);
 731 #endif
 732         sec_out32(&sec->mcfgr, mcr);
 733 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
 734         jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ | JRDID_MS_PRIM_DID;
 735         sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms);
 736 #endif
 737         jr_reset();
 738
 739 #ifdef CONFIG_FSL_CORENET
 740 #ifdef CONFIG_SPL_BUILD
 741         /*
 742          * For SPL Build, Set the Liodns in SEC JR0 for
 743          * creating PAMU entries corresponding to these.
 744          * For normal build, these are set in set_liodns().
 745          */
 746         liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
 747         liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
 748
 749         liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
 750                  ~(JRNSLIODN_MASK | JRSLIODN_MASK);
 751         liodnr = liodnr |
 752                  (liodn_ns << JRNSLIODN_SHIFT) |
 753                  (liodn_s << JRSLIODN_SHIFT);
 754         sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr);
 755 #else
 756         liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls);
 757         liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
 758         liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
 759 #endif
 760 #endif
 761 #if CONFIG_IS_ENABLED(OF_CONTROL)
 762 init:
 763 #endif
 764         ret = jr_init(sec_idx, caam);
 765         if (ret < 0) {
 766                 printf("SEC%u:  initialization failed\n", sec_idx);
 767                 return -1;
 768         }
 769 #if CONFIG_IS_ENABLED(OF_CONTROL)
 770         if (ofnode_valid(scu_node)) {
 771                 if (IS_ENABLED(CONFIG_DM_RNG)) {
 772                         ret = device_bind_driver(NULL, "caam-rng", "caam-rng", NULL);
 773                         if (ret)
 774                                 printf("Couldn't bind rng driver (%d)\n", ret);
 775                 }
 776                 return ret;
 777         }
 778 #endif
 779
 780 #ifdef CONFIG_FSL_CORENET
 781         ret = sec_config_pamu_table(liodn_ns, liodn_s);
 782         if (ret < 0)
 783                 return -1;
 784
 785         pamu_enable();
 786 #endif
 787
 788         if (get_rng_vid(caam->sec) >= 4) {
 789                 if (rng_init(sec_idx, caam->sec) < 0) {
 790                         printf("SEC%u:  RNG instantiation failed\n", sec_idx);
 791                         return -1;
 792                 }
 793
 794                 if (IS_ENABLED(CONFIG_DM_RNG)) {
 795                         ret = device_bind_driver(NULL, "caam-rng", "caam-rng",
 796                                                  NULL);
 797                         if (ret)
 798                                 printf("Couldn't bind rng driver (%d)\n", ret);
 799                 }
 800
 801                 printf("SEC%u:  RNG instantiated\n", sec_idx);
 802         }
 803         return ret;
 804 }
 805
 806 int sec_init(void)
 807 {
 808         return sec_init_idx(0);
 809 }
 810
 811 #if CONFIG_IS_ENABLED(DM)
 812 static int jr_power_on(ofnode node)
 813 {
 814 #if CONFIG_IS_ENABLED(POWER_DOMAIN)
 815         struct udevice __maybe_unused jr_dev;
 816         struct power_domain pd;
 817
 818         dev_set_ofnode(&jr_dev, node);
 819
 820         /* Power on Job Ring before access it */
 821         if (!power_domain_get(&jr_dev, &pd)) {
 822                 if (power_domain_on(&pd))
 823                         return -EINVAL;
 824         }
 825 #endif
 826         return 0;
 827 }
 828
 829 static int caam_jr_ioctl(struct udevice *dev, unsigned long request, void *buf)
 830 {
 831         if (request != CAAM_JR_RUN_DESC)
 832                 return -ENOSYS;
 833
 834         return run_descriptor_jr(buf);
 835 }
 836
 837 static int caam_jr_probe(struct udevice *dev)
 838 {
 839         struct caam_regs *caam = dev_get_priv(dev);
 840         fdt_addr_t addr;
 841         ofnode node, scu_node;
 842         unsigned int jr_node = 0;
 843
 844         caam_dev = dev;
 845
 846         addr = dev_read_addr(dev);
 847         if (addr == FDT_ADDR_T_NONE) {
 848                 printf("caam_jr: crypto not found\n");
 849                 return -EINVAL;
 850         }
 851         caam->sec = (ccsr_sec_t *)(uintptr_t)addr;
 852         caam->regs = (struct jr_regs *)caam->sec;
 853
 854         /* Check for enabled job ring node */
 855         ofnode_for_each_subnode(node, dev_ofnode(dev)) {
 856                 if (!ofnode_is_enabled(node))
 857                         continue;
 858
 859                 jr_node = ofnode_read_u32_default(node, "reg", -1);
 860                 if (jr_node > 0) {
 861                         caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node);
 862                         while (!(jr_node & 0x0F))
 863                                 jr_node = jr_node >> 4;
 864
 865                         caam->jrid = jr_node - 1;
 866                         scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
 867                         if (ofnode_valid(scu_node)) {
 868                                 if (jr_power_on(node))
 869                                         return -EINVAL;
 870                         }
 871                         break;
 872                 }
 873         }
 874
 875         if (sec_init())
 876                 printf("\nsec_init failed!\n");
 877
 878         return 0;
 879 }
 880
 881 static int caam_jr_bind(struct udevice *dev)
 882 {
 883         return 0;
 884 }
 885
 886 static const struct misc_ops caam_jr_ops = {
 887         .ioctl = caam_jr_ioctl,
 888 };
 889
 890 static const struct udevice_id caam_jr_match[] = {
 891         { .compatible = "fsl,sec-v4.0" },
 892         { }
 893 };
 894
 895 U_BOOT_DRIVER(caam_jr) = {
 896         .name           = "caam_jr",
 897         .id             = UCLASS_MISC,
 898         .of_match       = caam_jr_match,
 899         .ops            = &caam_jr_ops,
 900         .bind           = caam_jr_bind,
 901         .probe          = caam_jr_probe,
 902         .priv_auto      = sizeof(struct caam_regs),
 903 };
 904 #endif